include/opcode/ChangeLog

   1 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
   2             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
   3             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
   4             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
   5             Alan Modra  <amodra@bigpond.net.au>
   6
   7         * spu-insns.h: New file.
   8         * spu.h: New file.
   9
  10 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  11
  12         * ppc.h (PPC_OPCODE_CELL): Define.
  13
  14 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  15
  16         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  17         in amdfam10 architecture.
  18
  19 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         * i386.h: Replace CpuMNI with CpuSSSE3.
  22
  23 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  24             Joseph Myers  <joseph@codesourcery.com>
  25             Ian Lance Taylor  <ian@wasabisystems.com>
  26             Ben Elliston  <bje@wasabisystems.com>
  27
  28         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  29
  30 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  31
  32         * score-datadep.h: New file.
  33         * score-inst.h: New file.
  34
  35 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  38         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  39         movdq2q and movq2dq.
  40
  41 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  42            Michael Meissner             <michael.meissner@amd.com>
  43
  44         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  45
  46 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386.h (i386_optab): Add "nop" with memory reference.
  49
  50 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * i386.h (i386_optab): Update comment for 64bit NOP.
  53
  54 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  55             Anton Blanchard  <anton@samba.org>
  56
  57         * ppc.h (PPC_OPCODE_POWER6): Define.
  58         Adjust whitespace.
  59
  60 2006-06-05  Thiemo Seufer  <ths@mips.com>
  61
  62         * mips.h: Improve description of MT flags.
  63
  64 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  65
  66         * m68k.h (mcf_mask): Define.
  67
  68 2006-05-05  Thiemo Seufer  <ths@mips.com>
  69             David Ung  <davidu@mips.com>
  70
  71         * mips.h (enum): Add macro M_CACHE_AB.
  72
  73 2006-05-04  Thiemo Seufer  <ths@mips.com>
  74             Nigel Stephens  <nigel@mips.com>
  75             David Ung  <davidu@mips.com>
  76
  77         * mips.h: Add INSN_SMARTMIPS define.
  78
  79 2006-04-30  Thiemo Seufer  <ths@mips.com>
  80             David Ung  <davidu@mips.com>
  81
  82         * mips.h: Defines udi bits and masks.  Add description of
  83         characters which may appear in the args field of udi
  84         instructions.
  85
  86 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  87
  88         * mips.h: Improve comments describing the bitfield instruction
  89         fields.
  90
  91 2006-04-26  Julian Brown  <julian@codesourcery.com>
  92
  93         * arm.h (FPU_VFP_EXT_V3): Define constant.
  94         (FPU_NEON_EXT_V1): Likewise.
  95         (FPU_VFP_HARD): Update.
  96         (FPU_VFP_V3): Define macro.
  97         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  98
  99 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 100
 101         * avr.h (AVR_ISA_PWMx): New.
 102
 103 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 104
 105         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 106         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 107         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 108         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 109         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 110
 111 2006-03-10  Paul Brook  <paul@codesourcery.com>
 112
 113         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 114
 115 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 116
 117         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 118         first.  Correct mask of bb "B" opcode.
 119
 120 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 121
 122         * i386.h (i386_optab): Support Intel Merom New Instructions.
 123
 124 2006-02-24  Paul Brook  <paul@codesourcery.com>
 125
 126         * arm.h: Add V7 feature bits.
 127
 128 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 131
 132 2006-01-31  Paul Brook  <paul@codesourcery.com>
 133         Richard Earnshaw <rearnsha@arm.com>
 134
 135         * arm.h: Use ARM_CPU_FEATURE.
 136         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 137         (arm_feature_set): Change to a structure.
 138         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 139         ARM_FEATURE): New macros.
 140
 141 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 142
 143         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 144         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 145         (ADD_PC_INCR_OPCODE): Don't define.
 146
 147 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         PR gas/1874
 150         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 151
 152 2005-11-14  David Ung  <davidu@mips.com>
 153
 154         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 155         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 156         save/restore encoding of the args field.
 157
 158 2005-10-28  Dave Brolley  <brolley@redhat.com>
 159
 160         Contribute the following changes:
 161         2005-02-16  Dave Brolley  <brolley@redhat.com>
 162
 163         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 164         cgen_isa_mask_* to cgen_bitset_*.
 165         * cgen.h: Likewise.
 166
 167         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 168
 169         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 170         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 171         (CGEN_CPU_TABLE): Make isas a ponter.
 172
 173         2003-09-29  Dave Brolley  <brolley@redhat.com>
 174
 175         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 176         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 177         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 178
 179         2002-12-13  Dave Brolley  <brolley@redhat.com>
 180
 181         * cgen.h (symcat.h): #include it.
 182         (cgen-bitset.h): #include it.
 183         (CGEN_ATTR_VALUE_TYPE): Now a union.
 184         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 185         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 186         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 187         * cgen-bitset.h: New file.
 188
 189 2005-09-30  Catherine Moore  <clm@cm00re.com>
 190
 191         * bfin.h: New file.
 192
 193 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 194
 195         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 196         indirect operands.
 197
 198 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 199
 200         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 201         Add FLAG_STRICT to pa10 ftest opcode.
 202
 203 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 204
 205         * hppa.h (pa_opcodes): Remove lha entries.
 206
 207 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 208
 209         * hppa.h (FLAG_STRICT): Revise comment.
 210         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 211         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 212         entries for "fdc".
 213
 214 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 215
 216         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 217
 218 2005-09-06  Chao-ying Fu  <fu@mips.com>
 219
 220         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 221         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 222         define.
 223         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 224         (INSN_ASE_MASK): Update to include INSN_MT.
 225         (INSN_MT): New define for MT ASE.
 226
 227 2005-08-25  Chao-ying Fu  <fu@mips.com>
 228
 229         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 230         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 231         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 232         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 233         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 234         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 235         instructions.
 236         (INSN_DSP): New define for DSP ASE.
 237
 238 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 239
 240         * a29k.h: Delete.
 241
 242 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 243
 244         * ppc.h (PPC_OPCODE_E300): Define.
 245
 246 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 247
 248         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 249
 250 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 251
 252         PR gas/336
 253         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 254         and pitlb.
 255
 256 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 257
 258         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 259         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 260         Add movq-s as 64-bit variants of movd-s.
 261
 262 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 263
 264         * hppa.h: Fix punctuation in comment.
 265
 266         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 267         implicit space-register addressing.  Set space-register bits on opcodes
 268         using implicit space-register addressing.  Add various missing pa20
 269         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 270         space-register addressing.  Use "fE" instead of "fe" in various
 271         fstw opcodes.
 272
 273 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 274
 275         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 276
 277 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 278
 279         * i386.h (i386_optab): Support Intel VMX Instructions.
 280
 281 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 282
 283         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 284
 285 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 286
 287         * i386.h (i386_optab): Add new insns.
 288
 289 2005-07-01  Nick Clifton  <nickc@redhat.com>
 290
 291         * sparc.h: Add typedefs to structure declarations.
 292
 293 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         PR 1013
 296         * i386.h (i386_optab): Update comments for 64bit addressing on
 297         mov. Allow 64bit addressing for mov and movq.
 298
 299 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 300
 301         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 302         respectively, in various floating-point load and store patterns.
 303
 304 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 305
 306         * hppa.h (FLAG_STRICT): Correct comment.
 307         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 308         PA 2.0 mneumonics when equivalent.  Entries with cache control
 309         completers now require PA 1.1.  Adjust whitespace.
 310
 311 2005-05-19  Anton Blanchard  <anton@samba.org>
 312
 313         * ppc.h (PPC_OPCODE_POWER5): Define.
 314
 315 2005-05-10  Nick Clifton  <nickc@redhat.com>
 316
 317         * Update the address and phone number of the FSF organization in
 318         the GPL notices in the following files:
 319         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 320         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 321         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 322         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 323         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 324         tic54x.h, tic80.h, v850.h, vax.h
 325
 326 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 327
 328         * i386.h (i386_optab): Add ht and hnt.
 329
 330 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 331
 332         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 333         Add xcrypt-ctr.  Provide aliases without hyphens.
 334
 335 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         Moved from ../ChangeLog
 338
 339         2005-04-12  Paul Brook  <paul@codesourcery.com>
 340         * m88k.h: Rename psr macros to avoid conflicts.
 341
 342         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 343         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 344         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 345         and ARM_ARCH_V6ZKT2.
 346
 347         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 348         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 349         Remove redundant instruction types.
 350         (struct argument): X_op - new field.
 351         (struct cst4_entry): Remove.
 352         (no_op_insn): Declare.
 353
 354         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 355         * crx.h (enum argtype): Rename types, remove unused types.
 356
 357         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 358         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 359         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 360         (enum operand_type): Rearrange operands, edit comments.
 361         replace us<N> with ui<N> for unsigned immediate.
 362         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 363         displacements (respectively).
 364         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 365         (instruction type): Add NO_TYPE_INS.
 366         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 367         (operand_entry): New field - 'flags'.
 368         (operand flags): New.
 369
 370         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 371         * crx.h (operand_type): Remove redundant types i3, i4,
 372         i5, i8, i12.
 373         Add new unsigned immediate types us3, us4, us5, us16.
 374
 375 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 376
 377         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 378         adjust them accordingly.
 379
 380 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 381
 382         * i386.h (i386_optab): Add rdtscp.
 383
 384 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 385
 386         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 387         between memory and segment register. Allow movq for moving between
 388         general-purpose register and segment register.
 389
 390 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 391
 392         PR gas/707
 393         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 394         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 395         fnstsw.
 396
 397 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 398
 399         * m68k.h (m68008, m68ec030, m68882): Remove.
 400         (m68k_mask): New.
 401         (cpu_m68k, cpu_cf): New.
 402         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 403         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 404
 405 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 406
 407         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 408         * cgen.h (enum cgen_parse_operand_type): Add
 409         CGEN_PARSE_OPERAND_SYMBOLIC.
 410
 411 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 412
 413         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 414         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 415         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 416
 417 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 418
 419         * mips.h (struct mips_opcode): Add new pinfo2 member.
 420         (INSN_ALIAS): New define for opcode table entries that are
 421         specific instances of another entry, such as 'move' for an 'or'
 422         with a zero operand.
 423         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 424         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 425
 426 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 427
 428         * mips.h (CPU_RM9000): Define.
 429         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 430
 431 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 432
 433         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 434         to/from test registers are illegal in 64-bit mode. Add missing
 435         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 436         (previously one had to explicitly encode a rex64 prefix). Re-enable
 437         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 438         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 439
 440 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 441
 442         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 443         available only with SSE2. Change the MMX additions introduced by SSE
 444         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 445         instructions by their now designated identifier (since combining i686
 446         and 3DNow! does not really imply 3DNow!A).
 447
 448 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 449
 450         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 451         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 452
 453 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 454             Vineet Sharma      <vineets@noida.hcltech.com>
 455
 456         * maxq.h: New file: Disassembly information for the maxq port.
 457
 458 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         * i386.h (i386_optab): Put back "movzb".
 461
 462 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 463
 464         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 465         comments.  Remove member cris_ver_sim.  Add members
 466         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 467         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 468         (struct cris_support_reg, struct cris_cond15): New types.
 469         (cris_conds15): Declare.
 470         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 471         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 472         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 473         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 474         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 475         SIZE_FIELD_UNSIGNED.
 476
 477 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 478
 479         * i386.h (sldx_Suf): Remove.
 480         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 481         (q_FP): Define, implying no REX64.
 482         (x_FP, sl_FP): Imply FloatMF.
 483         (i386_optab): Split reg and mem forms of moving from segment registers
 484         so that the memory forms can ignore the 16-/32-bit operand size
 485         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 486         all non-floating-point instructions. Unite 32- and 64-bit forms of
 487         movsx, movzx, and movd. Adjust floating point operations for the above
 488         changes to the *FP macros. Add DefaultSize to floating point control
 489         insns operating on larger memory ranges. Remove left over comments
 490         hinting at certain insns being Intel-syntax ones where the ones
 491         actually meant are already gone.
 492
 493 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 494
 495         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 496         instruction type.
 497
 498 2004-09-30  Paul Brook  <paul@codesourcery.com>
 499
 500         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 501         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 502
 503 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 504
 505         * avr.h: Add support for
 506         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 507
 508 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 509
 510         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 511
 512 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 513
 514         * msp430.h (msp430_opc): Add new instructions.
 515         (msp430_rcodes): Declare new instructions.
 516         (msp430_hcodes): Likewise..
 517
 518 2004-08-13  Nick Clifton  <nickc@redhat.com>
 519
 520         PR/301
 521         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 522         processors.
 523
 524 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 525
 526         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 527
 528 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 531
 532 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 533
 534         * i386.h: Adjust instruction descriptions to better match the
 535         specification.
 536
 537 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 538
 539         * arm.h: Remove all old content.  Replace with architecture defines
 540         from gas/config/tc-arm.c.
 541
 542 2004-07-09  Andreas Schwab  <schwab@suse.de>
 543
 544         * m68k.h: Fix comment.
 545
 546 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 547
 548         * crx.h: New file.
 549
 550 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 551
 552         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 553
 554 2004-05-24  Peter Barada  <peter@the-baradas.com>
 555
 556         * m68k.h: Add 'size' to m68k_opcode.
 557
 558 2004-05-05  Peter Barada  <peter@the-baradas.com>
 559
 560         * m68k.h: Switch from ColdFire chip name to core variant.
 561
 562 2004-04-22  Peter Barada  <peter@the-baradas.com>
 563
 564         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 565         descriptions for new EMAC cases.
 566         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 567         handle Motorola MAC syntax.
 568         Allow disassembly of ColdFire V4e object files.
 569
 570 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 571
 572         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 573
 574 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 575
 576         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 577
 578 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 579
 580         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 581
 582 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 583
 584         * i386.h (i386_optab): Added xstore/xcrypt insns.
 585
 586 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 587
 588         * h8300.h (32bit ldc/stc): Add relaxing support.
 589
 590 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 591
 592         * h8300.h (BITOP): Pass MEMRELAX flag.
 593
 594 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 595
 596         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 597         except for the H8S.
 598
 599 For older changes see ChangeLog-9103
 600 \f
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 602 mode: change-log
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