1 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
3 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
4 (INSN_LOONGSON_3A): Clear bit 31.
6 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
9 * arm.h (ARM_AEXT_V6M_ONLY): New define.
10 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
11 (ARM_ARCH_V6M_ONLY): New define.
13 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
15 * mips.h (INSN_LOONGSON_3A): Defined.
16 (CPU_LOONGSON_3A): Defined.
17 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
19 2010-10-09 Matt Rice <ratmice@gmail.com>
21 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
22 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
24 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
26 * arm.h (ARM_EXT_VIRT): New define.
27 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
28 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
31 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
33 * arm.h (ARM_AEXT_ADIV): New define.
34 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
36 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
38 * arm.h (ARM_EXT_OS): New define.
39 (ARM_AEXT_V6SM): Likewise.
40 (ARM_ARCH_V6SM): Likewise.
42 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
44 * arm.h (ARM_EXT_MP): Add.
45 (ARM_ARCH_V7A_MP): Likewise.
47 2010-09-22 Mike Frysinger <vapier@gentoo.org>
49 * bfin.h: Declare pseudoChr structs/defines.
51 2010-09-21 Mike Frysinger <vapier@gentoo.org>
53 * bfin.h: Strip trailing whitespace.
55 2010-07-29 DJ Delorie <dj@redhat.com>
57 * rx.h (RX_Operand_Type): Add TwoReg.
58 (RX_Opcode_ID): Remove ediv and ediv2.
60 2010-07-27 DJ Delorie <dj@redhat.com>
62 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
64 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
65 Ina Pandit <ina.pandit@kpitcummins.com>
67 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
68 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
70 Remove PROCESSOR_V850EA support.
71 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
72 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
73 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
74 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
75 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
77 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
79 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
82 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
84 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
85 (MIPS16_INSN_BRANCH): Rename to...
86 (MIPS16_INSN_COND_BRANCH): ... this.
88 2010-07-03 Alan Modra <amodra@gmail.com>
90 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
91 Renumber other PPC_OPCODE defines.
93 2010-07-03 Alan Modra <amodra@gmail.com>
95 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
97 2010-06-29 Alan Modra <amodra@gmail.com>
99 * maxq.h: Delete file.
101 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
103 * ppc.h (PPC_OPCODE_E500): Define.
105 2010-05-26 Catherine Moore <clm@codesourcery.com>
107 * opcode/mips.h (INSN_MIPS16): Remove.
109 2010-04-21 Joseph Myers <joseph@codesourcery.com>
111 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
113 2010-04-15 Nick Clifton <nickc@redhat.com>
115 * alpha.h: Update copyright notice to use GPLv3.
121 * convex.h: Likewise.
135 * m68hc11.h: Likewise.
141 * mn10200.h: Likewise.
142 * mn10300.h: Likewise.
143 * msp430.h: Likewise.
154 * score-datadep.h: Likewise.
155 * score-inst.h: Likewise.
157 * spu-insns.h: Likewise.
161 * tic54x.h: Likewise.
166 2010-03-25 Joseph Myers <joseph@codesourcery.com>
168 * tic6x-control-registers.h, tic6x-insn-formats.h,
169 tic6x-opcode-table.h, tic6x.h: New.
171 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
173 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
175 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
177 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
179 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
181 * ia64.h (ia64_find_opcode): Remove argument name.
182 (ia64_find_next_opcode): Likewise.
183 (ia64_dis_opcode): Likewise.
184 (ia64_free_opcode): Likewise.
185 (ia64_find_dependency): Likewise.
187 2009-11-22 Doug Evans <dje@sebabeach.org>
189 * cgen.h: Include bfd_stdint.h.
190 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
192 2009-11-18 Paul Brook <paul@codesourcery.com>
194 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
196 2009-11-17 Paul Brook <paul@codesourcery.com>
197 Daniel Jacobowitz <dan@codesourcery.com>
199 * arm.h (ARM_EXT_V6_DSP): Define.
200 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
201 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
203 2009-11-04 DJ Delorie <dj@redhat.com>
205 * rx.h (rx_decode_opcode) (mvtipl): Add.
206 (mvtcp, mvfcp, opecp): Remove.
208 2009-11-02 Paul Brook <paul@codesourcery.com>
210 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
211 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
212 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
213 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
214 FPU_ARCH_NEON_VFP_V4): Define.
216 2009-10-23 Doug Evans <dje@sebabeach.org>
218 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
219 * cgen.h: Update. Improve multi-inclusion macro name.
221 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
223 * ppc.h (PPC_OPCODE_476): Define.
225 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
227 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
229 2009-09-29 DJ Delorie <dj@redhat.com>
233 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
235 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
237 2009-09-21 Ben Elliston <bje@au.ibm.com>
239 * ppc.h (PPC_OPCODE_PPCA2): New.
241 2009-09-05 Martin Thuresson <martin@mtme.org>
243 * ia64.h (struct ia64_operand): Renamed member class to op_class.
245 2009-08-29 Martin Thuresson <martin@mtme.org>
247 * tic30.h (template): Rename type template to
248 insn_template. Updated code to use new name.
249 * tic54x.h (template): Rename type template to
252 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
254 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
256 2009-06-11 Anthony Green <green@moxielogic.com>
258 * moxie.h (MOXIE_F3_PCREL): Define.
259 (moxie_form3_opc_info): Grow.
261 2009-06-06 Anthony Green <green@moxielogic.com>
263 * moxie.h (MOXIE_F1_M): Define.
265 2009-04-15 Anthony Green <green@moxielogic.com>
269 2009-04-06 DJ Delorie <dj@redhat.com>
271 * h8300.h: Add relaxation attributes to MOVA opcodes.
273 2009-03-10 Alan Modra <amodra@bigpond.net.au>
275 * ppc.h (ppc_parse_cpu): Declare.
277 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
279 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
280 and _IMM11 for mbitclr and mbitset.
281 * score-datadep.h: Update dependency information.
283 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
285 * ppc.h (PPC_OPCODE_POWER7): New.
287 2009-02-06 Doug Evans <dje@google.com>
289 * i386.h: Add comment regarding sse* insns and prefixes.
291 2009-02-03 Sandip Matte <sandip@rmicorp.com>
293 * mips.h (INSN_XLR): Define.
294 (INSN_CHIP_MASK): Update.
296 (OPCODE_IS_MEMBER): Update.
297 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
299 2009-01-28 Doug Evans <dje@google.com>
301 * opcode/i386.h: Add multiple inclusion protection.
302 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
303 (EDI_REG_NUM): New macros.
304 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
305 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
306 (REX_PREFIX_P): New macro.
308 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
310 * ppc.h (struct powerpc_opcode): New field "deprecated".
311 (PPC_OPCODE_NOPOWER4): Delete.
313 2008-11-28 Joshua Kinard <kumba@gentoo.org>
315 * mips.h: Define CPU_R14000, CPU_R16000.
316 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
318 2008-11-18 Catherine Moore <clm@codesourcery.com>
320 * arm.h (FPU_NEON_FP16): New.
321 (FPU_ARCH_NEON_FP16): New.
323 2008-11-06 Chao-ying Fu <fu@mips.com>
325 * mips.h: Doucument '1' for 5-bit sync type.
327 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
329 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
332 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
334 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
336 2008-07-30 Michael J. Eager <eager@eagercon.com>
338 * ppc.h (PPC_OPCODE_405): Define.
339 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
341 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
343 * ppc.h (ppc_cpu_t): New typedef.
344 (struct powerpc_opcode <flags>): Use it.
345 (struct powerpc_operand <insert, extract>): Likewise.
346 (struct powerpc_macro <flags>): Likewise.
348 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
350 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
351 Update comment before MIPS16 field descriptors to mention MIPS16.
352 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
354 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
355 New bit masks and shift counts for cins and exts.
357 * mips.h: Document new field descriptors +Q.
358 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
360 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
362 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
363 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
365 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
367 * ppc.h: (PPC_OPCODE_E500MC): New.
369 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
371 * i386.h (MAX_OPERANDS): Set to 5.
372 (MAX_MNEM_SIZE): Changed to 20.
374 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
376 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
378 2008-03-09 Paul Brook <paul@codesourcery.com>
380 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
382 2008-03-04 Paul Brook <paul@codesourcery.com>
384 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
385 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
386 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
388 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
389 Nick Clifton <nickc@redhat.com>
392 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
393 with a 32-bit displacement but without the top bit of the 4th byte
396 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
398 * cr16.h (cr16_num_optab): Declared.
400 2008-02-14 Hakan Ardo <hakan@debian.org>
403 * avr.h (AVR_ISA_2xxe): Define.
405 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
407 * mips.h: Update copyright.
408 (INSN_CHIP_MASK): New macro.
409 (INSN_OCTEON): New macro.
410 (CPU_OCTEON): New macro.
411 (OPCODE_IS_MEMBER): Handle Octeon instructions.
413 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
415 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
417 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
419 * avr.h (AVR_ISA_USB162): Add new opcode set.
420 (AVR_ISA_AVR3): Likewise.
422 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
424 * mips.h (INSN_LOONGSON_2E): New.
425 (INSN_LOONGSON_2F): New.
426 (CPU_LOONGSON_2E): New.
427 (CPU_LOONGSON_2F): New.
428 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
430 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
432 * mips.h (INSN_ISA*): Redefine certain values as an
433 enumeration. Update comments.
434 (mips_isa_table): New.
435 (ISA_MIPS*): Redefine to match enumeration.
436 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
439 2007-08-08 Ben Elliston <bje@au.ibm.com>
441 * ppc.h (PPC_OPCODE_PPCPS): New.
443 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
445 * m68k.h: Document j K & E.
447 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
449 * cr16.h: New file for CR16 target.
451 2007-05-02 Alan Modra <amodra@bigpond.net.au>
453 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
455 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
457 * m68k.h (mcfisa_c): New.
458 (mcfusp, mcf_mask): Adjust.
460 2007-04-20 Alan Modra <amodra@bigpond.net.au>
462 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
463 (num_powerpc_operands): Declare.
464 (PPC_OPERAND_SIGNED et al): Redefine as hex.
465 (PPC_OPERAND_PLUS1): Define.
467 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
469 * i386.h (REX_MODE64): Renamed to ...
471 (REX_EXTX): Renamed to ...
473 (REX_EXTY): Renamed to ...
475 (REX_EXTZ): Renamed to ...
478 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
480 * i386.h: Add entries from config/tc-i386.h and move tables
481 to opcodes/i386-opc.h.
483 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
485 * i386.h (FloatDR): Removed.
486 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
488 2007-03-01 Alan Modra <amodra@bigpond.net.au>
490 * spu-insns.h: Add soma double-float insns.
492 2007-02-20 Thiemo Seufer <ths@mips.com>
493 Chao-Ying Fu <fu@mips.com>
495 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
496 (INSN_DSPR2): Add flag for DSP R2 instructions.
497 (M_BALIGN): New macro.
499 2007-02-14 Alan Modra <amodra@bigpond.net.au>
501 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
502 and Seg3ShortFrom with Shortform.
504 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
507 * i386.h (i386_optab): Put the real "test" before the pseudo
510 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
512 * m68k.h (m68010up): OR fido_a.
514 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
516 * m68k.h (fido_a): New.
518 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
520 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
521 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
524 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
526 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
528 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
530 * score-inst.h (enum score_insn_type): Add Insn_internal.
532 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
533 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
534 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
535 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
536 Alan Modra <amodra@bigpond.net.au>
538 * spu-insns.h: New file.
541 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
543 * ppc.h (PPC_OPCODE_CELL): Define.
545 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
547 * i386.h : Modify opcode to support for the change in POPCNT opcode
548 in amdfam10 architecture.
550 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
552 * i386.h: Replace CpuMNI with CpuSSSE3.
554 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
555 Joseph Myers <joseph@codesourcery.com>
556 Ian Lance Taylor <ian@wasabisystems.com>
557 Ben Elliston <bje@wasabisystems.com>
559 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
561 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
563 * score-datadep.h: New file.
564 * score-inst.h: New file.
566 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
568 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
569 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
572 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
573 Michael Meissner <michael.meissner@amd.com>
575 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
577 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
579 * i386.h (i386_optab): Add "nop" with memory reference.
581 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
583 * i386.h (i386_optab): Update comment for 64bit NOP.
585 2006-06-06 Ben Elliston <bje@au.ibm.com>
586 Anton Blanchard <anton@samba.org>
588 * ppc.h (PPC_OPCODE_POWER6): Define.
591 2006-06-05 Thiemo Seufer <ths@mips.com>
593 * mips.h: Improve description of MT flags.
595 2006-05-25 Richard Sandiford <richard@codesourcery.com>
597 * m68k.h (mcf_mask): Define.
599 2006-05-05 Thiemo Seufer <ths@mips.com>
600 David Ung <davidu@mips.com>
602 * mips.h (enum): Add macro M_CACHE_AB.
604 2006-05-04 Thiemo Seufer <ths@mips.com>
605 Nigel Stephens <nigel@mips.com>
606 David Ung <davidu@mips.com>
608 * mips.h: Add INSN_SMARTMIPS define.
610 2006-04-30 Thiemo Seufer <ths@mips.com>
611 David Ung <davidu@mips.com>
613 * mips.h: Defines udi bits and masks. Add description of
614 characters which may appear in the args field of udi
617 2006-04-26 Thiemo Seufer <ths@networkno.de>
619 * mips.h: Improve comments describing the bitfield instruction
622 2006-04-26 Julian Brown <julian@codesourcery.com>
624 * arm.h (FPU_VFP_EXT_V3): Define constant.
625 (FPU_NEON_EXT_V1): Likewise.
626 (FPU_VFP_HARD): Update.
627 (FPU_VFP_V3): Define macro.
628 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
630 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
632 * avr.h (AVR_ISA_PWMx): New.
634 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
636 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
637 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
638 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
639 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
640 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
642 2006-03-10 Paul Brook <paul@codesourcery.com>
644 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
646 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
648 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
649 first. Correct mask of bb "B" opcode.
651 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
653 * i386.h (i386_optab): Support Intel Merom New Instructions.
655 2006-02-24 Paul Brook <paul@codesourcery.com>
657 * arm.h: Add V7 feature bits.
659 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
661 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
663 2006-01-31 Paul Brook <paul@codesourcery.com>
664 Richard Earnshaw <rearnsha@arm.com>
666 * arm.h: Use ARM_CPU_FEATURE.
667 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
668 (arm_feature_set): Change to a structure.
669 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
670 ARM_FEATURE): New macros.
672 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
674 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
675 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
676 (ADD_PC_INCR_OPCODE): Don't define.
678 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
681 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
683 2005-11-14 David Ung <davidu@mips.com>
685 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
686 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
687 save/restore encoding of the args field.
689 2005-10-28 Dave Brolley <brolley@redhat.com>
691 Contribute the following changes:
692 2005-02-16 Dave Brolley <brolley@redhat.com>
694 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
695 cgen_isa_mask_* to cgen_bitset_*.
698 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
700 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
701 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
702 (CGEN_CPU_TABLE): Make isas a ponter.
704 2003-09-29 Dave Brolley <brolley@redhat.com>
706 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
707 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
708 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
710 2002-12-13 Dave Brolley <brolley@redhat.com>
712 * cgen.h (symcat.h): #include it.
713 (cgen-bitset.h): #include it.
714 (CGEN_ATTR_VALUE_TYPE): Now a union.
715 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
716 (CGEN_ATTR_ENTRY): 'value' now unsigned.
717 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
718 * cgen-bitset.h: New file.
720 2005-09-30 Catherine Moore <clm@cm00re.com>
724 2005-10-24 Jan Beulich <jbeulich@novell.com>
726 * ia64.h (enum ia64_opnd): Move memory operand out of set of
729 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
731 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
732 Add FLAG_STRICT to pa10 ftest opcode.
734 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
736 * hppa.h (pa_opcodes): Remove lha entries.
738 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
740 * hppa.h (FLAG_STRICT): Revise comment.
741 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
742 before corresponding pa11 opcodes. Add strict pa10 register-immediate
745 2005-09-30 Catherine Moore <clm@cm00re.com>
749 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
751 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
753 2005-09-06 Chao-ying Fu <fu@mips.com>
755 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
756 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
758 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
759 (INSN_ASE_MASK): Update to include INSN_MT.
760 (INSN_MT): New define for MT ASE.
762 2005-08-25 Chao-ying Fu <fu@mips.com>
764 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
765 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
766 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
767 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
768 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
769 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
771 (INSN_DSP): New define for DSP ASE.
773 2005-08-18 Alan Modra <amodra@bigpond.net.au>
777 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
779 * ppc.h (PPC_OPCODE_E300): Define.
781 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
783 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
785 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
788 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
791 2005-07-27 Jan Beulich <jbeulich@novell.com>
793 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
794 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
795 Add movq-s as 64-bit variants of movd-s.
797 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
799 * hppa.h: Fix punctuation in comment.
801 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
802 implicit space-register addressing. Set space-register bits on opcodes
803 using implicit space-register addressing. Add various missing pa20
804 long-immediate opcodes. Remove various opcodes using implicit 3-bit
805 space-register addressing. Use "fE" instead of "fe" in various
808 2005-07-18 Jan Beulich <jbeulich@novell.com>
810 * i386.h (i386_optab): Operands of aam and aad are unsigned.
812 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
814 * i386.h (i386_optab): Support Intel VMX Instructions.
816 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
820 2005-07-05 Jan Beulich <jbeulich@novell.com>
822 * i386.h (i386_optab): Add new insns.
824 2005-07-01 Nick Clifton <nickc@redhat.com>
826 * sparc.h: Add typedefs to structure declarations.
828 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
831 * i386.h (i386_optab): Update comments for 64bit addressing on
832 mov. Allow 64bit addressing for mov and movq.
834 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
836 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
837 respectively, in various floating-point load and store patterns.
839 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
841 * hppa.h (FLAG_STRICT): Correct comment.
842 (pa_opcodes): Update load and store entries to allow both PA 1.X and
843 PA 2.0 mneumonics when equivalent. Entries with cache control
844 completers now require PA 1.1. Adjust whitespace.
846 2005-05-19 Anton Blanchard <anton@samba.org>
848 * ppc.h (PPC_OPCODE_POWER5): Define.
850 2005-05-10 Nick Clifton <nickc@redhat.com>
852 * Update the address and phone number of the FSF organization in
853 the GPL notices in the following files:
854 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
855 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
856 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
857 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
858 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
859 tic54x.h, tic80.h, v850.h, vax.h
861 2005-05-09 Jan Beulich <jbeulich@novell.com>
863 * i386.h (i386_optab): Add ht and hnt.
865 2005-04-18 Mark Kettenis <kettenis@gnu.org>
867 * i386.h: Insert hyphens into selected VIA PadLock extensions.
868 Add xcrypt-ctr. Provide aliases without hyphens.
870 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
872 Moved from ../ChangeLog
874 2005-04-12 Paul Brook <paul@codesourcery.com>
875 * m88k.h: Rename psr macros to avoid conflicts.
877 2005-03-12 Zack Weinberg <zack@codesourcery.com>
878 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
879 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
882 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
883 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
884 Remove redundant instruction types.
885 (struct argument): X_op - new field.
886 (struct cst4_entry): Remove.
887 (no_op_insn): Declare.
889 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
890 * crx.h (enum argtype): Rename types, remove unused types.
892 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
893 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
894 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
895 (enum operand_type): Rearrange operands, edit comments.
896 replace us<N> with ui<N> for unsigned immediate.
897 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
898 displacements (respectively).
899 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
900 (instruction type): Add NO_TYPE_INS.
901 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
902 (operand_entry): New field - 'flags'.
903 (operand flags): New.
905 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
906 * crx.h (operand_type): Remove redundant types i3, i4,
908 Add new unsigned immediate types us3, us4, us5, us16.
910 2005-04-12 Mark Kettenis <kettenis@gnu.org>
912 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
913 adjust them accordingly.
915 2005-04-01 Jan Beulich <jbeulich@novell.com>
917 * i386.h (i386_optab): Add rdtscp.
919 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
921 * i386.h (i386_optab): Don't allow the `l' suffix for moving
922 between memory and segment register. Allow movq for moving between
923 general-purpose register and segment register.
925 2005-02-09 Jan Beulich <jbeulich@novell.com>
928 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
929 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
932 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
934 * m68k.h (m68008, m68ec030, m68882): Remove.
936 (cpu_m68k, cpu_cf): New.
937 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
938 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
940 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
942 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
943 * cgen.h (enum cgen_parse_operand_type): Add
944 CGEN_PARSE_OPERAND_SYMBOLIC.
946 2005-01-21 Fred Fish <fnf@specifixinc.com>
948 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
949 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
950 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
952 2005-01-19 Fred Fish <fnf@specifixinc.com>
954 * mips.h (struct mips_opcode): Add new pinfo2 member.
955 (INSN_ALIAS): New define for opcode table entries that are
956 specific instances of another entry, such as 'move' for an 'or'
958 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
959 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
961 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
963 * mips.h (CPU_RM9000): Define.
964 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
966 2004-11-25 Jan Beulich <jbeulich@novell.com>
968 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
969 to/from test registers are illegal in 64-bit mode. Add missing
970 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
971 (previously one had to explicitly encode a rex64 prefix). Re-enable
972 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
973 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
975 2004-11-23 Jan Beulich <jbeulich@novell.com>
977 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
978 available only with SSE2. Change the MMX additions introduced by SSE
979 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
980 instructions by their now designated identifier (since combining i686
981 and 3DNow! does not really imply 3DNow!A).
983 2004-11-19 Alan Modra <amodra@bigpond.net.au>
985 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
986 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
988 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
989 Vineet Sharma <vineets@noida.hcltech.com>
991 * maxq.h: New file: Disassembly information for the maxq port.
993 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
995 * i386.h (i386_optab): Put back "movzb".
997 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
999 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1000 comments. Remove member cris_ver_sim. Add members
1001 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1002 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1003 (struct cris_support_reg, struct cris_cond15): New types.
1004 (cris_conds15): Declare.
1005 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1006 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1007 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1008 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1009 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1010 SIZE_FIELD_UNSIGNED.
1012 2004-11-04 Jan Beulich <jbeulich@novell.com>
1014 * i386.h (sldx_Suf): Remove.
1015 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1016 (q_FP): Define, implying no REX64.
1017 (x_FP, sl_FP): Imply FloatMF.
1018 (i386_optab): Split reg and mem forms of moving from segment registers
1019 so that the memory forms can ignore the 16-/32-bit operand size
1020 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1021 all non-floating-point instructions. Unite 32- and 64-bit forms of
1022 movsx, movzx, and movd. Adjust floating point operations for the above
1023 changes to the *FP macros. Add DefaultSize to floating point control
1024 insns operating on larger memory ranges. Remove left over comments
1025 hinting at certain insns being Intel-syntax ones where the ones
1026 actually meant are already gone.
1028 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1030 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1033 2004-09-30 Paul Brook <paul@codesourcery.com>
1035 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1036 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1038 2004-09-11 Theodore A. Roth <troth@openavr.org>
1040 * avr.h: Add support for
1041 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1043 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1045 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1047 2004-08-24 Dmitry Diky <diwil@spec.ru>
1049 * msp430.h (msp430_opc): Add new instructions.
1050 (msp430_rcodes): Declare new instructions.
1051 (msp430_hcodes): Likewise..
1053 2004-08-13 Nick Clifton <nickc@redhat.com>
1056 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1059 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1061 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1063 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1065 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1067 2004-07-21 Jan Beulich <jbeulich@novell.com>
1069 * i386.h: Adjust instruction descriptions to better match the
1072 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1074 * arm.h: Remove all old content. Replace with architecture defines
1075 from gas/config/tc-arm.c.
1077 2004-07-09 Andreas Schwab <schwab@suse.de>
1079 * m68k.h: Fix comment.
1081 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1085 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1087 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1089 2004-05-24 Peter Barada <peter@the-baradas.com>
1091 * m68k.h: Add 'size' to m68k_opcode.
1093 2004-05-05 Peter Barada <peter@the-baradas.com>
1095 * m68k.h: Switch from ColdFire chip name to core variant.
1097 2004-04-22 Peter Barada <peter@the-baradas.com>
1099 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1100 descriptions for new EMAC cases.
1101 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1102 handle Motorola MAC syntax.
1103 Allow disassembly of ColdFire V4e object files.
1105 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1107 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1109 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1111 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1113 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1115 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1117 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1119 * i386.h (i386_optab): Added xstore/xcrypt insns.
1121 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1123 * h8300.h (32bit ldc/stc): Add relaxing support.
1125 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1127 * h8300.h (BITOP): Pass MEMRELAX flag.
1129 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1131 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1134 For older changes see ChangeLog-9103
1140 version-control: never