include/opcode/ChangeLog

   1 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
   2
   3         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
   4         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
   5         (ADD_PC_INCR_OPCODE): Don't define.
   6
   7 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         PR gas/1874
  10         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  11
  12 2005-11-14  David Ung  <davidu@mips.com>
  13
  14         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  15         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  16         save/restore encoding of the args field.
  17
  18 2005-10-28  Dave Brolley  <brolley@redhat.com>
  19
  20         Contribute the following changes:
  21         2005-02-16  Dave Brolley  <brolley@redhat.com>
  22
  23         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  24         cgen_isa_mask_* to cgen_bitset_*.
  25         * cgen.h: Likewise.
  26
  27         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  28
  29         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  30         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  31         (CGEN_CPU_TABLE): Make isas a ponter.
  32
  33         2003-09-29  Dave Brolley  <brolley@redhat.com>
  34
  35         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  36         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  37         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  38
  39         2002-12-13  Dave Brolley  <brolley@redhat.com>
  40
  41         * cgen.h (symcat.h): #include it.
  42         (cgen-bitset.h): #include it.
  43         (CGEN_ATTR_VALUE_TYPE): Now a union.
  44         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  45         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  46         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  47         * cgen-bitset.h: New file.
  48
  49 2005-09-30  Catherine Moore  <clm@cm00re.com>
  50
  51         * bfin.h: New file.
  52
  53 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  54
  55         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  56         indirect operands.
  57
  58 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  59
  60         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  61         Add FLAG_STRICT to pa10 ftest opcode.
  62
  63 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  64
  65         * hppa.h (pa_opcodes): Remove lha entries.
  66
  67 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  68
  69         * hppa.h (FLAG_STRICT): Revise comment.
  70         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  71         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  72         entries for "fdc".
  73
  74 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  75
  76         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  77
  78 2005-09-06  Chao-ying Fu  <fu@mips.com>
  79
  80         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
  81         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
  82         define.
  83         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
  84         (INSN_ASE_MASK): Update to include INSN_MT.
  85         (INSN_MT): New define for MT ASE.
  86
  87 2005-08-25  Chao-ying Fu  <fu@mips.com>
  88
  89         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  90         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  91         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  92         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  93         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  94         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  95         instructions.
  96         (INSN_DSP): New define for DSP ASE.
  97
  98 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  99
 100         * a29k.h: Delete.
 101
 102 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 103
 104         * ppc.h (PPC_OPCODE_E300): Define.
 105
 106 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 107
 108         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 109
 110 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 111
 112         PR gas/336
 113         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 114         and pitlb.
 115
 116 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 117
 118         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 119         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 120         Add movq-s as 64-bit variants of movd-s.
 121
 122 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 123
 124         * hppa.h: Fix punctuation in comment.
 125
 126         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 127         implicit space-register addressing.  Set space-register bits on opcodes
 128         using implicit space-register addressing.  Add various missing pa20
 129         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 130         space-register addressing.  Use "fE" instead of "fe" in various
 131         fstw opcodes.
 132
 133 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 134
 135         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 136
 137 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 138
 139         * i386.h (i386_optab): Support Intel VMX Instructions.
 140
 141 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 142
 143         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 144
 145 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 146
 147         * i386.h (i386_optab): Add new insns.
 148
 149 2005-07-01  Nick Clifton  <nickc@redhat.com>
 150
 151         * sparc.h: Add typedefs to structure declarations.
 152
 153 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         PR 1013
 156         * i386.h (i386_optab): Update comments for 64bit addressing on
 157         mov. Allow 64bit addressing for mov and movq.
 158
 159 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 160
 161         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 162         respectively, in various floating-point load and store patterns.
 163
 164 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 165
 166         * hppa.h (FLAG_STRICT): Correct comment.
 167         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 168         PA 2.0 mneumonics when equivalent.  Entries with cache control
 169         completers now require PA 1.1.  Adjust whitespace.
 170
 171 2005-05-19  Anton Blanchard  <anton@samba.org>
 172
 173         * ppc.h (PPC_OPCODE_POWER5): Define.
 174
 175 2005-05-10  Nick Clifton  <nickc@redhat.com>
 176
 177         * Update the address and phone number of the FSF organization in
 178         the GPL notices in the following files:
 179         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 180         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 181         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 182         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 183         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 184         tic54x.h, tic80.h, v850.h, vax.h
 185
 186 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 187
 188         * i386.h (i386_optab): Add ht and hnt.
 189
 190 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 191
 192         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 193         Add xcrypt-ctr.  Provide aliases without hyphens.
 194
 195 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         Moved from ../ChangeLog
 198
 199         2005-04-12  Paul Brook  <paul@codesourcery.com>
 200         * m88k.h: Rename psr macros to avoid conflicts.
 201
 202         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 203         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 204         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 205         and ARM_ARCH_V6ZKT2.
 206
 207         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 208         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 209         Remove redundant instruction types.
 210         (struct argument): X_op - new field.
 211         (struct cst4_entry): Remove.
 212         (no_op_insn): Declare.
 213
 214         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 215         * crx.h (enum argtype): Rename types, remove unused types.
 216
 217         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 218         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 219         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 220         (enum operand_type): Rearrange operands, edit comments.
 221         replace us<N> with ui<N> for unsigned immediate.
 222         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 223         displacements (respectively).
 224         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 225         (instruction type): Add NO_TYPE_INS.
 226         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 227         (operand_entry): New field - 'flags'.
 228         (operand flags): New.
 229
 230         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 231         * crx.h (operand_type): Remove redundant types i3, i4,
 232         i5, i8, i12.
 233         Add new unsigned immediate types us3, us4, us5, us16.
 234
 235 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 236
 237         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 238         adjust them accordingly.
 239
 240 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 241
 242         * i386.h (i386_optab): Add rdtscp.
 243
 244 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 247         between memory and segment register. Allow movq for moving between
 248         general-purpose register and segment register.
 249
 250 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 251
 252         PR gas/707
 253         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 254         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 255         fnstsw.
 256
 257 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 258
 259         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 260         * cgen.h (enum cgen_parse_operand_type): Add
 261         CGEN_PARSE_OPERAND_SYMBOLIC.
 262
 263 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 264
 265         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 266         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 267         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 268
 269 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 270
 271         * mips.h (struct mips_opcode): Add new pinfo2 member.
 272         (INSN_ALIAS): New define for opcode table entries that are
 273         specific instances of another entry, such as 'move' for an 'or'
 274         with a zero operand.
 275         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 276         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 277
 278 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 279
 280         * mips.h (CPU_RM9000): Define.
 281         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 282
 283 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 284
 285         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 286         to/from test registers are illegal in 64-bit mode. Add missing
 287         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 288         (previously one had to explicitly encode a rex64 prefix). Re-enable
 289         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 290         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 291
 292 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 293
 294         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 295         available only with SSE2. Change the MMX additions introduced by SSE
 296         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 297         instructions by their now designated identifier (since combining i686
 298         and 3DNow! does not really imply 3DNow!A).
 299
 300 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 301
 302         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 303         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 304
 305 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 306             Vineet Sharma      <vineets@noida.hcltech.com>
 307
 308         * maxq.h: New file: Disassembly information for the maxq port.
 309
 310 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         * i386.h (i386_optab): Put back "movzb".
 313
 314 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 315
 316         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 317         comments.  Remove member cris_ver_sim.  Add members
 318         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 319         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 320         (struct cris_support_reg, struct cris_cond15): New types.
 321         (cris_conds15): Declare.
 322         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 323         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 324         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 325         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 326         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 327         SIZE_FIELD_UNSIGNED.
 328
 329 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 330
 331         * i386.h (sldx_Suf): Remove.
 332         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 333         (q_FP): Define, implying no REX64.
 334         (x_FP, sl_FP): Imply FloatMF.
 335         (i386_optab): Split reg and mem forms of moving from segment registers
 336         so that the memory forms can ignore the 16-/32-bit operand size
 337         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 338         all non-floating-point instructions. Unite 32- and 64-bit forms of
 339         movsx, movzx, and movd. Adjust floating point operations for the above
 340         changes to the *FP macros. Add DefaultSize to floating point control
 341         insns operating on larger memory ranges. Remove left over comments
 342         hinting at certain insns being Intel-syntax ones where the ones
 343         actually meant are already gone.
 344
 345 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 346
 347         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 348         instruction type.
 349
 350 2004-09-30  Paul Brook  <paul@codesourcery.com>
 351
 352         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 353         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 354
 355 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 356
 357         * avr.h: Add support for
 358         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 359
 360 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 361
 362         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 363
 364 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 365
 366         * msp430.h (msp430_opc): Add new instructions.
 367         (msp430_rcodes): Declare new instructions.
 368         (msp430_hcodes): Likewise..
 369
 370 2004-08-13  Nick Clifton  <nickc@redhat.com>
 371
 372         PR/301
 373         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 374         processors.
 375
 376 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 377
 378         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 379
 380 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 383
 384 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 385
 386         * i386.h: Adjust instruction descriptions to better match the
 387         specification.
 388
 389 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 390
 391         * arm.h: Remove all old content.  Replace with architecture defines
 392         from gas/config/tc-arm.c.
 393
 394 2004-07-09  Andreas Schwab  <schwab@suse.de>
 395
 396         * m68k.h: Fix comment.
 397
 398 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 399
 400         * crx.h: New file.
 401
 402 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 403
 404         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 405
 406 2004-05-24  Peter Barada  <peter@the-baradas.com>
 407
 408         * m68k.h: Add 'size' to m68k_opcode.
 409
 410 2004-05-05  Peter Barada  <peter@the-baradas.com>
 411
 412         * m68k.h: Switch from ColdFire chip name to core variant.
 413
 414 2004-04-22  Peter Barada  <peter@the-baradas.com>
 415
 416         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 417         descriptions for new EMAC cases.
 418         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 419         handle Motorola MAC syntax.
 420         Allow disassembly of ColdFire V4e object files.
 421
 422 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 423
 424         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 425
 426 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 427
 428         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 429
 430 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 431
 432         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 433
 434 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 435
 436         * i386.h (i386_optab): Added xstore/xcrypt insns.
 437
 438 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 439
 440         * h8300.h (32bit ldc/stc): Add relaxing support.
 441
 442 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 443
 444         * h8300.h (BITOP): Pass MEMRELAX flag.
 445
 446 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 447
 448         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 449         except for the H8S.
 450
 451 For older changes see ChangeLog-9103
 452 \f
 453 Local Variables:
 454 mode: change-log
 455 left-margin: 8
 456 fill-column: 74
 457 version-control: never
 458 End: