include/opcode/ChangeLog

   1 2008-03-09  Paul Brook  <paul@codesourcery.com>
   2
   3         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
   4
   5 2008-03-04  Paul Brook  <paul@codesourcery.com>
   6
   7         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
   8         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
   9         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  10
  11 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  12             Nick Clifton  <nickc@redhat.com>
  13
  14         PR 3134
  15         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
  16         with a 32-bit displacement but without the top bit of the 4th byte
  17         set.
  18
  19 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  20
  21         * cr16.h (cr16_num_optab): Declared.
  22
  23 2008-02-14  Hakan Ardo  <hakan@debian.org>
  24
  25         PR gas/2626
  26         * avr.h (AVR_ISA_2xxe): Define.
  27
  28 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  29
  30         * mips.h: Update copyright.
  31         (INSN_CHIP_MASK): New macro.
  32         (INSN_OCTEON): New macro.
  33         (CPU_OCTEON): New macro.
  34         (OPCODE_IS_MEMBER): Handle Octeon instructions.
  35
  36 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  37
  38         * mips.h (INSN_LOONGSON_2E): New.
  39         (INSN_LOONGSON_2F): New.
  40         (CPU_LOONGSON_2E): New.
  41         (CPU_LOONGSON_2F): New.
  42         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
  43
  44 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  45
  46         * mips.h (INSN_ISA*): Redefine certain values as an
  47         enumeration.  Update comments.
  48         (mips_isa_table): New.
  49         (ISA_MIPS*): Redefine to match enumeration.
  50         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  51         values.
  52
  53 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  54
  55         * ppc.h (PPC_OPCODE_PPCPS): New.
  56
  57 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  58
  59         * m68k.h: Document j K & E.
  60
  61 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  62
  63         * cr16.h: New file for CR16 target.
  64
  65 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  66
  67         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  68
  69 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  70
  71         * m68k.h (mcfisa_c): New.
  72         (mcfusp, mcf_mask): Adjust.
  73
  74 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  75
  76         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  77         (num_powerpc_operands): Declare.
  78         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  79         (PPC_OPERAND_PLUS1): Define.
  80
  81 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * i386.h (REX_MODE64): Renamed to ...
  84         (REX_W): This.
  85         (REX_EXTX): Renamed to ...
  86         (REX_R): This.
  87         (REX_EXTY): Renamed to ...
  88         (REX_X): This.
  89         (REX_EXTZ): Renamed to ...
  90         (REX_B): This.
  91
  92 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386.h: Add entries from config/tc-i386.h and move tables
  95         to opcodes/i386-opc.h.
  96
  97 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  98
  99         * i386.h (FloatDR): Removed.
 100         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 101
 102 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 103
 104         * spu-insns.h: Add soma double-float insns.
 105
 106 2007-02-20  Thiemo Seufer  <ths@mips.com>
 107             Chao-Ying Fu  <fu@mips.com>
 108
 109         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 110         (INSN_DSPR2): Add flag for DSP R2 instructions.
 111         (M_BALIGN): New macro.
 112
 113 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 114
 115         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 116         and Seg3ShortFrom with Shortform.
 117
 118 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR gas/4027
 121         * i386.h (i386_optab): Put the real "test" before the pseudo
 122         one.
 123
 124 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 125
 126         * m68k.h (m68010up): OR fido_a.
 127
 128 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 129
 130         * m68k.h (fido_a): New.
 131
 132 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 133
 134         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 135         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 136         values.
 137
 138 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 141
 142 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 143
 144         * score-inst.h (enum score_insn_type): Add Insn_internal.
 145
 146 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 147             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 148             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 149             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 150             Alan Modra  <amodra@bigpond.net.au>
 151
 152         * spu-insns.h: New file.
 153         * spu.h: New file.
 154
 155 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 156
 157         * ppc.h (PPC_OPCODE_CELL): Define.
 158
 159 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 160
 161         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 162         in amdfam10 architecture.
 163
 164 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 165
 166         * i386.h: Replace CpuMNI with CpuSSSE3.
 167
 168 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 169             Joseph Myers  <joseph@codesourcery.com>
 170             Ian Lance Taylor  <ian@wasabisystems.com>
 171             Ben Elliston  <bje@wasabisystems.com>
 172
 173         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 174
 175 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 176
 177         * score-datadep.h: New file.
 178         * score-inst.h: New file.
 179
 180 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 181
 182         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 183         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 184         movdq2q and movq2dq.
 185
 186 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 187            Michael Meissner             <michael.meissner@amd.com>
 188
 189         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 190
 191 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386.h (i386_optab): Add "nop" with memory reference.
 194
 195 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         * i386.h (i386_optab): Update comment for 64bit NOP.
 198
 199 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 200             Anton Blanchard  <anton@samba.org>
 201
 202         * ppc.h (PPC_OPCODE_POWER6): Define.
 203         Adjust whitespace.
 204
 205 2006-06-05  Thiemo Seufer  <ths@mips.com>
 206
 207         * mips.h: Improve description of MT flags.
 208
 209 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 210
 211         * m68k.h (mcf_mask): Define.
 212
 213 2006-05-05  Thiemo Seufer  <ths@mips.com>
 214             David Ung  <davidu@mips.com>
 215
 216         * mips.h (enum): Add macro M_CACHE_AB.
 217
 218 2006-05-04  Thiemo Seufer  <ths@mips.com>
 219             Nigel Stephens  <nigel@mips.com>
 220             David Ung  <davidu@mips.com>
 221
 222         * mips.h: Add INSN_SMARTMIPS define.
 223
 224 2006-04-30  Thiemo Seufer  <ths@mips.com>
 225             David Ung  <davidu@mips.com>
 226
 227         * mips.h: Defines udi bits and masks.  Add description of
 228         characters which may appear in the args field of udi
 229         instructions.
 230
 231 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 232
 233         * mips.h: Improve comments describing the bitfield instruction
 234         fields.
 235
 236 2006-04-26  Julian Brown  <julian@codesourcery.com>
 237
 238         * arm.h (FPU_VFP_EXT_V3): Define constant.
 239         (FPU_NEON_EXT_V1): Likewise.
 240         (FPU_VFP_HARD): Update.
 241         (FPU_VFP_V3): Define macro.
 242         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 243
 244 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 245
 246         * avr.h (AVR_ISA_PWMx): New.
 247
 248 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 249
 250         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 251         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 252         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 253         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 254         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 255
 256 2006-03-10  Paul Brook  <paul@codesourcery.com>
 257
 258         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 259
 260 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 261
 262         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 263         first.  Correct mask of bb "B" opcode.
 264
 265 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 266
 267         * i386.h (i386_optab): Support Intel Merom New Instructions.
 268
 269 2006-02-24  Paul Brook  <paul@codesourcery.com>
 270
 271         * arm.h: Add V7 feature bits.
 272
 273 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 276
 277 2006-01-31  Paul Brook  <paul@codesourcery.com>
 278         Richard Earnshaw <rearnsha@arm.com>
 279
 280         * arm.h: Use ARM_CPU_FEATURE.
 281         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 282         (arm_feature_set): Change to a structure.
 283         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 284         ARM_FEATURE): New macros.
 285
 286 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 287
 288         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 289         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 290         (ADD_PC_INCR_OPCODE): Don't define.
 291
 292 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         PR gas/1874
 295         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 296
 297 2005-11-14  David Ung  <davidu@mips.com>
 298
 299         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 300         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 301         save/restore encoding of the args field.
 302
 303 2005-10-28  Dave Brolley  <brolley@redhat.com>
 304
 305         Contribute the following changes:
 306         2005-02-16  Dave Brolley  <brolley@redhat.com>
 307
 308         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 309         cgen_isa_mask_* to cgen_bitset_*.
 310         * cgen.h: Likewise.
 311
 312         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 313
 314         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 315         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 316         (CGEN_CPU_TABLE): Make isas a ponter.
 317
 318         2003-09-29  Dave Brolley  <brolley@redhat.com>
 319
 320         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 321         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 322         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 323
 324         2002-12-13  Dave Brolley  <brolley@redhat.com>
 325
 326         * cgen.h (symcat.h): #include it.
 327         (cgen-bitset.h): #include it.
 328         (CGEN_ATTR_VALUE_TYPE): Now a union.
 329         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 330         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 331         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 332         * cgen-bitset.h: New file.
 333
 334 2005-09-30  Catherine Moore  <clm@cm00re.com>
 335
 336         * bfin.h: New file.
 337
 338 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 339
 340         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 341         indirect operands.
 342
 343 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 344
 345         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 346         Add FLAG_STRICT to pa10 ftest opcode.
 347
 348 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 349
 350         * hppa.h (pa_opcodes): Remove lha entries.
 351
 352 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 353
 354         * hppa.h (FLAG_STRICT): Revise comment.
 355         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 356         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 357         entries for "fdc".
 358
 359 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 360
 361         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 362
 363 2005-09-06  Chao-ying Fu  <fu@mips.com>
 364
 365         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 366         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 367         define.
 368         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 369         (INSN_ASE_MASK): Update to include INSN_MT.
 370         (INSN_MT): New define for MT ASE.
 371
 372 2005-08-25  Chao-ying Fu  <fu@mips.com>
 373
 374         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 375         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 376         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 377         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 378         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 379         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 380         instructions.
 381         (INSN_DSP): New define for DSP ASE.
 382
 383 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 384
 385         * a29k.h: Delete.
 386
 387 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 388
 389         * ppc.h (PPC_OPCODE_E300): Define.
 390
 391 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 392
 393         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 394
 395 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 396
 397         PR gas/336
 398         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 399         and pitlb.
 400
 401 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 402
 403         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 404         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 405         Add movq-s as 64-bit variants of movd-s.
 406
 407 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 408
 409         * hppa.h: Fix punctuation in comment.
 410
 411         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 412         implicit space-register addressing.  Set space-register bits on opcodes
 413         using implicit space-register addressing.  Add various missing pa20
 414         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 415         space-register addressing.  Use "fE" instead of "fe" in various
 416         fstw opcodes.
 417
 418 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 419
 420         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 421
 422 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 423
 424         * i386.h (i386_optab): Support Intel VMX Instructions.
 425
 426 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 427
 428         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 429
 430 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 431
 432         * i386.h (i386_optab): Add new insns.
 433
 434 2005-07-01  Nick Clifton  <nickc@redhat.com>
 435
 436         * sparc.h: Add typedefs to structure declarations.
 437
 438 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR 1013
 441         * i386.h (i386_optab): Update comments for 64bit addressing on
 442         mov. Allow 64bit addressing for mov and movq.
 443
 444 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 445
 446         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 447         respectively, in various floating-point load and store patterns.
 448
 449 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 450
 451         * hppa.h (FLAG_STRICT): Correct comment.
 452         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 453         PA 2.0 mneumonics when equivalent.  Entries with cache control
 454         completers now require PA 1.1.  Adjust whitespace.
 455
 456 2005-05-19  Anton Blanchard  <anton@samba.org>
 457
 458         * ppc.h (PPC_OPCODE_POWER5): Define.
 459
 460 2005-05-10  Nick Clifton  <nickc@redhat.com>
 461
 462         * Update the address and phone number of the FSF organization in
 463         the GPL notices in the following files:
 464         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 465         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 466         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 467         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 468         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 469         tic54x.h, tic80.h, v850.h, vax.h
 470
 471 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 472
 473         * i386.h (i386_optab): Add ht and hnt.
 474
 475 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 476
 477         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 478         Add xcrypt-ctr.  Provide aliases without hyphens.
 479
 480 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         Moved from ../ChangeLog
 483
 484         2005-04-12  Paul Brook  <paul@codesourcery.com>
 485         * m88k.h: Rename psr macros to avoid conflicts.
 486
 487         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 488         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 489         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 490         and ARM_ARCH_V6ZKT2.
 491
 492         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 493         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 494         Remove redundant instruction types.
 495         (struct argument): X_op - new field.
 496         (struct cst4_entry): Remove.
 497         (no_op_insn): Declare.
 498
 499         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 500         * crx.h (enum argtype): Rename types, remove unused types.
 501
 502         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 503         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 504         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 505         (enum operand_type): Rearrange operands, edit comments.
 506         replace us<N> with ui<N> for unsigned immediate.
 507         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 508         displacements (respectively).
 509         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 510         (instruction type): Add NO_TYPE_INS.
 511         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 512         (operand_entry): New field - 'flags'.
 513         (operand flags): New.
 514
 515         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 516         * crx.h (operand_type): Remove redundant types i3, i4,
 517         i5, i8, i12.
 518         Add new unsigned immediate types us3, us4, us5, us16.
 519
 520 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 521
 522         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 523         adjust them accordingly.
 524
 525 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 526
 527         * i386.h (i386_optab): Add rdtscp.
 528
 529 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 532         between memory and segment register. Allow movq for moving between
 533         general-purpose register and segment register.
 534
 535 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 536
 537         PR gas/707
 538         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 539         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 540         fnstsw.
 541
 542 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 543
 544         * m68k.h (m68008, m68ec030, m68882): Remove.
 545         (m68k_mask): New.
 546         (cpu_m68k, cpu_cf): New.
 547         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 548         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 549
 550 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 551
 552         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 553         * cgen.h (enum cgen_parse_operand_type): Add
 554         CGEN_PARSE_OPERAND_SYMBOLIC.
 555
 556 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 557
 558         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 559         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 560         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 561
 562 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 563
 564         * mips.h (struct mips_opcode): Add new pinfo2 member.
 565         (INSN_ALIAS): New define for opcode table entries that are
 566         specific instances of another entry, such as 'move' for an 'or'
 567         with a zero operand.
 568         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 569         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 570
 571 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 572
 573         * mips.h (CPU_RM9000): Define.
 574         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 575
 576 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 577
 578         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 579         to/from test registers are illegal in 64-bit mode. Add missing
 580         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 581         (previously one had to explicitly encode a rex64 prefix). Re-enable
 582         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 583         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 584
 585 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 586
 587         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 588         available only with SSE2. Change the MMX additions introduced by SSE
 589         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 590         instructions by their now designated identifier (since combining i686
 591         and 3DNow! does not really imply 3DNow!A).
 592
 593 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 594
 595         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 596         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 597
 598 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 599             Vineet Sharma      <vineets@noida.hcltech.com>
 600
 601         * maxq.h: New file: Disassembly information for the maxq port.
 602
 603 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         * i386.h (i386_optab): Put back "movzb".
 606
 607 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 608
 609         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 610         comments.  Remove member cris_ver_sim.  Add members
 611         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 612         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 613         (struct cris_support_reg, struct cris_cond15): New types.
 614         (cris_conds15): Declare.
 615         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 616         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 617         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 618         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 619         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 620         SIZE_FIELD_UNSIGNED.
 621
 622 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 623
 624         * i386.h (sldx_Suf): Remove.
 625         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 626         (q_FP): Define, implying no REX64.
 627         (x_FP, sl_FP): Imply FloatMF.
 628         (i386_optab): Split reg and mem forms of moving from segment registers
 629         so that the memory forms can ignore the 16-/32-bit operand size
 630         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 631         all non-floating-point instructions. Unite 32- and 64-bit forms of
 632         movsx, movzx, and movd. Adjust floating point operations for the above
 633         changes to the *FP macros. Add DefaultSize to floating point control
 634         insns operating on larger memory ranges. Remove left over comments
 635         hinting at certain insns being Intel-syntax ones where the ones
 636         actually meant are already gone.
 637
 638 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 639
 640         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 641         instruction type.
 642
 643 2004-09-30  Paul Brook  <paul@codesourcery.com>
 644
 645         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 646         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 647
 648 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 649
 650         * avr.h: Add support for
 651         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 652
 653 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 654
 655         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 656
 657 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 658
 659         * msp430.h (msp430_opc): Add new instructions.
 660         (msp430_rcodes): Declare new instructions.
 661         (msp430_hcodes): Likewise..
 662
 663 2004-08-13  Nick Clifton  <nickc@redhat.com>
 664
 665         PR/301
 666         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 667         processors.
 668
 669 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 670
 671         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 672
 673 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 676
 677 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 678
 679         * i386.h: Adjust instruction descriptions to better match the
 680         specification.
 681
 682 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 683
 684         * arm.h: Remove all old content.  Replace with architecture defines
 685         from gas/config/tc-arm.c.
 686
 687 2004-07-09  Andreas Schwab  <schwab@suse.de>
 688
 689         * m68k.h: Fix comment.
 690
 691 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 692
 693         * crx.h: New file.
 694
 695 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 696
 697         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 698
 699 2004-05-24  Peter Barada  <peter@the-baradas.com>
 700
 701         * m68k.h: Add 'size' to m68k_opcode.
 702
 703 2004-05-05  Peter Barada  <peter@the-baradas.com>
 704
 705         * m68k.h: Switch from ColdFire chip name to core variant.
 706
 707 2004-04-22  Peter Barada  <peter@the-baradas.com>
 708
 709         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 710         descriptions for new EMAC cases.
 711         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 712         handle Motorola MAC syntax.
 713         Allow disassembly of ColdFire V4e object files.
 714
 715 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 716
 717         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 718
 719 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 720
 721         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 722
 723 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 724
 725         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 726
 727 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 728
 729         * i386.h (i386_optab): Added xstore/xcrypt insns.
 730
 731 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 732
 733         * h8300.h (32bit ldc/stc): Add relaxing support.
 734
 735 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 736
 737         * h8300.h (BITOP): Pass MEMRELAX flag.
 738
 739 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 740
 741         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 742         except for the H8S.
 743
 744 For older changes see ChangeLog-9103
 745 \f
 746 Local Variables:
 747 mode: change-log
 748 left-margin: 8
 749 fill-column: 74
 750 version-control: never
 751 End: