include/opcode/ChangeLog

   1 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
   2
   3         * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
   4         (INSN_LOAD_COPROC): New define.
   5         (INSN_COPROC_MOVE_DELAY): Rename to...
   6         (INSN_COPROC_MOVE): New define.
   7
   8 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
   9             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
  10             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
  11             Soundararajan  <Sounderarajan.D@atmel.com>
  12
  13         * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
  14         (AVR_ISA_2xxxa): Define ISA without LPM.
  15         (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
  16         Add doc for contraint used in 16 bit lds/sts.
  17         Adjust ISA group for icall, ijmp, pop and push.
  18         Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
  19
  20 2014-05-19  Nick Clifton  <nickc@redhat.com>
  21
  22         * msp430.h (struct msp430_operand_s): Add vshift field.
  23
  24 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
  25
  26         * mips.h (INSN_ISA_MASK): Updated.
  27         (INSN_ISA32R3): New define.
  28         (INSN_ISA32R5): New define.
  29         (INSN_ISA64R3): New define.
  30         (INSN_ISA64R5): New define.
  31         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
  32         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
  33         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
  34         mips64r5.
  35         (INSN_UPTO32R3): New define.
  36         (INSN_UPTO32R5): New define.
  37         (INSN_UPTO64R3): New define.
  38         (INSN_UPTO64R5): New define.
  39         (ISA_MIPS32R3): New define.
  40         (ISA_MIPS32R5): New define.
  41         (ISA_MIPS64R3): New define.
  42         (ISA_MIPS64R5): New define.
  43         (CPU_MIPS32R3): New define.
  44         (CPU_MIPS32R5): New define.
  45         (CPU_MIPS64R3): New define.
  46         (CPU_MIPS64R5): New define.
  47
  48 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
  49
  50         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
  51
  52 2014-04-22  Christian Svensson  <blue@cmd.nu>
  53
  54         * or32.h: Delete.
  55
  56 2014-03-05  Alan Modra  <amodra@gmail.com>
  57
  58         Update copyright years.
  59
  60 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  61
  62         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
  63         microMIPS.
  64
  65 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  66             Wei-Cheng Wang  <cole945@gmail.com>
  67
  68         * nds32.h: New file for Andes NDS32.
  69
  70 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
  71
  72         * bfin.h: Remove +x file mode.
  73
  74 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  75
  76         * aarch64.h (aarch64_pstatefields): Change element type to
  77         aarch64_sys_reg.
  78
  79 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  80
  81         * arm.h (ARM_AEXT_V7VE): New define.
  82         (ARM_ARCH_V7VE): New define.
  83         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  84
  85 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  86
  87         Revert
  88
  89         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  90
  91         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  92         (aarch64_sys_reg_writeonly_p): Ditto.
  93
  94 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  95
  96         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  97         (aarch64_sys_reg_writeonly_p): Ditto.
  98
  99 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 100
 101         * aarch64.h (aarch64_sys_reg): New typedef.
 102         (aarch64_sys_regs): Change to define with the new type.
 103         (aarch64_sys_reg_deprecated_p): Declare.
 104
 105 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 106
 107         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
 108         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
 109
 110 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 111
 112         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
 113         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
 114         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 115         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 116         For MIPS, update extension character sequences after +.
 117         (ASE_MSA): New define.
 118         (ASE_MSA64): New define.
 119         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 120         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 121         For microMIPS, update extension character sequences after +.
 122
 123 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 124
 125         PR binutils/15834
 126         * i960.h: Fix typos.
 127
 128 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 129
 130         * mips.h: Remove references to "+I" and imm2_expr.
 131
 132 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 133
 134         * mips.h (M_DEXT, M_DINS): Delete.
 135
 136 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 137
 138         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 139         (mips_optional_operand_p): New function.
 140
 141 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 142             Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * mips.h: Document new VU0 operand characters.
 145         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 146         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 147         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 148         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 149         (mips_vu0_channel_mask): Declare.
 150
 151 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 152
 153         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 154         (mips_int_operand_min, mips_int_operand_max): New functions.
 155         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 156
 157 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 158
 159         * mips.h (mips_decode_reg_operand): New function.
 160         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 161         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 162         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 163         New macros.
 164         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 165         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 166         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 167         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 168         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 169         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 170         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 171         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 172         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 173         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 174         macros to cover the gaps.
 175         (INSN2_MOD_SP): Replace with...
 176         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 177         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 178         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 179         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 180         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 181         Delete.
 182
 183 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 184
 185         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 186         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 187         (MIPS16_INSN_COND_BRANCH): Delete.
 188
 189 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 190             Kirill Yukhin  <kirill.yukhin@intel.com>
 191             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 192
 193         * i386.h (BND_PREFIX_OPCODE): New.
 194
 195 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 196
 197         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 198         OP_SAVE_RESTORE_LIST.
 199         (decode_mips16_operand): Declare.
 200
 201 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 202
 203         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 204         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 205         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 206         (mips_pcrel_operand): New structures.
 207         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 208         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 209         (decode_mips_operand, decode_micromips_operand): Declare.
 210
 211 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 212
 213         * mips.h: Document MIPS16 "I" opcode.
 214
 215 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 216
 217         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 218         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 219         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 220         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 221         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 222         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 223         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 224         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 225         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 226         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 227         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 228         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 229         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 230         Rename to...
 231         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 232         (M_USD_AB): ...these.
 233
 234 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 235
 236         * mips.h: Remove documentation of "[" and "]".  Update documentation
 237         of "k" and the MDMX formats.
 238
 239 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 240
 241         * mips.h: Update documentation of "+s" and "+S".
 242
 243 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 244
 245         * mips.h: Document "+i".
 246
 247 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 248
 249         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 250         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 251         Delete.
 252         (INSN2_WRITE_GPR_MHI): Rename to...
 253         (INSN2_WRITE_GPR_MH): ...this.
 254
 255 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 256
 257         * mips.h: Remove documentation of "+D" and "+T".
 258
 259 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 260
 261         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 262         Use "source" rather than "destination" for microMIPS "G".
 263
 264 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 265
 266         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 267         values.
 268
 269 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 270
 271         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 272
 273 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 274             Maciej W. Rozycki  <macro@codesourcery.com>
 275             Chao-Ying Fu  <fu@mips.com>
 276
 277         * mips.h (OP_SH_EVAOFFSET): Define.
 278         (OP_MASK_EVAOFFSET): Define.
 279         (INSN_ASE_MASK): Delete.
 280         (ASE_EVA): Define.
 281         (M_CACHEE_AB, M_CACHEE_OB): New.
 282         (M_LBE_OB, M_LBE_AB): New.
 283         (M_LBUE_OB, M_LBUE_AB): New.
 284         (M_LHE_OB, M_LHE_AB): New.
 285         (M_LHUE_OB, M_LHUE_AB): New.
 286         (M_LLE_AB, M_LLE_OB): New.
 287         (M_LWE_OB, M_LWE_AB): New.
 288         (M_LWLE_AB, M_LWLE_OB): New.
 289         (M_LWRE_AB, M_LWRE_OB): New.
 290         (M_PREFE_AB, M_PREFE_OB): New.
 291         (M_SCE_AB, M_SCE_OB): New.
 292         (M_SBE_OB, M_SBE_AB): New.
 293         (M_SHE_OB, M_SHE_AB): New.
 294         (M_SWE_OB, M_SWE_AB): New.
 295         (M_SWLE_AB, M_SWLE_OB): New.
 296         (M_SWRE_AB, M_SWRE_OB): New.
 297         (MICROMIPSOP_SH_EVAOFFSET): Define.
 298         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 299
 300 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 301
 302         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 303
 304 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 305
 306         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 307
 308 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 309
 310         * mips.h (OP_MASK_CODE10): Correct definition.
 311         (OP_SH_CODE10): Likewise.
 312         Add a comment that "+J" is used now for OP_*CODE10.
 313         (INSN_ASE_MASK): Update.
 314         (INSN_VIRT): New macro.
 315         (INSN_VIRT64): New macro
 316
 317 2013-05-02  Nick Clifton  <nickc@redhat.com>
 318
 319         * msp430.h: Add patterns for MSP430X instructions.
 320
 321 2013-04-06  David S. Miller  <davem@davemloft.net>
 322
 323         * sparc.h (F_PREFERRED): Define.
 324         (F_PREF_ALIAS): Define.
 325
 326 2013-04-03  Nick Clifton  <nickc@redhat.com>
 327
 328         * v850.h (V850_INVERSE_PCREL): Define.
 329
 330 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 331
 332         PR binutils/15068
 333         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 334
 335 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 336
 337         PR binutils/15068
 338         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 339         Add 16-bit opcodes.
 340         * tic6xc-opcode-table.h: Add 16-bit insns.
 341         * tic6x.h: Add support for 16-bit insns.
 342
 343 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 344
 345         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 346         and mov.b/w/l Rs,@(d:32,ERd).
 347
 348 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 349
 350         PR gas/15082
 351         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 352         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 353         tic6x_operand_xregpair operand coding type.
 354         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 355         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 356         TIC6X_FLAG_NO_CROSS.
 357
 358 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 359
 360         PR gas/15095
 361         * tic6x.h (enum tic6x_coding_method): Add
 362         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 363         separately the msb and lsb of a register pair.  This is needed to
 364         encode the opcodes in the same way as TI assembler does.
 365         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 366         and rsqrdp opcodes to use the new field coding types.
 367
 368 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 369
 370         * arm.h (CRC_EXT_ARMV8): New constant.
 371         (ARCH_CRC_ARMV8): New macro.
 372
 373 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 374
 375         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 376
 377 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 378             Andrew Jenner <andrew@codesourcery.com>
 379
 380         Based on patches from Altera Corporation.
 381
 382         * nios2.h: New file.
 383
 384 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 385
 386         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 387
 388 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 389
 390         PR gas/15069
 391         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 392
 393 2013-01-24  Nick Clifton  <nickc@redhat.com>
 394
 395         * v850.h: Add e3v5 support.
 396
 397 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 398
 399         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 400
 401 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 402
 403         * ppc.h (PPC_OPCODE_POWER8): New define.
 404         (PPC_OPCODE_HTM): Likewise.
 405
 406 2013-01-10  Will Newton <will.newton@imgtec.com>
 407
 408         * metag.h: New file.
 409
 410 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 411
 412         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 413         (match_opcode): Rename to cr16_match_opcode.
 414
 415 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 416
 417         * mips.h: Add support for r5900 instructions including lq and sq.
 418
 419 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 420
 421         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 422         (make_instruction,match_opcode): Added function prototypes.
 423         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 424
 425 2012-11-23  Alan Modra  <amodra@gmail.com>
 426
 427         * ppc.h (ppc_parse_cpu): Update prototype.
 428
 429 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 430
 431         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 432         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 433
 434 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 435
 436         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 437
 438 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 439
 440         * ia64.h (ia64_opnd): Add new operand types.
 441
 442 2012-08-21  David S. Miller  <davem@davemloft.net>
 443
 444         * sparc.h (F3F4): New macro.
 445
 446 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 447             Laurent Desnogues  <laurent.desnogues@arm.com>
 448             Jim MacArthur  <jim.macarthur@arm.com>
 449             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 450             Nigel Stephens  <nigel.stephens@arm.com>
 451             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 452             Richard Earnshaw  <rearnsha@arm.com>
 453             Sofiane Naci  <sofiane.naci@arm.com>
 454             Tejas Belagod  <tejas.belagod@arm.com>
 455             Yufeng Zhang  <yufeng.zhang@arm.com>
 456
 457         * aarch64.h: New file.
 458
 459 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 460             Maciej W. Rozycki  <macro@codesourcery.com>
 461
 462         * mips.h (mips_opcode): Add the exclusions field.
 463         (OPCODE_IS_MEMBER): Remove macro.
 464         (cpu_is_member): New inline function.
 465         (opcode_is_member): Likewise.
 466
 467 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 468             Catherine Moore  <clm@codesourcery.com>
 469             Maciej W. Rozycki  <macro@codesourcery.com>
 470
 471         * mips.h: Document microMIPS DSP ASE usage.
 472         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 473         microMIPS DSP ASE support.
 474         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 475         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 476         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 477         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 478         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 479         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 480         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 481
 482 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 483
 484         * mips.h: Fix a typo in description.
 485
 486 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 487
 488         * avr.h: (AVR_ISA_XCH): New define.
 489         (AVR_ISA_XMEGA): Use it.
 490         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 491
 492 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 493
 494         * m68hc11.h: Add XGate definitions.
 495         (struct m68hc11_opcode): Add xg_mask field.
 496
 497 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 498             Maciej W. Rozycki  <macro@codesourcery.com>
 499             Rhonda Wittels  <rhonda@codesourcery.com>
 500
 501         * ppc.h (PPC_OPCODE_VLE): New definition.
 502         (PPC_OP_SA): New macro.
 503         (PPC_OP_SE_VLE): New macro.
 504         (PPC_OP): Use a variable shift amount.
 505         (powerpc_operand): Update comments.
 506         (PPC_OPSHIFT_INV): New macro.
 507         (PPC_OPERAND_CR): Replace with...
 508         (PPC_OPERAND_CR_BIT): ...this and
 509         (PPC_OPERAND_CR_REG): ...this.
 510
 511
 512 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 513
 514         * xgate.h: Header file for XGATE assembler.
 515
 516 2012-04-27  David S. Miller  <davem@davemloft.net>
 517
 518         * sparc.h: Document new arg code' )' for crypto RS3
 519         immediates.
 520
 521         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 522         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 523         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 524         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 525         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 526         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 527         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 528         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 529         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 530         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 531         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 532
 533 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 534
 535         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 536
 537 2012-02-27  Alan Modra  <amodra@gmail.com>
 538
 539         * crx.h (cst4_map): Update declaration.
 540
 541 2012-02-25  Walter Lee  <walt@tilera.com>
 542
 543         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 544         TILEGX_OPC_LD_TLS.
 545         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 546         TILEPRO_OPC_LW_TLS_SN.
 547
 548 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 551         (XRELEASE_PREFIX_OPCODE): Likewise.
 552
 553 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 554             Adam Nemet  <anemet@caviumnetworks.com>
 555
 556         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 557         (INSN_OCTEON2): New macro.
 558         (CPU_OCTEON2): New macro.
 559         (OPCODE_IS_MEMBER): Add Octeon2.
 560
 561 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 562
 563         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 564         (INSN_OCTEONP): New macro.
 565         (CPU_OCTEONP): New macro.
 566         (OPCODE_IS_MEMBER): Add Octeon+.
 567         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 568
 569 2011-11-01  DJ Delorie  <dj@redhat.com>
 570
 571         * rl78.h: New file.
 572
 573 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 574
 575         * mips.h: Fix a typo in description.
 576
 577 2011-09-21  David S. Miller  <davem@davemloft.net>
 578
 579         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 580         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 581         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 582         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 583
 584 2011-08-09  Chao-ying Fu  <fu@mips.com>
 585             Maciej W. Rozycki  <macro@codesourcery.com>
 586
 587         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 588         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 589         (INSN_ASE_MASK): Add the MCU bit.
 590         (INSN_MCU): New macro.
 591         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 592         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 593
 594 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 595
 596         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 597         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 598         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 599         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 600         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 601         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 602         (INSN2_READ_GPR_MMN): Likewise.
 603         (INSN2_READ_FPR_D): Change the bit used.
 604         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 605         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 606         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 607         (INSN2_COND_BRANCH): Likewise.
 608         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 609         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 610         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 611         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 612         (INSN2_MOD_GPR_MN): Likewise.
 613
 614 2011-08-05  David S. Miller  <davem@davemloft.net>
 615
 616         * sparc.h: Document new format codes '4', '5', and '('.
 617         (OPF_LOW4, RS3): New macros.
 618
 619 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 620
 621         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 622         order of flags documented.
 623
 624 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 625
 626         * mips.h: Clarify the description of microMIPS instruction
 627         manipulation macros.
 628         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 629
 630 2011-07-24  Chao-ying Fu  <fu@mips.com>
 631             Maciej W. Rozycki  <macro@codesourcery.com>
 632
 633         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 634         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 635         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 636         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 637         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 638         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 639         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 640         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 641         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 642         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 643         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 644         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 645         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 646         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 647         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 648         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 649         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 650         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 651         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 652         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 653         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 654         (INSN_WRITE_GPR_S): New macro.
 655         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 656         (INSN2_READ_FPR_D): Likewise.
 657         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 658         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 659         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 660         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 661         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 662         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 663         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 664         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 665         (CPU_MICROMIPS): New macro.
 666         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 667         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 668         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 669         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 670         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 671         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 672         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 673         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 674         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 675         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 676         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 677         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 678         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 679         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 680         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 681         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 682         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 683         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 684         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 685         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 686         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 687         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 688         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 689         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 690         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 691         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 692         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 693         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 694         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 695         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 696         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 697         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 698         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 699         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 700         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 701         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 702         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 703         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 704         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 705         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 706         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 707         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 708         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 709         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 710         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 711         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 712         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 713         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 714         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 715         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 716         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 717         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 718         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 719         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 720         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 721         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 722         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 723         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 724         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 725         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 726         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 727         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 728         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 729         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 730         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 731         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 732         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 733         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 734         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 735         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 736         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 737         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 738         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 739         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 740         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 741         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 742         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 743         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 744         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 745         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 746         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 747         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 748         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 749         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 750         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 751         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 752         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 753         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 754         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 755         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 756         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 757         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 758         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 759         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 760         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 761         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 762         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 763         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 764         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 765         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 766         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 767         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 768         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 769         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 770         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 771         (micromips_opcodes): New declaration.
 772         (bfd_micromips_num_opcodes): Likewise.
 773
 774 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 775
 776         * mips.h (INSN_TRAP): Rename to...
 777         (INSN_NO_DELAY_SLOT): ... this.
 778         (INSN_SYNC): Remove macro.
 779
 780 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 781
 782         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 783         a duplicate of AVR_ISA_SPM.
 784
 785 2011-07-01  Nick Clifton  <nickc@redhat.com>
 786
 787         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 788
 789 2011-06-18  Robin Getz  <robin.getz@analog.com>
 790
 791         * bfin.h (is_macmod_signed): New func
 792
 793 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 794
 795         * bfin.h (is_macmod_pmove): Add missing space before func args.
 796         (is_macmod_hmove): Likewise.
 797
 798 2011-06-13  Walter Lee  <walt@tilera.com>
 799
 800         * tilegx.h: New file.
 801         * tilepro.h: New file.
 802
 803 2011-05-31  Paul Brook  <paul@codesourcery.com>
 804
 805         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 806
 807 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 808
 809         * s390.h: Replace S390_OPERAND_REG_EVEN with
 810         S390_OPERAND_REG_PAIR.
 811
 812 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 813
 814         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 815
 816 2011-04-18  Julian Brown  <julian@codesourcery.com>
 817
 818         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 819
 820 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 821
 822         PR gas/12296
 823         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 824
 825 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 826
 827         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 828         New instruction set flags.
 829         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 830
 831 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 832
 833         * mips.h (M_PREF_AB): New enum value.
 834
 835 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 836
 837         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 838         M_IU): Define.
 839         (is_macmod_pmove, is_macmod_hmove): New functions.
 840
 841 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 842
 843         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 844
 845 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 846
 847         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 848         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 849
 850 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 851
 852         PR gas/11395
 853         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 854         "bb" entries.
 855
 856 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 857
 858         PR gas/11395
 859         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 860
 861 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 862
 863         * mips.h: Update commentary after last commit.
 864
 865 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 866
 867         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 868         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 869         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 870
 871 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 872
 873         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 874
 875 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 876
 877         * mips.h: Fix previous commit.
 878
 879 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 880
 881         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 882         (INSN_LOONGSON_3A): Clear bit 31.
 883
 884 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 885
 886         PR gas/12198
 887         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 888         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 889         (ARM_ARCH_V6M_ONLY): New define.
 890
 891 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 892
 893         * mips.h (INSN_LOONGSON_3A): Defined.
 894         (CPU_LOONGSON_3A): Defined.
 895         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 896
 897 2010-10-09  Matt Rice  <ratmice@gmail.com>
 898
 899         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 900         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 901
 902 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 903
 904         * arm.h (ARM_EXT_VIRT): New define.
 905         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 906         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 907         Extensions.
 908
 909 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 910
 911         * arm.h (ARM_AEXT_ADIV): New define.
 912         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 913
 914 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 915
 916         * arm.h (ARM_EXT_OS): New define.
 917         (ARM_AEXT_V6SM): Likewise.
 918         (ARM_ARCH_V6SM): Likewise.
 919
 920 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 921
 922         * arm.h (ARM_EXT_MP): Add.
 923         (ARM_ARCH_V7A_MP): Likewise.
 924
 925 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 926
 927         * bfin.h: Declare pseudoChr structs/defines.
 928
 929 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 930
 931         * bfin.h: Strip trailing whitespace.
 932
 933 2010-07-29  DJ Delorie  <dj@redhat.com>
 934
 935         * rx.h (RX_Operand_Type): Add TwoReg.
 936         (RX_Opcode_ID): Remove ediv and ediv2.
 937
 938 2010-07-27  DJ Delorie  <dj@redhat.com>
 939
 940         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 941
 942 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 943             Ina Pandit  <ina.pandit@kpitcummins.com>
 944
 945         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 946         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 947         PROCESSOR_V850E2_ALL.
 948         Remove PROCESSOR_V850EA support.
 949         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 950         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 951         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 952         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 953         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 954         V850_OPERAND_PERCENT.
 955         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 956         V850_NOT_R0.
 957         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 958         and V850E_PUSH_POP
 959
 960 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 961
 962         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 963         (MIPS16_INSN_BRANCH): Rename to...
 964         (MIPS16_INSN_COND_BRANCH): ... this.
 965
 966 2010-07-03  Alan Modra  <amodra@gmail.com>
 967
 968         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 969         Renumber other PPC_OPCODE defines.
 970
 971 2010-07-03  Alan Modra  <amodra@gmail.com>
 972
 973         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 974
 975 2010-06-29  Alan Modra  <amodra@gmail.com>
 976
 977         * maxq.h: Delete file.
 978
 979 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 980
 981         * ppc.h (PPC_OPCODE_E500): Define.
 982
 983 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 984
 985         * opcode/mips.h (INSN_MIPS16): Remove.
 986
 987 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 988
 989         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 990
 991 2010-04-15  Nick Clifton  <nickc@redhat.com>
 992
 993         * alpha.h: Update copyright notice to use GPLv3.
 994         * arc.h: Likewise.
 995         * arm.h: Likewise.
 996         * avr.h: Likewise.
 997         * bfin.h: Likewise.
 998         * cgen.h: Likewise.
 999         * convex.h: Likewise.
1000         * cr16.h: Likewise.
1001         * cris.h: Likewise.
1002         * crx.h: Likewise.
1003         * d10v.h: Likewise.
1004         * d30v.h: Likewise.
1005         * dlx.h: Likewise.
1006         * h8300.h: Likewise.
1007         * hppa.h: Likewise.
1008         * i370.h: Likewise.
1009         * i386.h: Likewise.
1010         * i860.h: Likewise.
1011         * i960.h: Likewise.
1012         * ia64.h: Likewise.
1013         * m68hc11.h: Likewise.
1014         * m68k.h: Likewise.
1015         * m88k.h: Likewise.
1016         * maxq.h: Likewise.
1017         * mips.h: Likewise.
1018         * mmix.h: Likewise.
1019         * mn10200.h: Likewise.
1020         * mn10300.h: Likewise.
1021         * msp430.h: Likewise.
1022         * np1.h: Likewise.
1023         * ns32k.h: Likewise.
1024         * or32.h: Likewise.
1025         * pdp11.h: Likewise.
1026         * pj.h: Likewise.
1027         * pn.h: Likewise.
1028         * ppc.h: Likewise.
1029         * pyr.h: Likewise.
1030         * rx.h: Likewise.
1031         * s390.h: Likewise.
1032         * score-datadep.h: Likewise.
1033         * score-inst.h: Likewise.
1034         * sparc.h: Likewise.
1035         * spu-insns.h: Likewise.
1036         * spu.h: Likewise.
1037         * tic30.h: Likewise.
1038         * tic4x.h: Likewise.
1039         * tic54x.h: Likewise.
1040         * tic80.h: Likewise.
1041         * v850.h: Likewise.
1042         * vax.h: Likewise.
1043
1044 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1045
1046         * tic6x-control-registers.h, tic6x-insn-formats.h,
1047         tic6x-opcode-table.h, tic6x.h: New.
1048
1049 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1050
1051         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1052
1053 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1054
1055         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1056
1057 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         * ia64.h (ia64_find_opcode): Remove argument name.
1060         (ia64_find_next_opcode): Likewise.
1061         (ia64_dis_opcode): Likewise.
1062         (ia64_free_opcode): Likewise.
1063         (ia64_find_dependency): Likewise.
1064
1065 2009-11-22  Doug Evans  <dje@sebabeach.org>
1066
1067         * cgen.h: Include bfd_stdint.h.
1068         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1069
1070 2009-11-18  Paul Brook  <paul@codesourcery.com>
1071
1072         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1073
1074 2009-11-17  Paul Brook  <paul@codesourcery.com>
1075         Daniel Jacobowitz  <dan@codesourcery.com>
1076
1077         * arm.h (ARM_EXT_V6_DSP): Define.
1078         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1079         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1080
1081 2009-11-04  DJ Delorie  <dj@redhat.com>
1082
1083         * rx.h (rx_decode_opcode) (mvtipl): Add.
1084         (mvtcp, mvfcp, opecp): Remove.
1085
1086 2009-11-02  Paul Brook  <paul@codesourcery.com>
1087
1088         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1089         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1090         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1091         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1092         FPU_ARCH_NEON_VFP_V4): Define.
1093
1094 2009-10-23  Doug Evans  <dje@sebabeach.org>
1095
1096         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1097         * cgen.h: Update.  Improve multi-inclusion macro name.
1098
1099 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1100
1101         * ppc.h (PPC_OPCODE_476): Define.
1102
1103 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1104
1105         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1106
1107 2009-09-29  DJ Delorie  <dj@redhat.com>
1108
1109         * rx.h: New file.
1110
1111 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1112
1113         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1114
1115 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1116
1117         * ppc.h (PPC_OPCODE_PPCA2): New.
1118
1119 2009-09-05  Martin Thuresson  <martin@mtme.org>
1120
1121         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1122
1123 2009-08-29  Martin Thuresson  <martin@mtme.org>
1124
1125         * tic30.h (template): Rename type template to
1126         insn_template. Updated code to use new name.
1127         * tic54x.h (template): Rename type template to
1128         insn_template.
1129
1130 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1131
1132         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1133
1134 2009-06-11  Anthony Green  <green@moxielogic.com>
1135
1136         * moxie.h (MOXIE_F3_PCREL): Define.
1137         (moxie_form3_opc_info): Grow.
1138
1139 2009-06-06  Anthony Green  <green@moxielogic.com>
1140
1141         * moxie.h (MOXIE_F1_M): Define.
1142
1143 2009-04-15  Anthony Green  <green@moxielogic.com>
1144
1145         * moxie.h: Created.
1146
1147 2009-04-06  DJ Delorie  <dj@redhat.com>
1148
1149         * h8300.h: Add relaxation attributes to MOVA opcodes.
1150
1151 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1152
1153         * ppc.h (ppc_parse_cpu): Declare.
1154
1155 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1156
1157         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1158         and _IMM11 for mbitclr and mbitset.
1159         * score-datadep.h: Update dependency information.
1160
1161 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1162
1163         * ppc.h (PPC_OPCODE_POWER7): New.
1164
1165 2009-02-06  Doug Evans  <dje@google.com>
1166
1167         * i386.h: Add comment regarding sse* insns and prefixes.
1168
1169 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1170
1171         * mips.h (INSN_XLR): Define.
1172         (INSN_CHIP_MASK): Update.
1173         (CPU_XLR): Define.
1174         (OPCODE_IS_MEMBER): Update.
1175         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1176
1177 2009-01-28  Doug Evans  <dje@google.com>
1178
1179         * opcode/i386.h: Add multiple inclusion protection.
1180         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1181         (EDI_REG_NUM): New macros.
1182         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1183         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1184         (REX_PREFIX_P): New macro.
1185
1186 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1187
1188         * ppc.h (struct powerpc_opcode): New field "deprecated".
1189         (PPC_OPCODE_NOPOWER4): Delete.
1190
1191 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1192
1193         * mips.h: Define CPU_R14000, CPU_R16000.
1194         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1195
1196 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1197
1198         * arm.h (FPU_NEON_FP16): New.
1199         (FPU_ARCH_NEON_FP16): New.
1200
1201 2008-11-06  Chao-ying Fu  <fu@mips.com>
1202
1203         * mips.h: Doucument '1' for 5-bit sync type.
1204
1205 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1206
1207         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1208         IA64_RS_CR.
1209
1210 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1211
1212         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1213
1214 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1215
1216         * ppc.h (PPC_OPCODE_405): Define.
1217         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1218
1219 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1220
1221         * ppc.h (ppc_cpu_t): New typedef.
1222         (struct powerpc_opcode <flags>): Use it.
1223         (struct powerpc_operand <insert, extract>): Likewise.
1224         (struct powerpc_macro <flags>): Likewise.
1225
1226 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1227
1228         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1229         Update comment before MIPS16 field descriptors to mention MIPS16.
1230         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1231         BBIT.
1232         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1233         New bit masks and shift counts for cins and exts.
1234
1235         * mips.h: Document new field descriptors +Q.
1236         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1237
1238 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1239
1240         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1241         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1242
1243 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1244
1245         * ppc.h: (PPC_OPCODE_E500MC): New.
1246
1247 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1248
1249         * i386.h (MAX_OPERANDS): Set to 5.
1250         (MAX_MNEM_SIZE): Changed to 20.
1251
1252 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1253
1254         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1255
1256 2008-03-09  Paul Brook  <paul@codesourcery.com>
1257
1258         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1259
1260 2008-03-04  Paul Brook  <paul@codesourcery.com>
1261
1262         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1263         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1264         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1265
1266 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1267             Nick Clifton  <nickc@redhat.com>
1268
1269         PR 3134
1270         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1271         with a 32-bit displacement but without the top bit of the 4th byte
1272         set.
1273
1274 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1275
1276         * cr16.h (cr16_num_optab): Declared.
1277
1278 2008-02-14  Hakan Ardo  <hakan@debian.org>
1279
1280         PR gas/2626
1281         * avr.h (AVR_ISA_2xxe): Define.
1282
1283 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1284
1285         * mips.h: Update copyright.
1286         (INSN_CHIP_MASK): New macro.
1287         (INSN_OCTEON): New macro.
1288         (CPU_OCTEON): New macro.
1289         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1290
1291 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1292
1293         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1294
1295 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1296
1297         * avr.h (AVR_ISA_USB162): Add new opcode set.
1298         (AVR_ISA_AVR3): Likewise.
1299
1300 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1301
1302         * mips.h (INSN_LOONGSON_2E): New.
1303         (INSN_LOONGSON_2F): New.
1304         (CPU_LOONGSON_2E): New.
1305         (CPU_LOONGSON_2F): New.
1306         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1307
1308 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1309
1310         * mips.h (INSN_ISA*): Redefine certain values as an
1311         enumeration.  Update comments.
1312         (mips_isa_table): New.
1313         (ISA_MIPS*): Redefine to match enumeration.
1314         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1315         values.
1316
1317 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1318
1319         * ppc.h (PPC_OPCODE_PPCPS): New.
1320
1321 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1322
1323         * m68k.h: Document j K & E.
1324
1325 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1326
1327         * cr16.h: New file for CR16 target.
1328
1329 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1330
1331         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1332
1333 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1334
1335         * m68k.h (mcfisa_c): New.
1336         (mcfusp, mcf_mask): Adjust.
1337
1338 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1339
1340         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1341         (num_powerpc_operands): Declare.
1342         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1343         (PPC_OPERAND_PLUS1): Define.
1344
1345 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1346
1347         * i386.h (REX_MODE64): Renamed to ...
1348         (REX_W): This.
1349         (REX_EXTX): Renamed to ...
1350         (REX_R): This.
1351         (REX_EXTY): Renamed to ...
1352         (REX_X): This.
1353         (REX_EXTZ): Renamed to ...
1354         (REX_B): This.
1355
1356 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1357
1358         * i386.h: Add entries from config/tc-i386.h and move tables
1359         to opcodes/i386-opc.h.
1360
1361 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1362
1363         * i386.h (FloatDR): Removed.
1364         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1365
1366 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1367
1368         * spu-insns.h: Add soma double-float insns.
1369
1370 2007-02-20  Thiemo Seufer  <ths@mips.com>
1371             Chao-Ying Fu  <fu@mips.com>
1372
1373         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1374         (INSN_DSPR2): Add flag for DSP R2 instructions.
1375         (M_BALIGN): New macro.
1376
1377 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1378
1379         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1380         and Seg3ShortFrom with Shortform.
1381
1382 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1383
1384         PR gas/4027
1385         * i386.h (i386_optab): Put the real "test" before the pseudo
1386         one.
1387
1388 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1389
1390         * m68k.h (m68010up): OR fido_a.
1391
1392 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1393
1394         * m68k.h (fido_a): New.
1395
1396 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1397
1398         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1399         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1400         values.
1401
1402 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1403
1404         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1405
1406 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1407
1408         * score-inst.h (enum score_insn_type): Add Insn_internal.
1409
1410 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1411             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1412             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1413             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1414             Alan Modra  <amodra@bigpond.net.au>
1415
1416         * spu-insns.h: New file.
1417         * spu.h: New file.
1418
1419 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1420
1421         * ppc.h (PPC_OPCODE_CELL): Define.
1422
1423 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1424
1425         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1426         in amdfam10 architecture.
1427
1428 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1429
1430         * i386.h: Replace CpuMNI with CpuSSSE3.
1431
1432 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1433             Joseph Myers  <joseph@codesourcery.com>
1434             Ian Lance Taylor  <ian@wasabisystems.com>
1435             Ben Elliston  <bje@wasabisystems.com>
1436
1437         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1438
1439 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1440
1441         * score-datadep.h: New file.
1442         * score-inst.h: New file.
1443
1444 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1445
1446         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1447         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1448         movdq2q and movq2dq.
1449
1450 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1451            Michael Meissner             <michael.meissner@amd.com>
1452
1453         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1454
1455 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1456
1457         * i386.h (i386_optab): Add "nop" with memory reference.
1458
1459 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1460
1461         * i386.h (i386_optab): Update comment for 64bit NOP.
1462
1463 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1464             Anton Blanchard  <anton@samba.org>
1465
1466         * ppc.h (PPC_OPCODE_POWER6): Define.
1467         Adjust whitespace.
1468
1469 2006-06-05  Thiemo Seufer  <ths@mips.com>
1470
1471         * mips.h: Improve description of MT flags.
1472
1473 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1474
1475         * m68k.h (mcf_mask): Define.
1476
1477 2006-05-05  Thiemo Seufer  <ths@mips.com>
1478             David Ung  <davidu@mips.com>
1479
1480         * mips.h (enum): Add macro M_CACHE_AB.
1481
1482 2006-05-04  Thiemo Seufer  <ths@mips.com>
1483             Nigel Stephens  <nigel@mips.com>
1484             David Ung  <davidu@mips.com>
1485
1486         * mips.h: Add INSN_SMARTMIPS define.
1487
1488 2006-04-30  Thiemo Seufer  <ths@mips.com>
1489             David Ung  <davidu@mips.com>
1490
1491         * mips.h: Defines udi bits and masks.  Add description of
1492         characters which may appear in the args field of udi
1493         instructions.
1494
1495 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1496
1497         * mips.h: Improve comments describing the bitfield instruction
1498         fields.
1499
1500 2006-04-26  Julian Brown  <julian@codesourcery.com>
1501
1502         * arm.h (FPU_VFP_EXT_V3): Define constant.
1503         (FPU_NEON_EXT_V1): Likewise.
1504         (FPU_VFP_HARD): Update.
1505         (FPU_VFP_V3): Define macro.
1506         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1507
1508 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1509
1510         * avr.h (AVR_ISA_PWMx): New.
1511
1512 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1513
1514         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1515         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1516         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1517         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1518         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1519
1520 2006-03-10  Paul Brook  <paul@codesourcery.com>
1521
1522         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1523
1524 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1525
1526         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1527         first.  Correct mask of bb "B" opcode.
1528
1529 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1530
1531         * i386.h (i386_optab): Support Intel Merom New Instructions.
1532
1533 2006-02-24  Paul Brook  <paul@codesourcery.com>
1534
1535         * arm.h: Add V7 feature bits.
1536
1537 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1538
1539         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1540
1541 2006-01-31  Paul Brook  <paul@codesourcery.com>
1542         Richard Earnshaw <rearnsha@arm.com>
1543
1544         * arm.h: Use ARM_CPU_FEATURE.
1545         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1546         (arm_feature_set): Change to a structure.
1547         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1548         ARM_FEATURE): New macros.
1549
1550 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1551
1552         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1553         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1554         (ADD_PC_INCR_OPCODE): Don't define.
1555
1556 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1557
1558         PR gas/1874
1559         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1560
1561 2005-11-14  David Ung  <davidu@mips.com>
1562
1563         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1564         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1565         save/restore encoding of the args field.
1566
1567 2005-10-28  Dave Brolley  <brolley@redhat.com>
1568
1569         Contribute the following changes:
1570         2005-02-16  Dave Brolley  <brolley@redhat.com>
1571
1572         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1573         cgen_isa_mask_* to cgen_bitset_*.
1574         * cgen.h: Likewise.
1575
1576         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1577
1578         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1579         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1580         (CGEN_CPU_TABLE): Make isas a ponter.
1581
1582         2003-09-29  Dave Brolley  <brolley@redhat.com>
1583
1584         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1585         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1586         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1587
1588         2002-12-13  Dave Brolley  <brolley@redhat.com>
1589
1590         * cgen.h (symcat.h): #include it.
1591         (cgen-bitset.h): #include it.
1592         (CGEN_ATTR_VALUE_TYPE): Now a union.
1593         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1594         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1595         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1596         * cgen-bitset.h: New file.
1597
1598 2005-09-30  Catherine Moore  <clm@cm00re.com>
1599
1600         * bfin.h: New file.
1601
1602 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1603
1604         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1605         indirect operands.
1606
1607 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1608
1609         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1610         Add FLAG_STRICT to pa10 ftest opcode.
1611
1612 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1613
1614         * hppa.h (pa_opcodes): Remove lha entries.
1615
1616 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1617
1618         * hppa.h (FLAG_STRICT): Revise comment.
1619         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1620         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1621         entries for "fdc".
1622
1623 2005-09-30  Catherine Moore  <clm@cm00re.com>
1624
1625         * bfin.h: New file.
1626
1627 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1628
1629         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1630
1631 2005-09-06  Chao-ying Fu  <fu@mips.com>
1632
1633         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1634         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1635         define.
1636         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1637         (INSN_ASE_MASK): Update to include INSN_MT.
1638         (INSN_MT): New define for MT ASE.
1639
1640 2005-08-25  Chao-ying Fu  <fu@mips.com>
1641
1642         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1643         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1644         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1645         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1646         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1647         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1648         instructions.
1649         (INSN_DSP): New define for DSP ASE.
1650
1651 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1652
1653         * a29k.h: Delete.
1654
1655 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1656
1657         * ppc.h (PPC_OPCODE_E300): Define.
1658
1659 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1660
1661         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1662
1663 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1664
1665         PR gas/336
1666         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1667         and pitlb.
1668
1669 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1670
1671         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1672         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1673         Add movq-s as 64-bit variants of movd-s.
1674
1675 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1676
1677         * hppa.h: Fix punctuation in comment.
1678
1679         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1680         implicit space-register addressing.  Set space-register bits on opcodes
1681         using implicit space-register addressing.  Add various missing pa20
1682         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1683         space-register addressing.  Use "fE" instead of "fe" in various
1684         fstw opcodes.
1685
1686 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1687
1688         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1689
1690 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1691
1692         * i386.h (i386_optab): Support Intel VMX Instructions.
1693
1694 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1695
1696         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1697
1698 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1699
1700         * i386.h (i386_optab): Add new insns.
1701
1702 2005-07-01  Nick Clifton  <nickc@redhat.com>
1703
1704         * sparc.h: Add typedefs to structure declarations.
1705
1706 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1707
1708         PR 1013
1709         * i386.h (i386_optab): Update comments for 64bit addressing on
1710         mov. Allow 64bit addressing for mov and movq.
1711
1712 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1713
1714         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1715         respectively, in various floating-point load and store patterns.
1716
1717 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1718
1719         * hppa.h (FLAG_STRICT): Correct comment.
1720         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1721         PA 2.0 mneumonics when equivalent.  Entries with cache control
1722         completers now require PA 1.1.  Adjust whitespace.
1723
1724 2005-05-19  Anton Blanchard  <anton@samba.org>
1725
1726         * ppc.h (PPC_OPCODE_POWER5): Define.
1727
1728 2005-05-10  Nick Clifton  <nickc@redhat.com>
1729
1730         * Update the address and phone number of the FSF organization in
1731         the GPL notices in the following files:
1732         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1733         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1734         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1735         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1736         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1737         tic54x.h, tic80.h, v850.h, vax.h
1738
1739 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1740
1741         * i386.h (i386_optab): Add ht and hnt.
1742
1743 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1744
1745         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1746         Add xcrypt-ctr.  Provide aliases without hyphens.
1747
1748 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1749
1750         Moved from ../ChangeLog
1751
1752         2005-04-12  Paul Brook  <paul@codesourcery.com>
1753         * m88k.h: Rename psr macros to avoid conflicts.
1754
1755         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1756         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1757         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1758         and ARM_ARCH_V6ZKT2.
1759
1760         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1761         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1762         Remove redundant instruction types.
1763         (struct argument): X_op - new field.
1764         (struct cst4_entry): Remove.
1765         (no_op_insn): Declare.
1766
1767         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1768         * crx.h (enum argtype): Rename types, remove unused types.
1769
1770         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1771         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1772         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1773         (enum operand_type): Rearrange operands, edit comments.
1774         replace us<N> with ui<N> for unsigned immediate.
1775         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1776         displacements (respectively).
1777         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1778         (instruction type): Add NO_TYPE_INS.
1779         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1780         (operand_entry): New field - 'flags'.
1781         (operand flags): New.
1782
1783         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1784         * crx.h (operand_type): Remove redundant types i3, i4,
1785         i5, i8, i12.
1786         Add new unsigned immediate types us3, us4, us5, us16.
1787
1788 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1789
1790         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1791         adjust them accordingly.
1792
1793 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1794
1795         * i386.h (i386_optab): Add rdtscp.
1796
1797 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1798
1799         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1800         between memory and segment register. Allow movq for moving between
1801         general-purpose register and segment register.
1802
1803 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1804
1805         PR gas/707
1806         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1807         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1808         fnstsw.
1809
1810 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1811
1812         * m68k.h (m68008, m68ec030, m68882): Remove.
1813         (m68k_mask): New.
1814         (cpu_m68k, cpu_cf): New.
1815         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1816         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1817
1818 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1819
1820         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1821         * cgen.h (enum cgen_parse_operand_type): Add
1822         CGEN_PARSE_OPERAND_SYMBOLIC.
1823
1824 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1825
1826         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1827         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1828         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1829
1830 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1831
1832         * mips.h (struct mips_opcode): Add new pinfo2 member.
1833         (INSN_ALIAS): New define for opcode table entries that are
1834         specific instances of another entry, such as 'move' for an 'or'
1835         with a zero operand.
1836         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1837         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1838
1839 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1840
1841         * mips.h (CPU_RM9000): Define.
1842         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1843
1844 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1845
1846         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1847         to/from test registers are illegal in 64-bit mode. Add missing
1848         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1849         (previously one had to explicitly encode a rex64 prefix). Re-enable
1850         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1851         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1852
1853 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1854
1855         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1856         available only with SSE2. Change the MMX additions introduced by SSE
1857         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1858         instructions by their now designated identifier (since combining i686
1859         and 3DNow! does not really imply 3DNow!A).
1860
1861 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1862
1863         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1864         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1865
1866 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1867             Vineet Sharma      <vineets@noida.hcltech.com>
1868
1869         * maxq.h: New file: Disassembly information for the maxq port.
1870
1871 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1872
1873         * i386.h (i386_optab): Put back "movzb".
1874
1875 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1876
1877         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1878         comments.  Remove member cris_ver_sim.  Add members
1879         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1880         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1881         (struct cris_support_reg, struct cris_cond15): New types.
1882         (cris_conds15): Declare.
1883         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1884         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1885         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1886         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1887         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1888         SIZE_FIELD_UNSIGNED.
1889
1890 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1891
1892         * i386.h (sldx_Suf): Remove.
1893         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1894         (q_FP): Define, implying no REX64.
1895         (x_FP, sl_FP): Imply FloatMF.
1896         (i386_optab): Split reg and mem forms of moving from segment registers
1897         so that the memory forms can ignore the 16-/32-bit operand size
1898         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1899         all non-floating-point instructions. Unite 32- and 64-bit forms of
1900         movsx, movzx, and movd. Adjust floating point operations for the above
1901         changes to the *FP macros. Add DefaultSize to floating point control
1902         insns operating on larger memory ranges. Remove left over comments
1903         hinting at certain insns being Intel-syntax ones where the ones
1904         actually meant are already gone.
1905
1906 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1907
1908         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1909         instruction type.
1910
1911 2004-09-30  Paul Brook  <paul@codesourcery.com>
1912
1913         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1914         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1915
1916 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1917
1918         * avr.h: Add support for
1919         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1920
1921 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1922
1923         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1924
1925 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1926
1927         * msp430.h (msp430_opc): Add new instructions.
1928         (msp430_rcodes): Declare new instructions.
1929         (msp430_hcodes): Likewise..
1930
1931 2004-08-13  Nick Clifton  <nickc@redhat.com>
1932
1933         PR/301
1934         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1935         processors.
1936
1937 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1938
1939         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1940
1941 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1942
1943         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1944
1945 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1946
1947         * i386.h: Adjust instruction descriptions to better match the
1948         specification.
1949
1950 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1951
1952         * arm.h: Remove all old content.  Replace with architecture defines
1953         from gas/config/tc-arm.c.
1954
1955 2004-07-09  Andreas Schwab  <schwab@suse.de>
1956
1957         * m68k.h: Fix comment.
1958
1959 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1960
1961         * crx.h: New file.
1962
1963 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1964
1965         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1966
1967 2004-05-24  Peter Barada  <peter@the-baradas.com>
1968
1969         * m68k.h: Add 'size' to m68k_opcode.
1970
1971 2004-05-05  Peter Barada  <peter@the-baradas.com>
1972
1973         * m68k.h: Switch from ColdFire chip name to core variant.
1974
1975 2004-04-22  Peter Barada  <peter@the-baradas.com>
1976
1977         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1978         descriptions for new EMAC cases.
1979         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1980         handle Motorola MAC syntax.
1981         Allow disassembly of ColdFire V4e object files.
1982
1983 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1984
1985         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1986
1987 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1988
1989         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1990
1991 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1992
1993         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1994
1995 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1996
1997         * i386.h (i386_optab): Added xstore/xcrypt insns.
1998
1999 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2000
2001         * h8300.h (32bit ldc/stc): Add relaxing support.
2002
2003 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
2004
2005         * h8300.h (BITOP): Pass MEMRELAX flag.
2006
2007 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2008
2009         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2010         except for the H8S.
2011
2012 For older changes see ChangeLog-9103
2013 \f
2014 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2015
2016 Copying and distribution of this file, with or without modification,
2017 are permitted in any medium without royalty provided the copyright
2018 notice and this notice are preserved.
2019
2020 Local Variables:
2021 mode: change-log
2022 left-margin: 8
2023 fill-column: 74
2024 version-control: never
2025 End: