1 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
3 * mips.h: Update copyright.
4 (INSN_CHIP_MASK): New macro.
5 (INSN_OCTEON): New macro.
6 (CPU_OCTEON): New macro.
7 (OPCODE_IS_MEMBER): Handle Octeon instructions.
9 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
11 * mips.h (INSN_LOONGSON_2E): New.
12 (INSN_LOONGSON_2F): New.
13 (CPU_LOONGSON_2E): New.
14 (CPU_LOONGSON_2F): New.
15 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
17 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
19 * mips.h (INSN_ISA*): Redefine certain values as an
20 enumeration. Update comments.
21 (mips_isa_table): New.
22 (ISA_MIPS*): Redefine to match enumeration.
23 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
26 2007-08-08 Ben Elliston <bje@au.ibm.com>
28 * ppc.h (PPC_OPCODE_PPCPS): New.
30 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
32 * m68k.h: Document j K & E.
34 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
36 * cr16.h: New file for CR16 target.
38 2007-05-02 Alan Modra <amodra@bigpond.net.au>
40 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
42 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
44 * m68k.h (mcfisa_c): New.
45 (mcfusp, mcf_mask): Adjust.
47 2007-04-20 Alan Modra <amodra@bigpond.net.au>
49 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
50 (num_powerpc_operands): Declare.
51 (PPC_OPERAND_SIGNED et al): Redefine as hex.
52 (PPC_OPERAND_PLUS1): Define.
54 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
56 * i386.h (REX_MODE64): Renamed to ...
58 (REX_EXTX): Renamed to ...
60 (REX_EXTY): Renamed to ...
62 (REX_EXTZ): Renamed to ...
65 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
67 * i386.h: Add entries from config/tc-i386.h and move tables
68 to opcodes/i386-opc.h.
70 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
72 * i386.h (FloatDR): Removed.
73 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
75 2007-03-01 Alan Modra <amodra@bigpond.net.au>
77 * spu-insns.h: Add soma double-float insns.
79 2007-02-20 Thiemo Seufer <ths@mips.com>
80 Chao-Ying Fu <fu@mips.com>
82 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
83 (INSN_DSPR2): Add flag for DSP R2 instructions.
84 (M_BALIGN): New macro.
86 2007-02-14 Alan Modra <amodra@bigpond.net.au>
88 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
89 and Seg3ShortFrom with Shortform.
91 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
94 * i386.h (i386_optab): Put the real "test" before the pseudo
97 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
99 * m68k.h (m68010up): OR fido_a.
101 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
103 * m68k.h (fido_a): New.
105 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
107 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
108 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
111 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
113 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
115 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
117 * score-inst.h (enum score_insn_type): Add Insn_internal.
119 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
120 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
121 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
122 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
123 Alan Modra <amodra@bigpond.net.au>
125 * spu-insns.h: New file.
128 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
130 * ppc.h (PPC_OPCODE_CELL): Define.
132 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
134 * i386.h : Modify opcode to support for the change in POPCNT opcode
135 in amdfam10 architecture.
137 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
139 * i386.h: Replace CpuMNI with CpuSSSE3.
141 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
142 Joseph Myers <joseph@codesourcery.com>
143 Ian Lance Taylor <ian@wasabisystems.com>
144 Ben Elliston <bje@wasabisystems.com>
146 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
148 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
150 * score-datadep.h: New file.
151 * score-inst.h: New file.
153 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
155 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
156 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
159 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
160 Michael Meissner <michael.meissner@amd.com>
162 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
164 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
166 * i386.h (i386_optab): Add "nop" with memory reference.
168 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
170 * i386.h (i386_optab): Update comment for 64bit NOP.
172 2006-06-06 Ben Elliston <bje@au.ibm.com>
173 Anton Blanchard <anton@samba.org>
175 * ppc.h (PPC_OPCODE_POWER6): Define.
178 2006-06-05 Thiemo Seufer <ths@mips.com>
180 * mips.h: Improve description of MT flags.
182 2006-05-25 Richard Sandiford <richard@codesourcery.com>
184 * m68k.h (mcf_mask): Define.
186 2006-05-05 Thiemo Seufer <ths@mips.com>
187 David Ung <davidu@mips.com>
189 * mips.h (enum): Add macro M_CACHE_AB.
191 2006-05-04 Thiemo Seufer <ths@mips.com>
192 Nigel Stephens <nigel@mips.com>
193 David Ung <davidu@mips.com>
195 * mips.h: Add INSN_SMARTMIPS define.
197 2006-04-30 Thiemo Seufer <ths@mips.com>
198 David Ung <davidu@mips.com>
200 * mips.h: Defines udi bits and masks. Add description of
201 characters which may appear in the args field of udi
204 2006-04-26 Thiemo Seufer <ths@networkno.de>
206 * mips.h: Improve comments describing the bitfield instruction
209 2006-04-26 Julian Brown <julian@codesourcery.com>
211 * arm.h (FPU_VFP_EXT_V3): Define constant.
212 (FPU_NEON_EXT_V1): Likewise.
213 (FPU_VFP_HARD): Update.
214 (FPU_VFP_V3): Define macro.
215 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
217 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
219 * avr.h (AVR_ISA_PWMx): New.
221 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
223 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
224 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
225 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
226 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
227 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
229 2006-03-10 Paul Brook <paul@codesourcery.com>
231 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
233 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
235 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
236 first. Correct mask of bb "B" opcode.
238 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
240 * i386.h (i386_optab): Support Intel Merom New Instructions.
242 2006-02-24 Paul Brook <paul@codesourcery.com>
244 * arm.h: Add V7 feature bits.
246 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
248 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
250 2006-01-31 Paul Brook <paul@codesourcery.com>
251 Richard Earnshaw <rearnsha@arm.com>
253 * arm.h: Use ARM_CPU_FEATURE.
254 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
255 (arm_feature_set): Change to a structure.
256 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
257 ARM_FEATURE): New macros.
259 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
261 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
262 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
263 (ADD_PC_INCR_OPCODE): Don't define.
265 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
268 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
270 2005-11-14 David Ung <davidu@mips.com>
272 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
273 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
274 save/restore encoding of the args field.
276 2005-10-28 Dave Brolley <brolley@redhat.com>
278 Contribute the following changes:
279 2005-02-16 Dave Brolley <brolley@redhat.com>
281 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
282 cgen_isa_mask_* to cgen_bitset_*.
285 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
287 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
288 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
289 (CGEN_CPU_TABLE): Make isas a ponter.
291 2003-09-29 Dave Brolley <brolley@redhat.com>
293 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
294 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
295 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
297 2002-12-13 Dave Brolley <brolley@redhat.com>
299 * cgen.h (symcat.h): #include it.
300 (cgen-bitset.h): #include it.
301 (CGEN_ATTR_VALUE_TYPE): Now a union.
302 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
303 (CGEN_ATTR_ENTRY): 'value' now unsigned.
304 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
305 * cgen-bitset.h: New file.
307 2005-09-30 Catherine Moore <clm@cm00re.com>
311 2005-10-24 Jan Beulich <jbeulich@novell.com>
313 * ia64.h (enum ia64_opnd): Move memory operand out of set of
316 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
318 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
319 Add FLAG_STRICT to pa10 ftest opcode.
321 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
323 * hppa.h (pa_opcodes): Remove lha entries.
325 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
327 * hppa.h (FLAG_STRICT): Revise comment.
328 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
329 before corresponding pa11 opcodes. Add strict pa10 register-immediate
332 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
334 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
336 2005-09-06 Chao-ying Fu <fu@mips.com>
338 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
339 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
341 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
342 (INSN_ASE_MASK): Update to include INSN_MT.
343 (INSN_MT): New define for MT ASE.
345 2005-08-25 Chao-ying Fu <fu@mips.com>
347 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
348 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
349 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
350 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
351 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
352 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
354 (INSN_DSP): New define for DSP ASE.
356 2005-08-18 Alan Modra <amodra@bigpond.net.au>
360 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
362 * ppc.h (PPC_OPCODE_E300): Define.
364 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
366 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
368 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
371 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
374 2005-07-27 Jan Beulich <jbeulich@novell.com>
376 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
377 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
378 Add movq-s as 64-bit variants of movd-s.
380 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
382 * hppa.h: Fix punctuation in comment.
384 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
385 implicit space-register addressing. Set space-register bits on opcodes
386 using implicit space-register addressing. Add various missing pa20
387 long-immediate opcodes. Remove various opcodes using implicit 3-bit
388 space-register addressing. Use "fE" instead of "fe" in various
391 2005-07-18 Jan Beulich <jbeulich@novell.com>
393 * i386.h (i386_optab): Operands of aam and aad are unsigned.
395 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
397 * i386.h (i386_optab): Support Intel VMX Instructions.
399 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
401 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
403 2005-07-05 Jan Beulich <jbeulich@novell.com>
405 * i386.h (i386_optab): Add new insns.
407 2005-07-01 Nick Clifton <nickc@redhat.com>
409 * sparc.h: Add typedefs to structure declarations.
411 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
414 * i386.h (i386_optab): Update comments for 64bit addressing on
415 mov. Allow 64bit addressing for mov and movq.
417 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
419 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
420 respectively, in various floating-point load and store patterns.
422 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
424 * hppa.h (FLAG_STRICT): Correct comment.
425 (pa_opcodes): Update load and store entries to allow both PA 1.X and
426 PA 2.0 mneumonics when equivalent. Entries with cache control
427 completers now require PA 1.1. Adjust whitespace.
429 2005-05-19 Anton Blanchard <anton@samba.org>
431 * ppc.h (PPC_OPCODE_POWER5): Define.
433 2005-05-10 Nick Clifton <nickc@redhat.com>
435 * Update the address and phone number of the FSF organization in
436 the GPL notices in the following files:
437 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
438 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
439 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
440 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
441 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
442 tic54x.h, tic80.h, v850.h, vax.h
444 2005-05-09 Jan Beulich <jbeulich@novell.com>
446 * i386.h (i386_optab): Add ht and hnt.
448 2005-04-18 Mark Kettenis <kettenis@gnu.org>
450 * i386.h: Insert hyphens into selected VIA PadLock extensions.
451 Add xcrypt-ctr. Provide aliases without hyphens.
453 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
455 Moved from ../ChangeLog
457 2005-04-12 Paul Brook <paul@codesourcery.com>
458 * m88k.h: Rename psr macros to avoid conflicts.
460 2005-03-12 Zack Weinberg <zack@codesourcery.com>
461 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
462 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
465 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
466 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
467 Remove redundant instruction types.
468 (struct argument): X_op - new field.
469 (struct cst4_entry): Remove.
470 (no_op_insn): Declare.
472 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
473 * crx.h (enum argtype): Rename types, remove unused types.
475 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
476 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
477 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
478 (enum operand_type): Rearrange operands, edit comments.
479 replace us<N> with ui<N> for unsigned immediate.
480 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
481 displacements (respectively).
482 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
483 (instruction type): Add NO_TYPE_INS.
484 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
485 (operand_entry): New field - 'flags'.
486 (operand flags): New.
488 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
489 * crx.h (operand_type): Remove redundant types i3, i4,
491 Add new unsigned immediate types us3, us4, us5, us16.
493 2005-04-12 Mark Kettenis <kettenis@gnu.org>
495 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
496 adjust them accordingly.
498 2005-04-01 Jan Beulich <jbeulich@novell.com>
500 * i386.h (i386_optab): Add rdtscp.
502 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
504 * i386.h (i386_optab): Don't allow the `l' suffix for moving
505 between memory and segment register. Allow movq for moving between
506 general-purpose register and segment register.
508 2005-02-09 Jan Beulich <jbeulich@novell.com>
511 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
512 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
515 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
517 * m68k.h (m68008, m68ec030, m68882): Remove.
519 (cpu_m68k, cpu_cf): New.
520 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
521 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
523 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
525 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
526 * cgen.h (enum cgen_parse_operand_type): Add
527 CGEN_PARSE_OPERAND_SYMBOLIC.
529 2005-01-21 Fred Fish <fnf@specifixinc.com>
531 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
532 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
533 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
535 2005-01-19 Fred Fish <fnf@specifixinc.com>
537 * mips.h (struct mips_opcode): Add new pinfo2 member.
538 (INSN_ALIAS): New define for opcode table entries that are
539 specific instances of another entry, such as 'move' for an 'or'
541 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
542 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
544 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
546 * mips.h (CPU_RM9000): Define.
547 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
549 2004-11-25 Jan Beulich <jbeulich@novell.com>
551 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
552 to/from test registers are illegal in 64-bit mode. Add missing
553 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
554 (previously one had to explicitly encode a rex64 prefix). Re-enable
555 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
556 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
558 2004-11-23 Jan Beulich <jbeulich@novell.com>
560 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
561 available only with SSE2. Change the MMX additions introduced by SSE
562 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
563 instructions by their now designated identifier (since combining i686
564 and 3DNow! does not really imply 3DNow!A).
566 2004-11-19 Alan Modra <amodra@bigpond.net.au>
568 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
569 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
571 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
572 Vineet Sharma <vineets@noida.hcltech.com>
574 * maxq.h: New file: Disassembly information for the maxq port.
576 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
578 * i386.h (i386_optab): Put back "movzb".
580 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
582 * cris.h (enum cris_insn_version_usage): Tweak formatting and
583 comments. Remove member cris_ver_sim. Add members
584 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
585 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
586 (struct cris_support_reg, struct cris_cond15): New types.
587 (cris_conds15): Declare.
588 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
589 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
590 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
591 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
592 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
595 2004-11-04 Jan Beulich <jbeulich@novell.com>
597 * i386.h (sldx_Suf): Remove.
598 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
599 (q_FP): Define, implying no REX64.
600 (x_FP, sl_FP): Imply FloatMF.
601 (i386_optab): Split reg and mem forms of moving from segment registers
602 so that the memory forms can ignore the 16-/32-bit operand size
603 distinction. Adjust a few others for Intel mode. Remove *FP uses from
604 all non-floating-point instructions. Unite 32- and 64-bit forms of
605 movsx, movzx, and movd. Adjust floating point operations for the above
606 changes to the *FP macros. Add DefaultSize to floating point control
607 insns operating on larger memory ranges. Remove left over comments
608 hinting at certain insns being Intel-syntax ones where the ones
609 actually meant are already gone.
611 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
613 * crx.h: Add COPS_REG_INS - Coprocessor Special register
616 2004-09-30 Paul Brook <paul@codesourcery.com>
618 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
619 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
621 2004-09-11 Theodore A. Roth <troth@openavr.org>
623 * avr.h: Add support for
624 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
626 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
628 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
630 2004-08-24 Dmitry Diky <diwil@spec.ru>
632 * msp430.h (msp430_opc): Add new instructions.
633 (msp430_rcodes): Declare new instructions.
634 (msp430_hcodes): Likewise..
636 2004-08-13 Nick Clifton <nickc@redhat.com>
639 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
642 2004-08-30 Michal Ludvig <mludvig@suse.cz>
644 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
646 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
648 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
650 2004-07-21 Jan Beulich <jbeulich@novell.com>
652 * i386.h: Adjust instruction descriptions to better match the
655 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
657 * arm.h: Remove all old content. Replace with architecture defines
658 from gas/config/tc-arm.c.
660 2004-07-09 Andreas Schwab <schwab@suse.de>
662 * m68k.h: Fix comment.
664 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
668 2004-06-24 Alan Modra <amodra@bigpond.net.au>
670 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
672 2004-05-24 Peter Barada <peter@the-baradas.com>
674 * m68k.h: Add 'size' to m68k_opcode.
676 2004-05-05 Peter Barada <peter@the-baradas.com>
678 * m68k.h: Switch from ColdFire chip name to core variant.
680 2004-04-22 Peter Barada <peter@the-baradas.com>
682 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
683 descriptions for new EMAC cases.
684 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
685 handle Motorola MAC syntax.
686 Allow disassembly of ColdFire V4e object files.
688 2004-03-16 Alan Modra <amodra@bigpond.net.au>
690 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
692 2004-03-12 Jakub Jelinek <jakub@redhat.com>
694 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
696 2004-03-12 Michal Ludvig <mludvig@suse.cz>
698 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
700 2004-03-12 Michal Ludvig <mludvig@suse.cz>
702 * i386.h (i386_optab): Added xstore/xcrypt insns.
704 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
706 * h8300.h (32bit ldc/stc): Add relaxing support.
708 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
710 * h8300.h (BITOP): Pass MEMRELAX flag.
712 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
714 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
717 For older changes see ChangeLog-9103
723 version-control: never