include/opcode/ChangeLog

   1 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Support Intel Merom New Instructions.
   4
   5 2006-02-24  Paul Brook  <paul@codesourcery.com>
   6
   7         * arm.h: Add V7 feature bits.
   8
   9 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  12
  13 2006-01-31  Paul Brook  <paul@codesourcery.com>
  14         Richard Earnshaw <rearnsha@arm.com>
  15
  16         * arm.h: Use ARM_CPU_FEATURE.
  17         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  18         (arm_feature_set): Change to a structure.
  19         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  20         ARM_FEATURE): New macros.
  21
  22 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  23
  24         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  25         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  26         (ADD_PC_INCR_OPCODE): Don't define.
  27
  28 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         PR gas/1874
  31         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  32
  33 2005-11-14  David Ung  <davidu@mips.com>
  34
  35         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  36         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  37         save/restore encoding of the args field.
  38
  39 2005-10-28  Dave Brolley  <brolley@redhat.com>
  40
  41         Contribute the following changes:
  42         2005-02-16  Dave Brolley  <brolley@redhat.com>
  43
  44         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  45         cgen_isa_mask_* to cgen_bitset_*.
  46         * cgen.h: Likewise.
  47
  48         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  49
  50         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  51         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  52         (CGEN_CPU_TABLE): Make isas a ponter.
  53
  54         2003-09-29  Dave Brolley  <brolley@redhat.com>
  55
  56         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  57         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  58         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  59
  60         2002-12-13  Dave Brolley  <brolley@redhat.com>
  61
  62         * cgen.h (symcat.h): #include it.
  63         (cgen-bitset.h): #include it.
  64         (CGEN_ATTR_VALUE_TYPE): Now a union.
  65         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  66         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  67         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  68         * cgen-bitset.h: New file.
  69
  70 2005-09-30  Catherine Moore  <clm@cm00re.com>
  71
  72         * bfin.h: New file.
  73
  74 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  75
  76         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  77         indirect operands.
  78
  79 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  80
  81         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  82         Add FLAG_STRICT to pa10 ftest opcode.
  83
  84 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  85
  86         * hppa.h (pa_opcodes): Remove lha entries.
  87
  88 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  89
  90         * hppa.h (FLAG_STRICT): Revise comment.
  91         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  92         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  93         entries for "fdc".
  94
  95 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  96
  97         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  98
  99 2005-09-06  Chao-ying Fu  <fu@mips.com>
 100
 101         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 102         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 103         define.
 104         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 105         (INSN_ASE_MASK): Update to include INSN_MT.
 106         (INSN_MT): New define for MT ASE.
 107
 108 2005-08-25  Chao-ying Fu  <fu@mips.com>
 109
 110         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 111         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 112         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 113         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 114         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 115         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 116         instructions.
 117         (INSN_DSP): New define for DSP ASE.
 118
 119 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 120
 121         * a29k.h: Delete.
 122
 123 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 124
 125         * ppc.h (PPC_OPCODE_E300): Define.
 126
 127 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 128
 129         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 130
 131 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 132
 133         PR gas/336
 134         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 135         and pitlb.
 136
 137 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 138
 139         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 140         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 141         Add movq-s as 64-bit variants of movd-s.
 142
 143 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 144
 145         * hppa.h: Fix punctuation in comment.
 146
 147         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 148         implicit space-register addressing.  Set space-register bits on opcodes
 149         using implicit space-register addressing.  Add various missing pa20
 150         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 151         space-register addressing.  Use "fE" instead of "fe" in various
 152         fstw opcodes.
 153
 154 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 155
 156         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 157
 158 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 159
 160         * i386.h (i386_optab): Support Intel VMX Instructions.
 161
 162 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 163
 164         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 165
 166 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 167
 168         * i386.h (i386_optab): Add new insns.
 169
 170 2005-07-01  Nick Clifton  <nickc@redhat.com>
 171
 172         * sparc.h: Add typedefs to structure declarations.
 173
 174 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         PR 1013
 177         * i386.h (i386_optab): Update comments for 64bit addressing on
 178         mov. Allow 64bit addressing for mov and movq.
 179
 180 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 181
 182         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 183         respectively, in various floating-point load and store patterns.
 184
 185 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 186
 187         * hppa.h (FLAG_STRICT): Correct comment.
 188         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 189         PA 2.0 mneumonics when equivalent.  Entries with cache control
 190         completers now require PA 1.1.  Adjust whitespace.
 191
 192 2005-05-19  Anton Blanchard  <anton@samba.org>
 193
 194         * ppc.h (PPC_OPCODE_POWER5): Define.
 195
 196 2005-05-10  Nick Clifton  <nickc@redhat.com>
 197
 198         * Update the address and phone number of the FSF organization in
 199         the GPL notices in the following files:
 200         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 201         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 202         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 203         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 204         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 205         tic54x.h, tic80.h, v850.h, vax.h
 206
 207 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 208
 209         * i386.h (i386_optab): Add ht and hnt.
 210
 211 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 212
 213         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 214         Add xcrypt-ctr.  Provide aliases without hyphens.
 215
 216 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         Moved from ../ChangeLog
 219
 220         2005-04-12  Paul Brook  <paul@codesourcery.com>
 221         * m88k.h: Rename psr macros to avoid conflicts.
 222
 223         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 224         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 225         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 226         and ARM_ARCH_V6ZKT2.
 227
 228         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 229         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 230         Remove redundant instruction types.
 231         (struct argument): X_op - new field.
 232         (struct cst4_entry): Remove.
 233         (no_op_insn): Declare.
 234
 235         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 236         * crx.h (enum argtype): Rename types, remove unused types.
 237
 238         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 239         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 240         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 241         (enum operand_type): Rearrange operands, edit comments.
 242         replace us<N> with ui<N> for unsigned immediate.
 243         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 244         displacements (respectively).
 245         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 246         (instruction type): Add NO_TYPE_INS.
 247         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 248         (operand_entry): New field - 'flags'.
 249         (operand flags): New.
 250
 251         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 252         * crx.h (operand_type): Remove redundant types i3, i4,
 253         i5, i8, i12.
 254         Add new unsigned immediate types us3, us4, us5, us16.
 255
 256 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 257
 258         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 259         adjust them accordingly.
 260
 261 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 262
 263         * i386.h (i386_optab): Add rdtscp.
 264
 265 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 266
 267         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 268         between memory and segment register. Allow movq for moving between
 269         general-purpose register and segment register.
 270
 271 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 272
 273         PR gas/707
 274         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 275         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 276         fnstsw.
 277
 278 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 279
 280         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 281         * cgen.h (enum cgen_parse_operand_type): Add
 282         CGEN_PARSE_OPERAND_SYMBOLIC.
 283
 284 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 285
 286         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 287         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 288         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 289
 290 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 291
 292         * mips.h (struct mips_opcode): Add new pinfo2 member.
 293         (INSN_ALIAS): New define for opcode table entries that are
 294         specific instances of another entry, such as 'move' for an 'or'
 295         with a zero operand.
 296         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 297         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 298
 299 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 300
 301         * mips.h (CPU_RM9000): Define.
 302         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 303
 304 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 305
 306         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 307         to/from test registers are illegal in 64-bit mode. Add missing
 308         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 309         (previously one had to explicitly encode a rex64 prefix). Re-enable
 310         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 311         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 312
 313 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 314
 315         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 316         available only with SSE2. Change the MMX additions introduced by SSE
 317         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 318         instructions by their now designated identifier (since combining i686
 319         and 3DNow! does not really imply 3DNow!A).
 320
 321 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 322
 323         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 324         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 325
 326 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 327             Vineet Sharma      <vineets@noida.hcltech.com>
 328
 329         * maxq.h: New file: Disassembly information for the maxq port.
 330
 331 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         * i386.h (i386_optab): Put back "movzb".
 334
 335 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 336
 337         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 338         comments.  Remove member cris_ver_sim.  Add members
 339         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 340         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 341         (struct cris_support_reg, struct cris_cond15): New types.
 342         (cris_conds15): Declare.
 343         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 344         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 345         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 346         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 347         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 348         SIZE_FIELD_UNSIGNED.
 349
 350 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 351
 352         * i386.h (sldx_Suf): Remove.
 353         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 354         (q_FP): Define, implying no REX64.
 355         (x_FP, sl_FP): Imply FloatMF.
 356         (i386_optab): Split reg and mem forms of moving from segment registers
 357         so that the memory forms can ignore the 16-/32-bit operand size
 358         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 359         all non-floating-point instructions. Unite 32- and 64-bit forms of
 360         movsx, movzx, and movd. Adjust floating point operations for the above
 361         changes to the *FP macros. Add DefaultSize to floating point control
 362         insns operating on larger memory ranges. Remove left over comments
 363         hinting at certain insns being Intel-syntax ones where the ones
 364         actually meant are already gone.
 365
 366 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 367
 368         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 369         instruction type.
 370
 371 2004-09-30  Paul Brook  <paul@codesourcery.com>
 372
 373         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 374         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 375
 376 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 377
 378         * avr.h: Add support for
 379         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 380
 381 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 382
 383         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 384
 385 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 386
 387         * msp430.h (msp430_opc): Add new instructions.
 388         (msp430_rcodes): Declare new instructions.
 389         (msp430_hcodes): Likewise..
 390
 391 2004-08-13  Nick Clifton  <nickc@redhat.com>
 392
 393         PR/301
 394         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 395         processors.
 396
 397 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 398
 399         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 400
 401 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 404
 405 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 406
 407         * i386.h: Adjust instruction descriptions to better match the
 408         specification.
 409
 410 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 411
 412         * arm.h: Remove all old content.  Replace with architecture defines
 413         from gas/config/tc-arm.c.
 414
 415 2004-07-09  Andreas Schwab  <schwab@suse.de>
 416
 417         * m68k.h: Fix comment.
 418
 419 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 420
 421         * crx.h: New file.
 422
 423 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 424
 425         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 426
 427 2004-05-24  Peter Barada  <peter@the-baradas.com>
 428
 429         * m68k.h: Add 'size' to m68k_opcode.
 430
 431 2004-05-05  Peter Barada  <peter@the-baradas.com>
 432
 433         * m68k.h: Switch from ColdFire chip name to core variant.
 434
 435 2004-04-22  Peter Barada  <peter@the-baradas.com>
 436
 437         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 438         descriptions for new EMAC cases.
 439         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 440         handle Motorola MAC syntax.
 441         Allow disassembly of ColdFire V4e object files.
 442
 443 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 444
 445         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 446
 447 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 448
 449         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 450
 451 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 452
 453         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 454
 455 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 456
 457         * i386.h (i386_optab): Added xstore/xcrypt insns.
 458
 459 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 460
 461         * h8300.h (32bit ldc/stc): Add relaxing support.
 462
 463 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 464
 465         * h8300.h (BITOP): Pass MEMRELAX flag.
 466
 467 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 468
 469         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 470         except for the H8S.
 471
 472 For older changes see ChangeLog-9103
 473 \f
 474 Local Variables:
 475 mode: change-log
 476 left-margin: 8
 477 fill-column: 74
 478 version-control: never
 479 End: