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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
1 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
2
3 PR binutils/15068
4 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
5 Add 16-bit opcodes.
6 * tic6xc-opcode-table.h: Add 16-bit insns.
7 * tic6x.h: Add support for 16-bit insns.
8
9 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
10
11 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
12 and mov.b/w/l Rs,@(d:32,ERd).
13
14 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
15
16 PR gas/15082
17 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
18 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
19 tic6x_operand_xregpair operand coding type.
20 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
21 opcode field, usu ORXREGD1324 for the src2 operand and remove the
22 TIC6X_FLAG_NO_CROSS.
23
24 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
25
26 PR gas/15095
27 * tic6x.h (enum tic6x_coding_method): Add
28 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
29 separately the msb and lsb of a register pair. This is needed to
30 encode the opcodes in the same way as TI assembler does.
31 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
32 and rsqrdp opcodes to use the new field coding types.
33
34 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
35
36 * arm.h (CRC_EXT_ARMV8): New constant.
37 (ARCH_CRC_ARMV8): New macro.
38
39 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
40
41 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
42
43 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
44 Andrew Jenner <andrew@codesourcery.com>
45
46 Based on patches from Altera Corporation.
47
48 * nios2.h: New file.
49
50 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
51
52 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
53
54 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
55
56 PR gas/15069
57 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
58
59 2013-01-24 Nick Clifton <nickc@redhat.com>
60
61 * v850.h: Add e3v5 support.
62
63 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
64
65 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
66
67 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
68
69 * ppc.h (PPC_OPCODE_POWER8): New define.
70 (PPC_OPCODE_HTM): Likewise.
71
72 2013-01-10 Will Newton <will.newton@imgtec.com>
73
74 * metag.h: New file.
75
76 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
77
78 * cr16.h (make_instruction): Rename to cr16_make_instruction.
79 (match_opcode): Rename to cr16_match_opcode.
80
81 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
82
83 * mips.h: Add support for r5900 instructions including lq and sq.
84
85 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
86
87 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
88 (make_instruction,match_opcode): Added function prototypes.
89 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
90
91 2012-11-23 Alan Modra <amodra@gmail.com>
92
93 * ppc.h (ppc_parse_cpu): Update prototype.
94
95 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
96
97 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
98 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
99
100 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
101
102 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
103
104 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
105
106 * ia64.h (ia64_opnd): Add new operand types.
107
108 2012-08-21 David S. Miller <davem@davemloft.net>
109
110 * sparc.h (F3F4): New macro.
111
112 2012-08-13 Ian Bolton <ian.bolton@arm.com>
113 Laurent Desnogues <laurent.desnogues@arm.com>
114 Jim MacArthur <jim.macarthur@arm.com>
115 Marcus Shawcroft <marcus.shawcroft@arm.com>
116 Nigel Stephens <nigel.stephens@arm.com>
117 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
118 Richard Earnshaw <rearnsha@arm.com>
119 Sofiane Naci <sofiane.naci@arm.com>
120 Tejas Belagod <tejas.belagod@arm.com>
121 Yufeng Zhang <yufeng.zhang@arm.com>
122
123 * aarch64.h: New file.
124
125 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
126 Maciej W. Rozycki <macro@codesourcery.com>
127
128 * mips.h (mips_opcode): Add the exclusions field.
129 (OPCODE_IS_MEMBER): Remove macro.
130 (cpu_is_member): New inline function.
131 (opcode_is_member): Likewise.
132
133 2012-07-31 Chao-Ying Fu <fu@mips.com>
134 Catherine Moore <clm@codesourcery.com>
135 Maciej W. Rozycki <macro@codesourcery.com>
136
137 * mips.h: Document microMIPS DSP ASE usage.
138 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
139 microMIPS DSP ASE support.
140 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
141 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
142 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
143 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
144 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
145 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
146 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
147
148 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
149
150 * mips.h: Fix a typo in description.
151
152 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
153
154 * avr.h: (AVR_ISA_XCH): New define.
155 (AVR_ISA_XMEGA): Use it.
156 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
157
158 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
159
160 * m68hc11.h: Add XGate definitions.
161 (struct m68hc11_opcode): Add xg_mask field.
162
163 2012-05-14 Catherine Moore <clm@codesourcery.com>
164 Maciej W. Rozycki <macro@codesourcery.com>
165 Rhonda Wittels <rhonda@codesourcery.com>
166
167 * ppc.h (PPC_OPCODE_VLE): New definition.
168 (PPC_OP_SA): New macro.
169 (PPC_OP_SE_VLE): New macro.
170 (PPC_OP): Use a variable shift amount.
171 (powerpc_operand): Update comments.
172 (PPC_OPSHIFT_INV): New macro.
173 (PPC_OPERAND_CR): Replace with...
174 (PPC_OPERAND_CR_BIT): ...this and
175 (PPC_OPERAND_CR_REG): ...this.
176
177
178 2012-05-03 Sean Keys <skeys@ipdatasys.com>
179
180 * xgate.h: Header file for XGATE assembler.
181
182 2012-04-27 David S. Miller <davem@davemloft.net>
183
184 * sparc.h: Document new arg code' )' for crypto RS3
185 immediates.
186
187 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
188 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
189 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
190 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
191 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
192 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
193 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
194 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
195 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
196 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
197 HWCAP_CBCOND, HWCAP_CRC32): New defines.
198
199 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
200
201 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
202
203 2012-02-27 Alan Modra <amodra@gmail.com>
204
205 * crx.h (cst4_map): Update declaration.
206
207 2012-02-25 Walter Lee <walt@tilera.com>
208
209 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
210 TILEGX_OPC_LD_TLS.
211 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
212 TILEPRO_OPC_LW_TLS_SN.
213
214 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
215
216 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
217 (XRELEASE_PREFIX_OPCODE): Likewise.
218
219 2011-12-08 Andrew Pinski <apinski@cavium.com>
220 Adam Nemet <anemet@caviumnetworks.com>
221
222 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
223 (INSN_OCTEON2): New macro.
224 (CPU_OCTEON2): New macro.
225 (OPCODE_IS_MEMBER): Add Octeon2.
226
227 2011-11-29 Andrew Pinski <apinski@cavium.com>
228
229 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
230 (INSN_OCTEONP): New macro.
231 (CPU_OCTEONP): New macro.
232 (OPCODE_IS_MEMBER): Add Octeon+.
233 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
234
235 2011-11-01 DJ Delorie <dj@redhat.com>
236
237 * rl78.h: New file.
238
239 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
240
241 * mips.h: Fix a typo in description.
242
243 2011-09-21 David S. Miller <davem@davemloft.net>
244
245 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
246 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
247 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
248 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
249
250 2011-08-09 Chao-ying Fu <fu@mips.com>
251 Maciej W. Rozycki <macro@codesourcery.com>
252
253 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
254 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
255 (INSN_ASE_MASK): Add the MCU bit.
256 (INSN_MCU): New macro.
257 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
258 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
259
260 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
261
262 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
263 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
264 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
265 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
266 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
267 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
268 (INSN2_READ_GPR_MMN): Likewise.
269 (INSN2_READ_FPR_D): Change the bit used.
270 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
271 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
272 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
273 (INSN2_COND_BRANCH): Likewise.
274 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
275 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
276 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
277 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
278 (INSN2_MOD_GPR_MN): Likewise.
279
280 2011-08-05 David S. Miller <davem@davemloft.net>
281
282 * sparc.h: Document new format codes '4', '5', and '('.
283 (OPF_LOW4, RS3): New macros.
284
285 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
286
287 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
288 order of flags documented.
289
290 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
291
292 * mips.h: Clarify the description of microMIPS instruction
293 manipulation macros.
294 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
295
296 2011-07-24 Chao-ying Fu <fu@mips.com>
297 Maciej W. Rozycki <macro@codesourcery.com>
298
299 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
300 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
301 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
302 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
303 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
304 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
305 (OP_MASK_RS3, OP_SH_RS3): Likewise.
306 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
307 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
308 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
309 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
310 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
311 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
312 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
313 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
314 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
315 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
316 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
317 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
318 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
319 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
320 (INSN_WRITE_GPR_S): New macro.
321 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
322 (INSN2_READ_FPR_D): Likewise.
323 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
324 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
325 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
326 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
327 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
328 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
329 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
330 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
331 (CPU_MICROMIPS): New macro.
332 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
333 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
334 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
335 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
336 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
337 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
338 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
339 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
340 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
341 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
342 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
343 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
344 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
345 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
346 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
347 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
348 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
349 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
350 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
351 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
352 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
353 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
354 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
355 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
356 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
357 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
358 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
359 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
360 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
361 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
362 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
363 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
364 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
365 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
366 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
367 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
368 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
369 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
370 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
371 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
372 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
373 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
374 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
375 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
376 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
377 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
378 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
379 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
380 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
381 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
382 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
383 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
384 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
385 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
386 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
387 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
388 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
389 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
390 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
391 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
392 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
393 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
394 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
395 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
396 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
397 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
398 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
399 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
400 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
401 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
402 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
403 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
404 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
405 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
406 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
407 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
408 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
409 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
410 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
411 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
412 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
413 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
414 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
415 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
416 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
417 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
418 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
419 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
420 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
421 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
422 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
423 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
424 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
425 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
426 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
427 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
428 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
429 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
430 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
431 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
432 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
433 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
434 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
435 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
436 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
437 (micromips_opcodes): New declaration.
438 (bfd_micromips_num_opcodes): Likewise.
439
440 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
441
442 * mips.h (INSN_TRAP): Rename to...
443 (INSN_NO_DELAY_SLOT): ... this.
444 (INSN_SYNC): Remove macro.
445
446 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
447
448 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
449 a duplicate of AVR_ISA_SPM.
450
451 2011-07-01 Nick Clifton <nickc@redhat.com>
452
453 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
454
455 2011-06-18 Robin Getz <robin.getz@analog.com>
456
457 * bfin.h (is_macmod_signed): New func
458
459 2011-06-18 Mike Frysinger <vapier@gentoo.org>
460
461 * bfin.h (is_macmod_pmove): Add missing space before func args.
462 (is_macmod_hmove): Likewise.
463
464 2011-06-13 Walter Lee <walt@tilera.com>
465
466 * tilegx.h: New file.
467 * tilepro.h: New file.
468
469 2011-05-31 Paul Brook <paul@codesourcery.com>
470
471 * arm.h (ARM_ARCH_V7R_IDIV): Define.
472
473 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
474
475 * s390.h: Replace S390_OPERAND_REG_EVEN with
476 S390_OPERAND_REG_PAIR.
477
478 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
479
480 * s390.h: Add S390_OPCODE_REG_EVEN flag.
481
482 2011-04-18 Julian Brown <julian@codesourcery.com>
483
484 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
485
486 2011-04-11 Dan McDonald <dan@wellkeeper.com>
487
488 PR gas/12296
489 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
490
491 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
492
493 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
494 New instruction set flags.
495 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
496
497 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
498
499 * mips.h (M_PREF_AB): New enum value.
500
501 2011-02-12 Mike Frysinger <vapier@gentoo.org>
502
503 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
504 M_IU): Define.
505 (is_macmod_pmove, is_macmod_hmove): New functions.
506
507 2011-02-11 Mike Frysinger <vapier@gentoo.org>
508
509 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
510
511 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
512
513 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
514 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
515
516 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
517
518 PR gas/11395
519 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
520 "bb" entries.
521
522 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
523
524 PR gas/11395
525 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
526
527 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
528
529 * mips.h: Update commentary after last commit.
530
531 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
532
533 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
534 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
535 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
536
537 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
538
539 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
540
541 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
542
543 * mips.h: Fix previous commit.
544
545 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
546
547 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
548 (INSN_LOONGSON_3A): Clear bit 31.
549
550 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
551
552 PR gas/12198
553 * arm.h (ARM_AEXT_V6M_ONLY): New define.
554 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
555 (ARM_ARCH_V6M_ONLY): New define.
556
557 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
558
559 * mips.h (INSN_LOONGSON_3A): Defined.
560 (CPU_LOONGSON_3A): Defined.
561 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
562
563 2010-10-09 Matt Rice <ratmice@gmail.com>
564
565 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
566 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
567
568 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
569
570 * arm.h (ARM_EXT_VIRT): New define.
571 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
572 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
573 Extensions.
574
575 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
576
577 * arm.h (ARM_AEXT_ADIV): New define.
578 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
579
580 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
581
582 * arm.h (ARM_EXT_OS): New define.
583 (ARM_AEXT_V6SM): Likewise.
584 (ARM_ARCH_V6SM): Likewise.
585
586 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
587
588 * arm.h (ARM_EXT_MP): Add.
589 (ARM_ARCH_V7A_MP): Likewise.
590
591 2010-09-22 Mike Frysinger <vapier@gentoo.org>
592
593 * bfin.h: Declare pseudoChr structs/defines.
594
595 2010-09-21 Mike Frysinger <vapier@gentoo.org>
596
597 * bfin.h: Strip trailing whitespace.
598
599 2010-07-29 DJ Delorie <dj@redhat.com>
600
601 * rx.h (RX_Operand_Type): Add TwoReg.
602 (RX_Opcode_ID): Remove ediv and ediv2.
603
604 2010-07-27 DJ Delorie <dj@redhat.com>
605
606 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
607
608 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
609 Ina Pandit <ina.pandit@kpitcummins.com>
610
611 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
612 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
613 PROCESSOR_V850E2_ALL.
614 Remove PROCESSOR_V850EA support.
615 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
616 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
617 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
618 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
619 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
620 V850_OPERAND_PERCENT.
621 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
622 V850_NOT_R0.
623 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
624 and V850E_PUSH_POP
625
626 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
627
628 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
629 (MIPS16_INSN_BRANCH): Rename to...
630 (MIPS16_INSN_COND_BRANCH): ... this.
631
632 2010-07-03 Alan Modra <amodra@gmail.com>
633
634 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
635 Renumber other PPC_OPCODE defines.
636
637 2010-07-03 Alan Modra <amodra@gmail.com>
638
639 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
640
641 2010-06-29 Alan Modra <amodra@gmail.com>
642
643 * maxq.h: Delete file.
644
645 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
646
647 * ppc.h (PPC_OPCODE_E500): Define.
648
649 2010-05-26 Catherine Moore <clm@codesourcery.com>
650
651 * opcode/mips.h (INSN_MIPS16): Remove.
652
653 2010-04-21 Joseph Myers <joseph@codesourcery.com>
654
655 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
656
657 2010-04-15 Nick Clifton <nickc@redhat.com>
658
659 * alpha.h: Update copyright notice to use GPLv3.
660 * arc.h: Likewise.
661 * arm.h: Likewise.
662 * avr.h: Likewise.
663 * bfin.h: Likewise.
664 * cgen.h: Likewise.
665 * convex.h: Likewise.
666 * cr16.h: Likewise.
667 * cris.h: Likewise.
668 * crx.h: Likewise.
669 * d10v.h: Likewise.
670 * d30v.h: Likewise.
671 * dlx.h: Likewise.
672 * h8300.h: Likewise.
673 * hppa.h: Likewise.
674 * i370.h: Likewise.
675 * i386.h: Likewise.
676 * i860.h: Likewise.
677 * i960.h: Likewise.
678 * ia64.h: Likewise.
679 * m68hc11.h: Likewise.
680 * m68k.h: Likewise.
681 * m88k.h: Likewise.
682 * maxq.h: Likewise.
683 * mips.h: Likewise.
684 * mmix.h: Likewise.
685 * mn10200.h: Likewise.
686 * mn10300.h: Likewise.
687 * msp430.h: Likewise.
688 * np1.h: Likewise.
689 * ns32k.h: Likewise.
690 * or32.h: Likewise.
691 * pdp11.h: Likewise.
692 * pj.h: Likewise.
693 * pn.h: Likewise.
694 * ppc.h: Likewise.
695 * pyr.h: Likewise.
696 * rx.h: Likewise.
697 * s390.h: Likewise.
698 * score-datadep.h: Likewise.
699 * score-inst.h: Likewise.
700 * sparc.h: Likewise.
701 * spu-insns.h: Likewise.
702 * spu.h: Likewise.
703 * tic30.h: Likewise.
704 * tic4x.h: Likewise.
705 * tic54x.h: Likewise.
706 * tic80.h: Likewise.
707 * v850.h: Likewise.
708 * vax.h: Likewise.
709
710 2010-03-25 Joseph Myers <joseph@codesourcery.com>
711
712 * tic6x-control-registers.h, tic6x-insn-formats.h,
713 tic6x-opcode-table.h, tic6x.h: New.
714
715 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
716
717 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
718
719 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
720
721 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
722
723 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
724
725 * ia64.h (ia64_find_opcode): Remove argument name.
726 (ia64_find_next_opcode): Likewise.
727 (ia64_dis_opcode): Likewise.
728 (ia64_free_opcode): Likewise.
729 (ia64_find_dependency): Likewise.
730
731 2009-11-22 Doug Evans <dje@sebabeach.org>
732
733 * cgen.h: Include bfd_stdint.h.
734 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
735
736 2009-11-18 Paul Brook <paul@codesourcery.com>
737
738 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
739
740 2009-11-17 Paul Brook <paul@codesourcery.com>
741 Daniel Jacobowitz <dan@codesourcery.com>
742
743 * arm.h (ARM_EXT_V6_DSP): Define.
744 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
745 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
746
747 2009-11-04 DJ Delorie <dj@redhat.com>
748
749 * rx.h (rx_decode_opcode) (mvtipl): Add.
750 (mvtcp, mvfcp, opecp): Remove.
751
752 2009-11-02 Paul Brook <paul@codesourcery.com>
753
754 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
755 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
756 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
757 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
758 FPU_ARCH_NEON_VFP_V4): Define.
759
760 2009-10-23 Doug Evans <dje@sebabeach.org>
761
762 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
763 * cgen.h: Update. Improve multi-inclusion macro name.
764
765 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
766
767 * ppc.h (PPC_OPCODE_476): Define.
768
769 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
770
771 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
772
773 2009-09-29 DJ Delorie <dj@redhat.com>
774
775 * rx.h: New file.
776
777 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
778
779 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
780
781 2009-09-21 Ben Elliston <bje@au.ibm.com>
782
783 * ppc.h (PPC_OPCODE_PPCA2): New.
784
785 2009-09-05 Martin Thuresson <martin@mtme.org>
786
787 * ia64.h (struct ia64_operand): Renamed member class to op_class.
788
789 2009-08-29 Martin Thuresson <martin@mtme.org>
790
791 * tic30.h (template): Rename type template to
792 insn_template. Updated code to use new name.
793 * tic54x.h (template): Rename type template to
794 insn_template.
795
796 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
797
798 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
799
800 2009-06-11 Anthony Green <green@moxielogic.com>
801
802 * moxie.h (MOXIE_F3_PCREL): Define.
803 (moxie_form3_opc_info): Grow.
804
805 2009-06-06 Anthony Green <green@moxielogic.com>
806
807 * moxie.h (MOXIE_F1_M): Define.
808
809 2009-04-15 Anthony Green <green@moxielogic.com>
810
811 * moxie.h: Created.
812
813 2009-04-06 DJ Delorie <dj@redhat.com>
814
815 * h8300.h: Add relaxation attributes to MOVA opcodes.
816
817 2009-03-10 Alan Modra <amodra@bigpond.net.au>
818
819 * ppc.h (ppc_parse_cpu): Declare.
820
821 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
822
823 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
824 and _IMM11 for mbitclr and mbitset.
825 * score-datadep.h: Update dependency information.
826
827 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
828
829 * ppc.h (PPC_OPCODE_POWER7): New.
830
831 2009-02-06 Doug Evans <dje@google.com>
832
833 * i386.h: Add comment regarding sse* insns and prefixes.
834
835 2009-02-03 Sandip Matte <sandip@rmicorp.com>
836
837 * mips.h (INSN_XLR): Define.
838 (INSN_CHIP_MASK): Update.
839 (CPU_XLR): Define.
840 (OPCODE_IS_MEMBER): Update.
841 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
842
843 2009-01-28 Doug Evans <dje@google.com>
844
845 * opcode/i386.h: Add multiple inclusion protection.
846 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
847 (EDI_REG_NUM): New macros.
848 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
849 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
850 (REX_PREFIX_P): New macro.
851
852 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
853
854 * ppc.h (struct powerpc_opcode): New field "deprecated".
855 (PPC_OPCODE_NOPOWER4): Delete.
856
857 2008-11-28 Joshua Kinard <kumba@gentoo.org>
858
859 * mips.h: Define CPU_R14000, CPU_R16000.
860 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
861
862 2008-11-18 Catherine Moore <clm@codesourcery.com>
863
864 * arm.h (FPU_NEON_FP16): New.
865 (FPU_ARCH_NEON_FP16): New.
866
867 2008-11-06 Chao-ying Fu <fu@mips.com>
868
869 * mips.h: Doucument '1' for 5-bit sync type.
870
871 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
872
873 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
874 IA64_RS_CR.
875
876 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
877
878 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
879
880 2008-07-30 Michael J. Eager <eager@eagercon.com>
881
882 * ppc.h (PPC_OPCODE_405): Define.
883 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
884
885 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
886
887 * ppc.h (ppc_cpu_t): New typedef.
888 (struct powerpc_opcode <flags>): Use it.
889 (struct powerpc_operand <insert, extract>): Likewise.
890 (struct powerpc_macro <flags>): Likewise.
891
892 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
893
894 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
895 Update comment before MIPS16 field descriptors to mention MIPS16.
896 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
897 BBIT.
898 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
899 New bit masks and shift counts for cins and exts.
900
901 * mips.h: Document new field descriptors +Q.
902 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
903
904 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
905
906 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
907 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
908
909 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
910
911 * ppc.h: (PPC_OPCODE_E500MC): New.
912
913 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386.h (MAX_OPERANDS): Set to 5.
916 (MAX_MNEM_SIZE): Changed to 20.
917
918 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
919
920 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
921
922 2008-03-09 Paul Brook <paul@codesourcery.com>
923
924 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
925
926 2008-03-04 Paul Brook <paul@codesourcery.com>
927
928 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
929 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
930 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
931
932 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
933 Nick Clifton <nickc@redhat.com>
934
935 PR 3134
936 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
937 with a 32-bit displacement but without the top bit of the 4th byte
938 set.
939
940 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
941
942 * cr16.h (cr16_num_optab): Declared.
943
944 2008-02-14 Hakan Ardo <hakan@debian.org>
945
946 PR gas/2626
947 * avr.h (AVR_ISA_2xxe): Define.
948
949 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
950
951 * mips.h: Update copyright.
952 (INSN_CHIP_MASK): New macro.
953 (INSN_OCTEON): New macro.
954 (CPU_OCTEON): New macro.
955 (OPCODE_IS_MEMBER): Handle Octeon instructions.
956
957 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
958
959 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
960
961 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
962
963 * avr.h (AVR_ISA_USB162): Add new opcode set.
964 (AVR_ISA_AVR3): Likewise.
965
966 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
967
968 * mips.h (INSN_LOONGSON_2E): New.
969 (INSN_LOONGSON_2F): New.
970 (CPU_LOONGSON_2E): New.
971 (CPU_LOONGSON_2F): New.
972 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
973
974 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
975
976 * mips.h (INSN_ISA*): Redefine certain values as an
977 enumeration. Update comments.
978 (mips_isa_table): New.
979 (ISA_MIPS*): Redefine to match enumeration.
980 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
981 values.
982
983 2007-08-08 Ben Elliston <bje@au.ibm.com>
984
985 * ppc.h (PPC_OPCODE_PPCPS): New.
986
987 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
988
989 * m68k.h: Document j K & E.
990
991 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
992
993 * cr16.h: New file for CR16 target.
994
995 2007-05-02 Alan Modra <amodra@bigpond.net.au>
996
997 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
998
999 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1000
1001 * m68k.h (mcfisa_c): New.
1002 (mcfusp, mcf_mask): Adjust.
1003
1004 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1005
1006 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1007 (num_powerpc_operands): Declare.
1008 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1009 (PPC_OPERAND_PLUS1): Define.
1010
1011 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 * i386.h (REX_MODE64): Renamed to ...
1014 (REX_W): This.
1015 (REX_EXTX): Renamed to ...
1016 (REX_R): This.
1017 (REX_EXTY): Renamed to ...
1018 (REX_X): This.
1019 (REX_EXTZ): Renamed to ...
1020 (REX_B): This.
1021
1022 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1023
1024 * i386.h: Add entries from config/tc-i386.h and move tables
1025 to opcodes/i386-opc.h.
1026
1027 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1028
1029 * i386.h (FloatDR): Removed.
1030 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1031
1032 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1033
1034 * spu-insns.h: Add soma double-float insns.
1035
1036 2007-02-20 Thiemo Seufer <ths@mips.com>
1037 Chao-Ying Fu <fu@mips.com>
1038
1039 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1040 (INSN_DSPR2): Add flag for DSP R2 instructions.
1041 (M_BALIGN): New macro.
1042
1043 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1044
1045 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1046 and Seg3ShortFrom with Shortform.
1047
1048 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1049
1050 PR gas/4027
1051 * i386.h (i386_optab): Put the real "test" before the pseudo
1052 one.
1053
1054 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1055
1056 * m68k.h (m68010up): OR fido_a.
1057
1058 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1059
1060 * m68k.h (fido_a): New.
1061
1062 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1063
1064 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1065 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1066 values.
1067
1068 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1069
1070 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1071
1072 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1073
1074 * score-inst.h (enum score_insn_type): Add Insn_internal.
1075
1076 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1077 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1078 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1079 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1080 Alan Modra <amodra@bigpond.net.au>
1081
1082 * spu-insns.h: New file.
1083 * spu.h: New file.
1084
1085 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1086
1087 * ppc.h (PPC_OPCODE_CELL): Define.
1088
1089 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1090
1091 * i386.h : Modify opcode to support for the change in POPCNT opcode
1092 in amdfam10 architecture.
1093
1094 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1095
1096 * i386.h: Replace CpuMNI with CpuSSSE3.
1097
1098 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1099 Joseph Myers <joseph@codesourcery.com>
1100 Ian Lance Taylor <ian@wasabisystems.com>
1101 Ben Elliston <bje@wasabisystems.com>
1102
1103 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1104
1105 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1106
1107 * score-datadep.h: New file.
1108 * score-inst.h: New file.
1109
1110 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1111
1112 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1113 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1114 movdq2q and movq2dq.
1115
1116 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1117 Michael Meissner <michael.meissner@amd.com>
1118
1119 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1120
1121 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1122
1123 * i386.h (i386_optab): Add "nop" with memory reference.
1124
1125 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1126
1127 * i386.h (i386_optab): Update comment for 64bit NOP.
1128
1129 2006-06-06 Ben Elliston <bje@au.ibm.com>
1130 Anton Blanchard <anton@samba.org>
1131
1132 * ppc.h (PPC_OPCODE_POWER6): Define.
1133 Adjust whitespace.
1134
1135 2006-06-05 Thiemo Seufer <ths@mips.com>
1136
1137 * mips.h: Improve description of MT flags.
1138
1139 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1140
1141 * m68k.h (mcf_mask): Define.
1142
1143 2006-05-05 Thiemo Seufer <ths@mips.com>
1144 David Ung <davidu@mips.com>
1145
1146 * mips.h (enum): Add macro M_CACHE_AB.
1147
1148 2006-05-04 Thiemo Seufer <ths@mips.com>
1149 Nigel Stephens <nigel@mips.com>
1150 David Ung <davidu@mips.com>
1151
1152 * mips.h: Add INSN_SMARTMIPS define.
1153
1154 2006-04-30 Thiemo Seufer <ths@mips.com>
1155 David Ung <davidu@mips.com>
1156
1157 * mips.h: Defines udi bits and masks. Add description of
1158 characters which may appear in the args field of udi
1159 instructions.
1160
1161 2006-04-26 Thiemo Seufer <ths@networkno.de>
1162
1163 * mips.h: Improve comments describing the bitfield instruction
1164 fields.
1165
1166 2006-04-26 Julian Brown <julian@codesourcery.com>
1167
1168 * arm.h (FPU_VFP_EXT_V3): Define constant.
1169 (FPU_NEON_EXT_V1): Likewise.
1170 (FPU_VFP_HARD): Update.
1171 (FPU_VFP_V3): Define macro.
1172 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1173
1174 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1175
1176 * avr.h (AVR_ISA_PWMx): New.
1177
1178 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1179
1180 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1181 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1182 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1183 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1184 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1185
1186 2006-03-10 Paul Brook <paul@codesourcery.com>
1187
1188 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1189
1190 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1191
1192 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1193 first. Correct mask of bb "B" opcode.
1194
1195 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1196
1197 * i386.h (i386_optab): Support Intel Merom New Instructions.
1198
1199 2006-02-24 Paul Brook <paul@codesourcery.com>
1200
1201 * arm.h: Add V7 feature bits.
1202
1203 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1204
1205 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1206
1207 2006-01-31 Paul Brook <paul@codesourcery.com>
1208 Richard Earnshaw <rearnsha@arm.com>
1209
1210 * arm.h: Use ARM_CPU_FEATURE.
1211 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1212 (arm_feature_set): Change to a structure.
1213 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1214 ARM_FEATURE): New macros.
1215
1216 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1217
1218 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1219 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1220 (ADD_PC_INCR_OPCODE): Don't define.
1221
1222 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1223
1224 PR gas/1874
1225 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1226
1227 2005-11-14 David Ung <davidu@mips.com>
1228
1229 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1230 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1231 save/restore encoding of the args field.
1232
1233 2005-10-28 Dave Brolley <brolley@redhat.com>
1234
1235 Contribute the following changes:
1236 2005-02-16 Dave Brolley <brolley@redhat.com>
1237
1238 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1239 cgen_isa_mask_* to cgen_bitset_*.
1240 * cgen.h: Likewise.
1241
1242 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1243
1244 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1245 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1246 (CGEN_CPU_TABLE): Make isas a ponter.
1247
1248 2003-09-29 Dave Brolley <brolley@redhat.com>
1249
1250 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1251 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1252 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1253
1254 2002-12-13 Dave Brolley <brolley@redhat.com>
1255
1256 * cgen.h (symcat.h): #include it.
1257 (cgen-bitset.h): #include it.
1258 (CGEN_ATTR_VALUE_TYPE): Now a union.
1259 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1260 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1261 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1262 * cgen-bitset.h: New file.
1263
1264 2005-09-30 Catherine Moore <clm@cm00re.com>
1265
1266 * bfin.h: New file.
1267
1268 2005-10-24 Jan Beulich <jbeulich@novell.com>
1269
1270 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1271 indirect operands.
1272
1273 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1274
1275 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1276 Add FLAG_STRICT to pa10 ftest opcode.
1277
1278 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1279
1280 * hppa.h (pa_opcodes): Remove lha entries.
1281
1282 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1283
1284 * hppa.h (FLAG_STRICT): Revise comment.
1285 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1286 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1287 entries for "fdc".
1288
1289 2005-09-30 Catherine Moore <clm@cm00re.com>
1290
1291 * bfin.h: New file.
1292
1293 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1294
1295 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1296
1297 2005-09-06 Chao-ying Fu <fu@mips.com>
1298
1299 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1300 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1301 define.
1302 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1303 (INSN_ASE_MASK): Update to include INSN_MT.
1304 (INSN_MT): New define for MT ASE.
1305
1306 2005-08-25 Chao-ying Fu <fu@mips.com>
1307
1308 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1309 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1310 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1311 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1312 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1313 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1314 instructions.
1315 (INSN_DSP): New define for DSP ASE.
1316
1317 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1318
1319 * a29k.h: Delete.
1320
1321 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1322
1323 * ppc.h (PPC_OPCODE_E300): Define.
1324
1325 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1326
1327 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1328
1329 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1330
1331 PR gas/336
1332 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1333 and pitlb.
1334
1335 2005-07-27 Jan Beulich <jbeulich@novell.com>
1336
1337 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1338 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1339 Add movq-s as 64-bit variants of movd-s.
1340
1341 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1342
1343 * hppa.h: Fix punctuation in comment.
1344
1345 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1346 implicit space-register addressing. Set space-register bits on opcodes
1347 using implicit space-register addressing. Add various missing pa20
1348 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1349 space-register addressing. Use "fE" instead of "fe" in various
1350 fstw opcodes.
1351
1352 2005-07-18 Jan Beulich <jbeulich@novell.com>
1353
1354 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1355
1356 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1357
1358 * i386.h (i386_optab): Support Intel VMX Instructions.
1359
1360 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1361
1362 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1363
1364 2005-07-05 Jan Beulich <jbeulich@novell.com>
1365
1366 * i386.h (i386_optab): Add new insns.
1367
1368 2005-07-01 Nick Clifton <nickc@redhat.com>
1369
1370 * sparc.h: Add typedefs to structure declarations.
1371
1372 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1373
1374 PR 1013
1375 * i386.h (i386_optab): Update comments for 64bit addressing on
1376 mov. Allow 64bit addressing for mov and movq.
1377
1378 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1379
1380 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1381 respectively, in various floating-point load and store patterns.
1382
1383 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1384
1385 * hppa.h (FLAG_STRICT): Correct comment.
1386 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1387 PA 2.0 mneumonics when equivalent. Entries with cache control
1388 completers now require PA 1.1. Adjust whitespace.
1389
1390 2005-05-19 Anton Blanchard <anton@samba.org>
1391
1392 * ppc.h (PPC_OPCODE_POWER5): Define.
1393
1394 2005-05-10 Nick Clifton <nickc@redhat.com>
1395
1396 * Update the address and phone number of the FSF organization in
1397 the GPL notices in the following files:
1398 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1399 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1400 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1401 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1402 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1403 tic54x.h, tic80.h, v850.h, vax.h
1404
1405 2005-05-09 Jan Beulich <jbeulich@novell.com>
1406
1407 * i386.h (i386_optab): Add ht and hnt.
1408
1409 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1410
1411 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1412 Add xcrypt-ctr. Provide aliases without hyphens.
1413
1414 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1415
1416 Moved from ../ChangeLog
1417
1418 2005-04-12 Paul Brook <paul@codesourcery.com>
1419 * m88k.h: Rename psr macros to avoid conflicts.
1420
1421 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1422 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1423 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1424 and ARM_ARCH_V6ZKT2.
1425
1426 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1427 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1428 Remove redundant instruction types.
1429 (struct argument): X_op - new field.
1430 (struct cst4_entry): Remove.
1431 (no_op_insn): Declare.
1432
1433 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1434 * crx.h (enum argtype): Rename types, remove unused types.
1435
1436 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1437 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1438 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1439 (enum operand_type): Rearrange operands, edit comments.
1440 replace us<N> with ui<N> for unsigned immediate.
1441 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1442 displacements (respectively).
1443 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1444 (instruction type): Add NO_TYPE_INS.
1445 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1446 (operand_entry): New field - 'flags'.
1447 (operand flags): New.
1448
1449 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1450 * crx.h (operand_type): Remove redundant types i3, i4,
1451 i5, i8, i12.
1452 Add new unsigned immediate types us3, us4, us5, us16.
1453
1454 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1455
1456 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1457 adjust them accordingly.
1458
1459 2005-04-01 Jan Beulich <jbeulich@novell.com>
1460
1461 * i386.h (i386_optab): Add rdtscp.
1462
1463 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1464
1465 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1466 between memory and segment register. Allow movq for moving between
1467 general-purpose register and segment register.
1468
1469 2005-02-09 Jan Beulich <jbeulich@novell.com>
1470
1471 PR gas/707
1472 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1473 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1474 fnstsw.
1475
1476 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1477
1478 * m68k.h (m68008, m68ec030, m68882): Remove.
1479 (m68k_mask): New.
1480 (cpu_m68k, cpu_cf): New.
1481 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1482 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1483
1484 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1485
1486 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1487 * cgen.h (enum cgen_parse_operand_type): Add
1488 CGEN_PARSE_OPERAND_SYMBOLIC.
1489
1490 2005-01-21 Fred Fish <fnf@specifixinc.com>
1491
1492 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1493 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1494 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1495
1496 2005-01-19 Fred Fish <fnf@specifixinc.com>
1497
1498 * mips.h (struct mips_opcode): Add new pinfo2 member.
1499 (INSN_ALIAS): New define for opcode table entries that are
1500 specific instances of another entry, such as 'move' for an 'or'
1501 with a zero operand.
1502 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1503 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1504
1505 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1506
1507 * mips.h (CPU_RM9000): Define.
1508 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1509
1510 2004-11-25 Jan Beulich <jbeulich@novell.com>
1511
1512 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1513 to/from test registers are illegal in 64-bit mode. Add missing
1514 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1515 (previously one had to explicitly encode a rex64 prefix). Re-enable
1516 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1517 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1518
1519 2004-11-23 Jan Beulich <jbeulich@novell.com>
1520
1521 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1522 available only with SSE2. Change the MMX additions introduced by SSE
1523 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1524 instructions by their now designated identifier (since combining i686
1525 and 3DNow! does not really imply 3DNow!A).
1526
1527 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1528
1529 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1530 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1531
1532 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1533 Vineet Sharma <vineets@noida.hcltech.com>
1534
1535 * maxq.h: New file: Disassembly information for the maxq port.
1536
1537 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1538
1539 * i386.h (i386_optab): Put back "movzb".
1540
1541 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1542
1543 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1544 comments. Remove member cris_ver_sim. Add members
1545 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1546 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1547 (struct cris_support_reg, struct cris_cond15): New types.
1548 (cris_conds15): Declare.
1549 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1550 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1551 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1552 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1553 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1554 SIZE_FIELD_UNSIGNED.
1555
1556 2004-11-04 Jan Beulich <jbeulich@novell.com>
1557
1558 * i386.h (sldx_Suf): Remove.
1559 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1560 (q_FP): Define, implying no REX64.
1561 (x_FP, sl_FP): Imply FloatMF.
1562 (i386_optab): Split reg and mem forms of moving from segment registers
1563 so that the memory forms can ignore the 16-/32-bit operand size
1564 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1565 all non-floating-point instructions. Unite 32- and 64-bit forms of
1566 movsx, movzx, and movd. Adjust floating point operations for the above
1567 changes to the *FP macros. Add DefaultSize to floating point control
1568 insns operating on larger memory ranges. Remove left over comments
1569 hinting at certain insns being Intel-syntax ones where the ones
1570 actually meant are already gone.
1571
1572 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1573
1574 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1575 instruction type.
1576
1577 2004-09-30 Paul Brook <paul@codesourcery.com>
1578
1579 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1580 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1581
1582 2004-09-11 Theodore A. Roth <troth@openavr.org>
1583
1584 * avr.h: Add support for
1585 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1586
1587 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1588
1589 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1590
1591 2004-08-24 Dmitry Diky <diwil@spec.ru>
1592
1593 * msp430.h (msp430_opc): Add new instructions.
1594 (msp430_rcodes): Declare new instructions.
1595 (msp430_hcodes): Likewise..
1596
1597 2004-08-13 Nick Clifton <nickc@redhat.com>
1598
1599 PR/301
1600 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1601 processors.
1602
1603 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1604
1605 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1606
1607 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1608
1609 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1610
1611 2004-07-21 Jan Beulich <jbeulich@novell.com>
1612
1613 * i386.h: Adjust instruction descriptions to better match the
1614 specification.
1615
1616 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1617
1618 * arm.h: Remove all old content. Replace with architecture defines
1619 from gas/config/tc-arm.c.
1620
1621 2004-07-09 Andreas Schwab <schwab@suse.de>
1622
1623 * m68k.h: Fix comment.
1624
1625 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1626
1627 * crx.h: New file.
1628
1629 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1630
1631 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1632
1633 2004-05-24 Peter Barada <peter@the-baradas.com>
1634
1635 * m68k.h: Add 'size' to m68k_opcode.
1636
1637 2004-05-05 Peter Barada <peter@the-baradas.com>
1638
1639 * m68k.h: Switch from ColdFire chip name to core variant.
1640
1641 2004-04-22 Peter Barada <peter@the-baradas.com>
1642
1643 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1644 descriptions for new EMAC cases.
1645 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1646 handle Motorola MAC syntax.
1647 Allow disassembly of ColdFire V4e object files.
1648
1649 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1650
1651 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1652
1653 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1654
1655 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1656
1657 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1658
1659 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1660
1661 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1662
1663 * i386.h (i386_optab): Added xstore/xcrypt insns.
1664
1665 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1666
1667 * h8300.h (32bit ldc/stc): Add relaxing support.
1668
1669 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1670
1671 * h8300.h (BITOP): Pass MEMRELAX flag.
1672
1673 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1674
1675 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1676 except for the H8S.
1677
1678 For older changes see ChangeLog-9103
1679 \f
1680 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1681
1682 Copying and distribution of this file, with or without modification,
1683 are permitted in any medium without royalty provided the copyright
1684 notice and this notice are preserved.
1685
1686 Local Variables:
1687 mode: change-log
1688 left-margin: 8
1689 fill-column: 74
1690 version-control: never
1691 End:
GDB Binutils - Deliverables
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