1 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
3 * ppc.h (PPC_OPCODE_E500): Define.
5 2010-05-26 Catherine Moore <clm@codesourcery.com>
7 * opcode/mips.h (INSN_MIPS16): Remove.
9 2010-04-21 Joseph Myers <joseph@codesourcery.com>
11 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
13 2010-04-15 Nick Clifton <nickc@redhat.com>
15 * alpha.h: Update copyright notice to use GPLv3.
35 * m68hc11.h: Likewise.
41 * mn10200.h: Likewise.
42 * mn10300.h: Likewise.
54 * score-datadep.h: Likewise.
55 * score-inst.h: Likewise.
57 * spu-insns.h: Likewise.
66 2010-03-25 Joseph Myers <joseph@codesourcery.com>
68 * tic6x-control-registers.h, tic6x-insn-formats.h,
69 tic6x-opcode-table.h, tic6x.h: New.
71 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
73 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
75 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
77 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
79 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
81 * ia64.h (ia64_find_opcode): Remove argument name.
82 (ia64_find_next_opcode): Likewise.
83 (ia64_dis_opcode): Likewise.
84 (ia64_free_opcode): Likewise.
85 (ia64_find_dependency): Likewise.
87 2009-11-22 Doug Evans <dje@sebabeach.org>
89 * cgen.h: Include bfd_stdint.h.
90 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
92 2009-11-18 Paul Brook <paul@codesourcery.com>
94 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
96 2009-11-17 Paul Brook <paul@codesourcery.com>
97 Daniel Jacobowitz <dan@codesourcery.com>
99 * arm.h (ARM_EXT_V6_DSP): Define.
100 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
101 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
103 2009-11-04 DJ Delorie <dj@redhat.com>
105 * rx.h (rx_decode_opcode) (mvtipl): Add.
106 (mvtcp, mvfcp, opecp): Remove.
108 2009-11-02 Paul Brook <paul@codesourcery.com>
110 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
111 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
112 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
113 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
114 FPU_ARCH_NEON_VFP_V4): Define.
116 2009-10-23 Doug Evans <dje@sebabeach.org>
118 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
119 * cgen.h: Update. Improve multi-inclusion macro name.
121 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
123 * ppc.h (PPC_OPCODE_476): Define.
125 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
127 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
129 2009-09-29 DJ Delorie <dj@redhat.com>
133 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
135 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
137 2009-09-21 Ben Elliston <bje@au.ibm.com>
139 * ppc.h (PPC_OPCODE_PPCA2): New.
141 2009-09-05 Martin Thuresson <martin@mtme.org>
143 * ia64.h (struct ia64_operand): Renamed member class to op_class.
145 2009-08-29 Martin Thuresson <martin@mtme.org>
147 * tic30.h (template): Rename type template to
148 insn_template. Updated code to use new name.
149 * tic54x.h (template): Rename type template to
152 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
154 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
156 2009-06-11 Anthony Green <green@moxielogic.com>
158 * moxie.h (MOXIE_F3_PCREL): Define.
159 (moxie_form3_opc_info): Grow.
161 2009-06-06 Anthony Green <green@moxielogic.com>
163 * moxie.h (MOXIE_F1_M): Define.
165 2009-04-15 Anthony Green <green@moxielogic.com>
169 2009-04-06 DJ Delorie <dj@redhat.com>
171 * h8300.h: Add relaxation attributes to MOVA opcodes.
173 2009-03-10 Alan Modra <amodra@bigpond.net.au>
175 * ppc.h (ppc_parse_cpu): Declare.
177 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
179 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
180 and _IMM11 for mbitclr and mbitset.
181 * score-datadep.h: Update dependency information.
183 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
185 * ppc.h (PPC_OPCODE_POWER7): New.
187 2009-02-06 Doug Evans <dje@google.com>
189 * i386.h: Add comment regarding sse* insns and prefixes.
191 2009-02-03 Sandip Matte <sandip@rmicorp.com>
193 * mips.h (INSN_XLR): Define.
194 (INSN_CHIP_MASK): Update.
196 (OPCODE_IS_MEMBER): Update.
197 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
199 2009-01-28 Doug Evans <dje@google.com>
201 * opcode/i386.h: Add multiple inclusion protection.
202 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
203 (EDI_REG_NUM): New macros.
204 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
205 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
206 (REX_PREFIX_P): New macro.
208 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
210 * ppc.h (struct powerpc_opcode): New field "deprecated".
211 (PPC_OPCODE_NOPOWER4): Delete.
213 2008-11-28 Joshua Kinard <kumba@gentoo.org>
215 * mips.h: Define CPU_R14000, CPU_R16000.
216 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
218 2008-11-18 Catherine Moore <clm@codesourcery.com>
220 * arm.h (FPU_NEON_FP16): New.
221 (FPU_ARCH_NEON_FP16): New.
223 2008-11-06 Chao-ying Fu <fu@mips.com>
225 * mips.h: Doucument '1' for 5-bit sync type.
227 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
229 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
232 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
234 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
236 2008-07-30 Michael J. Eager <eager@eagercon.com>
238 * ppc.h (PPC_OPCODE_405): Define.
239 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
241 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
243 * ppc.h (ppc_cpu_t): New typedef.
244 (struct powerpc_opcode <flags>): Use it.
245 (struct powerpc_operand <insert, extract>): Likewise.
246 (struct powerpc_macro <flags>): Likewise.
248 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
250 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
251 Update comment before MIPS16 field descriptors to mention MIPS16.
252 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
254 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
255 New bit masks and shift counts for cins and exts.
257 * mips.h: Document new field descriptors +Q.
258 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
260 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
262 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
263 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
265 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
267 * ppc.h: (PPC_OPCODE_E500MC): New.
269 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
271 * i386.h (MAX_OPERANDS): Set to 5.
272 (MAX_MNEM_SIZE): Changed to 20.
274 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
276 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
278 2008-03-09 Paul Brook <paul@codesourcery.com>
280 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
282 2008-03-04 Paul Brook <paul@codesourcery.com>
284 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
285 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
286 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
288 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
289 Nick Clifton <nickc@redhat.com>
292 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
293 with a 32-bit displacement but without the top bit of the 4th byte
296 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
298 * cr16.h (cr16_num_optab): Declared.
300 2008-02-14 Hakan Ardo <hakan@debian.org>
303 * avr.h (AVR_ISA_2xxe): Define.
305 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
307 * mips.h: Update copyright.
308 (INSN_CHIP_MASK): New macro.
309 (INSN_OCTEON): New macro.
310 (CPU_OCTEON): New macro.
311 (OPCODE_IS_MEMBER): Handle Octeon instructions.
313 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
315 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
317 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
319 * avr.h (AVR_ISA_USB162): Add new opcode set.
320 (AVR_ISA_AVR3): Likewise.
322 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
324 * mips.h (INSN_LOONGSON_2E): New.
325 (INSN_LOONGSON_2F): New.
326 (CPU_LOONGSON_2E): New.
327 (CPU_LOONGSON_2F): New.
328 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
330 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
332 * mips.h (INSN_ISA*): Redefine certain values as an
333 enumeration. Update comments.
334 (mips_isa_table): New.
335 (ISA_MIPS*): Redefine to match enumeration.
336 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
339 2007-08-08 Ben Elliston <bje@au.ibm.com>
341 * ppc.h (PPC_OPCODE_PPCPS): New.
343 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
345 * m68k.h: Document j K & E.
347 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
349 * cr16.h: New file for CR16 target.
351 2007-05-02 Alan Modra <amodra@bigpond.net.au>
353 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
355 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
357 * m68k.h (mcfisa_c): New.
358 (mcfusp, mcf_mask): Adjust.
360 2007-04-20 Alan Modra <amodra@bigpond.net.au>
362 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
363 (num_powerpc_operands): Declare.
364 (PPC_OPERAND_SIGNED et al): Redefine as hex.
365 (PPC_OPERAND_PLUS1): Define.
367 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
369 * i386.h (REX_MODE64): Renamed to ...
371 (REX_EXTX): Renamed to ...
373 (REX_EXTY): Renamed to ...
375 (REX_EXTZ): Renamed to ...
378 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
380 * i386.h: Add entries from config/tc-i386.h and move tables
381 to opcodes/i386-opc.h.
383 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
385 * i386.h (FloatDR): Removed.
386 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
388 2007-03-01 Alan Modra <amodra@bigpond.net.au>
390 * spu-insns.h: Add soma double-float insns.
392 2007-02-20 Thiemo Seufer <ths@mips.com>
393 Chao-Ying Fu <fu@mips.com>
395 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
396 (INSN_DSPR2): Add flag for DSP R2 instructions.
397 (M_BALIGN): New macro.
399 2007-02-14 Alan Modra <amodra@bigpond.net.au>
401 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
402 and Seg3ShortFrom with Shortform.
404 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
407 * i386.h (i386_optab): Put the real "test" before the pseudo
410 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
412 * m68k.h (m68010up): OR fido_a.
414 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
416 * m68k.h (fido_a): New.
418 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
420 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
421 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
424 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
426 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
428 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
430 * score-inst.h (enum score_insn_type): Add Insn_internal.
432 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
433 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
434 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
435 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
436 Alan Modra <amodra@bigpond.net.au>
438 * spu-insns.h: New file.
441 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
443 * ppc.h (PPC_OPCODE_CELL): Define.
445 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
447 * i386.h : Modify opcode to support for the change in POPCNT opcode
448 in amdfam10 architecture.
450 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
452 * i386.h: Replace CpuMNI with CpuSSSE3.
454 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
455 Joseph Myers <joseph@codesourcery.com>
456 Ian Lance Taylor <ian@wasabisystems.com>
457 Ben Elliston <bje@wasabisystems.com>
459 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
461 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
463 * score-datadep.h: New file.
464 * score-inst.h: New file.
466 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
468 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
469 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
472 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
473 Michael Meissner <michael.meissner@amd.com>
475 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
477 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
479 * i386.h (i386_optab): Add "nop" with memory reference.
481 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
483 * i386.h (i386_optab): Update comment for 64bit NOP.
485 2006-06-06 Ben Elliston <bje@au.ibm.com>
486 Anton Blanchard <anton@samba.org>
488 * ppc.h (PPC_OPCODE_POWER6): Define.
491 2006-06-05 Thiemo Seufer <ths@mips.com>
493 * mips.h: Improve description of MT flags.
495 2006-05-25 Richard Sandiford <richard@codesourcery.com>
497 * m68k.h (mcf_mask): Define.
499 2006-05-05 Thiemo Seufer <ths@mips.com>
500 David Ung <davidu@mips.com>
502 * mips.h (enum): Add macro M_CACHE_AB.
504 2006-05-04 Thiemo Seufer <ths@mips.com>
505 Nigel Stephens <nigel@mips.com>
506 David Ung <davidu@mips.com>
508 * mips.h: Add INSN_SMARTMIPS define.
510 2006-04-30 Thiemo Seufer <ths@mips.com>
511 David Ung <davidu@mips.com>
513 * mips.h: Defines udi bits and masks. Add description of
514 characters which may appear in the args field of udi
517 2006-04-26 Thiemo Seufer <ths@networkno.de>
519 * mips.h: Improve comments describing the bitfield instruction
522 2006-04-26 Julian Brown <julian@codesourcery.com>
524 * arm.h (FPU_VFP_EXT_V3): Define constant.
525 (FPU_NEON_EXT_V1): Likewise.
526 (FPU_VFP_HARD): Update.
527 (FPU_VFP_V3): Define macro.
528 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
530 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
532 * avr.h (AVR_ISA_PWMx): New.
534 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
536 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
537 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
538 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
539 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
540 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
542 2006-03-10 Paul Brook <paul@codesourcery.com>
544 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
546 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
548 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
549 first. Correct mask of bb "B" opcode.
551 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
553 * i386.h (i386_optab): Support Intel Merom New Instructions.
555 2006-02-24 Paul Brook <paul@codesourcery.com>
557 * arm.h: Add V7 feature bits.
559 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
561 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
563 2006-01-31 Paul Brook <paul@codesourcery.com>
564 Richard Earnshaw <rearnsha@arm.com>
566 * arm.h: Use ARM_CPU_FEATURE.
567 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
568 (arm_feature_set): Change to a structure.
569 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
570 ARM_FEATURE): New macros.
572 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
574 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
575 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
576 (ADD_PC_INCR_OPCODE): Don't define.
578 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
581 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
583 2005-11-14 David Ung <davidu@mips.com>
585 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
586 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
587 save/restore encoding of the args field.
589 2005-10-28 Dave Brolley <brolley@redhat.com>
591 Contribute the following changes:
592 2005-02-16 Dave Brolley <brolley@redhat.com>
594 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
595 cgen_isa_mask_* to cgen_bitset_*.
598 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
600 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
601 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
602 (CGEN_CPU_TABLE): Make isas a ponter.
604 2003-09-29 Dave Brolley <brolley@redhat.com>
606 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
607 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
608 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
610 2002-12-13 Dave Brolley <brolley@redhat.com>
612 * cgen.h (symcat.h): #include it.
613 (cgen-bitset.h): #include it.
614 (CGEN_ATTR_VALUE_TYPE): Now a union.
615 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
616 (CGEN_ATTR_ENTRY): 'value' now unsigned.
617 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
618 * cgen-bitset.h: New file.
620 2005-09-30 Catherine Moore <clm@cm00re.com>
624 2005-10-24 Jan Beulich <jbeulich@novell.com>
626 * ia64.h (enum ia64_opnd): Move memory operand out of set of
629 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
631 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
632 Add FLAG_STRICT to pa10 ftest opcode.
634 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
636 * hppa.h (pa_opcodes): Remove lha entries.
638 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
640 * hppa.h (FLAG_STRICT): Revise comment.
641 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
642 before corresponding pa11 opcodes. Add strict pa10 register-immediate
645 2005-09-30 Catherine Moore <clm@cm00re.com>
649 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
651 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
653 2005-09-06 Chao-ying Fu <fu@mips.com>
655 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
656 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
658 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
659 (INSN_ASE_MASK): Update to include INSN_MT.
660 (INSN_MT): New define for MT ASE.
662 2005-08-25 Chao-ying Fu <fu@mips.com>
664 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
665 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
666 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
667 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
668 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
669 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
671 (INSN_DSP): New define for DSP ASE.
673 2005-08-18 Alan Modra <amodra@bigpond.net.au>
677 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
679 * ppc.h (PPC_OPCODE_E300): Define.
681 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
683 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
685 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
688 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
691 2005-07-27 Jan Beulich <jbeulich@novell.com>
693 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
694 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
695 Add movq-s as 64-bit variants of movd-s.
697 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
699 * hppa.h: Fix punctuation in comment.
701 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
702 implicit space-register addressing. Set space-register bits on opcodes
703 using implicit space-register addressing. Add various missing pa20
704 long-immediate opcodes. Remove various opcodes using implicit 3-bit
705 space-register addressing. Use "fE" instead of "fe" in various
708 2005-07-18 Jan Beulich <jbeulich@novell.com>
710 * i386.h (i386_optab): Operands of aam and aad are unsigned.
712 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
714 * i386.h (i386_optab): Support Intel VMX Instructions.
716 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
718 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
720 2005-07-05 Jan Beulich <jbeulich@novell.com>
722 * i386.h (i386_optab): Add new insns.
724 2005-07-01 Nick Clifton <nickc@redhat.com>
726 * sparc.h: Add typedefs to structure declarations.
728 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
731 * i386.h (i386_optab): Update comments for 64bit addressing on
732 mov. Allow 64bit addressing for mov and movq.
734 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
736 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
737 respectively, in various floating-point load and store patterns.
739 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
741 * hppa.h (FLAG_STRICT): Correct comment.
742 (pa_opcodes): Update load and store entries to allow both PA 1.X and
743 PA 2.0 mneumonics when equivalent. Entries with cache control
744 completers now require PA 1.1. Adjust whitespace.
746 2005-05-19 Anton Blanchard <anton@samba.org>
748 * ppc.h (PPC_OPCODE_POWER5): Define.
750 2005-05-10 Nick Clifton <nickc@redhat.com>
752 * Update the address and phone number of the FSF organization in
753 the GPL notices in the following files:
754 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
755 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
756 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
757 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
758 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
759 tic54x.h, tic80.h, v850.h, vax.h
761 2005-05-09 Jan Beulich <jbeulich@novell.com>
763 * i386.h (i386_optab): Add ht and hnt.
765 2005-04-18 Mark Kettenis <kettenis@gnu.org>
767 * i386.h: Insert hyphens into selected VIA PadLock extensions.
768 Add xcrypt-ctr. Provide aliases without hyphens.
770 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
772 Moved from ../ChangeLog
774 2005-04-12 Paul Brook <paul@codesourcery.com>
775 * m88k.h: Rename psr macros to avoid conflicts.
777 2005-03-12 Zack Weinberg <zack@codesourcery.com>
778 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
779 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
782 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
783 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
784 Remove redundant instruction types.
785 (struct argument): X_op - new field.
786 (struct cst4_entry): Remove.
787 (no_op_insn): Declare.
789 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
790 * crx.h (enum argtype): Rename types, remove unused types.
792 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
793 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
794 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
795 (enum operand_type): Rearrange operands, edit comments.
796 replace us<N> with ui<N> for unsigned immediate.
797 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
798 displacements (respectively).
799 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
800 (instruction type): Add NO_TYPE_INS.
801 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
802 (operand_entry): New field - 'flags'.
803 (operand flags): New.
805 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
806 * crx.h (operand_type): Remove redundant types i3, i4,
808 Add new unsigned immediate types us3, us4, us5, us16.
810 2005-04-12 Mark Kettenis <kettenis@gnu.org>
812 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
813 adjust them accordingly.
815 2005-04-01 Jan Beulich <jbeulich@novell.com>
817 * i386.h (i386_optab): Add rdtscp.
819 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
821 * i386.h (i386_optab): Don't allow the `l' suffix for moving
822 between memory and segment register. Allow movq for moving between
823 general-purpose register and segment register.
825 2005-02-09 Jan Beulich <jbeulich@novell.com>
828 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
829 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
832 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
834 * m68k.h (m68008, m68ec030, m68882): Remove.
836 (cpu_m68k, cpu_cf): New.
837 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
838 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
840 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
842 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
843 * cgen.h (enum cgen_parse_operand_type): Add
844 CGEN_PARSE_OPERAND_SYMBOLIC.
846 2005-01-21 Fred Fish <fnf@specifixinc.com>
848 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
849 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
850 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
852 2005-01-19 Fred Fish <fnf@specifixinc.com>
854 * mips.h (struct mips_opcode): Add new pinfo2 member.
855 (INSN_ALIAS): New define for opcode table entries that are
856 specific instances of another entry, such as 'move' for an 'or'
858 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
859 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
861 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
863 * mips.h (CPU_RM9000): Define.
864 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
866 2004-11-25 Jan Beulich <jbeulich@novell.com>
868 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
869 to/from test registers are illegal in 64-bit mode. Add missing
870 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
871 (previously one had to explicitly encode a rex64 prefix). Re-enable
872 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
873 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
875 2004-11-23 Jan Beulich <jbeulich@novell.com>
877 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
878 available only with SSE2. Change the MMX additions introduced by SSE
879 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
880 instructions by their now designated identifier (since combining i686
881 and 3DNow! does not really imply 3DNow!A).
883 2004-11-19 Alan Modra <amodra@bigpond.net.au>
885 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
886 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
888 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
889 Vineet Sharma <vineets@noida.hcltech.com>
891 * maxq.h: New file: Disassembly information for the maxq port.
893 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
895 * i386.h (i386_optab): Put back "movzb".
897 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
899 * cris.h (enum cris_insn_version_usage): Tweak formatting and
900 comments. Remove member cris_ver_sim. Add members
901 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
902 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
903 (struct cris_support_reg, struct cris_cond15): New types.
904 (cris_conds15): Declare.
905 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
906 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
907 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
908 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
909 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
912 2004-11-04 Jan Beulich <jbeulich@novell.com>
914 * i386.h (sldx_Suf): Remove.
915 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
916 (q_FP): Define, implying no REX64.
917 (x_FP, sl_FP): Imply FloatMF.
918 (i386_optab): Split reg and mem forms of moving from segment registers
919 so that the memory forms can ignore the 16-/32-bit operand size
920 distinction. Adjust a few others for Intel mode. Remove *FP uses from
921 all non-floating-point instructions. Unite 32- and 64-bit forms of
922 movsx, movzx, and movd. Adjust floating point operations for the above
923 changes to the *FP macros. Add DefaultSize to floating point control
924 insns operating on larger memory ranges. Remove left over comments
925 hinting at certain insns being Intel-syntax ones where the ones
926 actually meant are already gone.
928 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
930 * crx.h: Add COPS_REG_INS - Coprocessor Special register
933 2004-09-30 Paul Brook <paul@codesourcery.com>
935 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
936 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
938 2004-09-11 Theodore A. Roth <troth@openavr.org>
940 * avr.h: Add support for
941 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
943 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
945 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
947 2004-08-24 Dmitry Diky <diwil@spec.ru>
949 * msp430.h (msp430_opc): Add new instructions.
950 (msp430_rcodes): Declare new instructions.
951 (msp430_hcodes): Likewise..
953 2004-08-13 Nick Clifton <nickc@redhat.com>
956 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
959 2004-08-30 Michal Ludvig <mludvig@suse.cz>
961 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
963 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
965 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
967 2004-07-21 Jan Beulich <jbeulich@novell.com>
969 * i386.h: Adjust instruction descriptions to better match the
972 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
974 * arm.h: Remove all old content. Replace with architecture defines
975 from gas/config/tc-arm.c.
977 2004-07-09 Andreas Schwab <schwab@suse.de>
979 * m68k.h: Fix comment.
981 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
985 2004-06-24 Alan Modra <amodra@bigpond.net.au>
987 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
989 2004-05-24 Peter Barada <peter@the-baradas.com>
991 * m68k.h: Add 'size' to m68k_opcode.
993 2004-05-05 Peter Barada <peter@the-baradas.com>
995 * m68k.h: Switch from ColdFire chip name to core variant.
997 2004-04-22 Peter Barada <peter@the-baradas.com>
999 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1000 descriptions for new EMAC cases.
1001 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1002 handle Motorola MAC syntax.
1003 Allow disassembly of ColdFire V4e object files.
1005 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1007 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1009 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1011 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1013 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1015 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1017 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1019 * i386.h (i386_optab): Added xstore/xcrypt insns.
1021 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1023 * h8300.h (32bit ldc/stc): Add relaxing support.
1025 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1027 * h8300.h (BITOP): Pass MEMRELAX flag.
1029 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1031 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1034 For older changes see ChangeLog-9103
1040 version-control: never