include/opcode/ChangeLog

   1 2009-02-06  Doug Evans  <dje@google.com>
   2
   3         * i386.h: Add comment regarding sse* insns and prefixes.
   4
   5 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
   6
   7         * mips.h (INSN_XLR): Define.
   8         (INSN_CHIP_MASK): Update.
   9         (CPU_XLR): Define.
  10         (OPCODE_IS_MEMBER): Update.
  11         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  12
  13 2009-01-28  Doug Evans  <dje@google.com>
  14
  15         * opcode/i386.h: Add multiple inclusion protection.
  16         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  17         (EDI_REG_NUM): New macros.
  18         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  19         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  20         (REX_PREFIX_P): New macro.
  21
  22 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  23
  24         * ppc.h (struct powerpc_opcode): New field "deprecated".
  25         (PPC_OPCODE_NOPOWER4): Delete.
  26
  27 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  28
  29         * mips.h: Define CPU_R14000, CPU_R16000.
  30         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  31
  32 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  33
  34         * arm.h (FPU_NEON_FP16): New.
  35         (FPU_ARCH_NEON_FP16): New.
  36
  37 2008-11-06  Chao-ying Fu  <fu@mips.com>
  38
  39         * mips.h: Doucument '1' for 5-bit sync type.
  40
  41 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  44         IA64_RS_CR.
  45
  46 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  47
  48         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  49
  50 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  51
  52         * ppc.h (PPC_OPCODE_405): Define.
  53         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  54
  55 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  56
  57         * ppc.h (ppc_cpu_t): New typedef.
  58         (struct powerpc_opcode <flags>): Use it.
  59         (struct powerpc_operand <insert, extract>): Likewise.
  60         (struct powerpc_macro <flags>): Likewise.
  61
  62 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  63
  64         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  65         Update comment before MIPS16 field descriptors to mention MIPS16.
  66         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  67         BBIT.
  68         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  69         New bit masks and shift counts for cins and exts.
  70
  71         * mips.h: Document new field descriptors +Q.
  72         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  73
  74 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  75
  76         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  77         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  78
  79 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  80
  81         * ppc.h: (PPC_OPCODE_E500MC): New.
  82
  83 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  84
  85         * i386.h (MAX_OPERANDS): Set to 5.
  86         (MAX_MNEM_SIZE): Changed to 20.
  87
  88 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  89
  90         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  91
  92 2008-03-09  Paul Brook  <paul@codesourcery.com>
  93
  94         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  95
  96 2008-03-04  Paul Brook  <paul@codesourcery.com>
  97
  98         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  99         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 100         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 101
 102 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 103             Nick Clifton  <nickc@redhat.com>
 104
 105         PR 3134
 106         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 107         with a 32-bit displacement but without the top bit of the 4th byte
 108         set.
 109
 110 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 111
 112         * cr16.h (cr16_num_optab): Declared.
 113
 114 2008-02-14  Hakan Ardo  <hakan@debian.org>
 115
 116         PR gas/2626
 117         * avr.h (AVR_ISA_2xxe): Define.
 118
 119 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 120
 121         * mips.h: Update copyright.
 122         (INSN_CHIP_MASK): New macro.
 123         (INSN_OCTEON): New macro.
 124         (CPU_OCTEON): New macro.
 125         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 126
 127 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 128
 129         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 130
 131 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 132
 133         * avr.h (AVR_ISA_USB162): Add new opcode set.
 134         (AVR_ISA_AVR3): Likewise.
 135
 136 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 137
 138         * mips.h (INSN_LOONGSON_2E): New.
 139         (INSN_LOONGSON_2F): New.
 140         (CPU_LOONGSON_2E): New.
 141         (CPU_LOONGSON_2F): New.
 142         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 143
 144 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 145
 146         * mips.h (INSN_ISA*): Redefine certain values as an
 147         enumeration.  Update comments.
 148         (mips_isa_table): New.
 149         (ISA_MIPS*): Redefine to match enumeration.
 150         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 151         values.
 152
 153 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 154
 155         * ppc.h (PPC_OPCODE_PPCPS): New.
 156
 157 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 158
 159         * m68k.h: Document j K & E.
 160
 161 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 162
 163         * cr16.h: New file for CR16 target.
 164
 165 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 166
 167         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 168
 169 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 170
 171         * m68k.h (mcfisa_c): New.
 172         (mcfusp, mcf_mask): Adjust.
 173
 174 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 175
 176         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 177         (num_powerpc_operands): Declare.
 178         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 179         (PPC_OPERAND_PLUS1): Define.
 180
 181 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 182
 183         * i386.h (REX_MODE64): Renamed to ...
 184         (REX_W): This.
 185         (REX_EXTX): Renamed to ...
 186         (REX_R): This.
 187         (REX_EXTY): Renamed to ...
 188         (REX_X): This.
 189         (REX_EXTZ): Renamed to ...
 190         (REX_B): This.
 191
 192 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * i386.h: Add entries from config/tc-i386.h and move tables
 195         to opcodes/i386-opc.h.
 196
 197 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         * i386.h (FloatDR): Removed.
 200         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 201
 202 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 203
 204         * spu-insns.h: Add soma double-float insns.
 205
 206 2007-02-20  Thiemo Seufer  <ths@mips.com>
 207             Chao-Ying Fu  <fu@mips.com>
 208
 209         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 210         (INSN_DSPR2): Add flag for DSP R2 instructions.
 211         (M_BALIGN): New macro.
 212
 213 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 214
 215         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 216         and Seg3ShortFrom with Shortform.
 217
 218 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         PR gas/4027
 221         * i386.h (i386_optab): Put the real "test" before the pseudo
 222         one.
 223
 224 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 225
 226         * m68k.h (m68010up): OR fido_a.
 227
 228 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 229
 230         * m68k.h (fido_a): New.
 231
 232 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 233
 234         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 235         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 236         values.
 237
 238 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 241
 242 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 243
 244         * score-inst.h (enum score_insn_type): Add Insn_internal.
 245
 246 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 247             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 248             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 249             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 250             Alan Modra  <amodra@bigpond.net.au>
 251
 252         * spu-insns.h: New file.
 253         * spu.h: New file.
 254
 255 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 256
 257         * ppc.h (PPC_OPCODE_CELL): Define.
 258
 259 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 260
 261         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 262         in amdfam10 architecture.
 263
 264 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         * i386.h: Replace CpuMNI with CpuSSSE3.
 267
 268 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 269             Joseph Myers  <joseph@codesourcery.com>
 270             Ian Lance Taylor  <ian@wasabisystems.com>
 271             Ben Elliston  <bje@wasabisystems.com>
 272
 273         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 274
 275 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 276
 277         * score-datadep.h: New file.
 278         * score-inst.h: New file.
 279
 280 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 283         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 284         movdq2q and movq2dq.
 285
 286 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 287            Michael Meissner             <michael.meissner@amd.com>
 288
 289         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 290
 291 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * i386.h (i386_optab): Add "nop" with memory reference.
 294
 295 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386.h (i386_optab): Update comment for 64bit NOP.
 298
 299 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 300             Anton Blanchard  <anton@samba.org>
 301
 302         * ppc.h (PPC_OPCODE_POWER6): Define.
 303         Adjust whitespace.
 304
 305 2006-06-05  Thiemo Seufer  <ths@mips.com>
 306
 307         * mips.h: Improve description of MT flags.
 308
 309 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 310
 311         * m68k.h (mcf_mask): Define.
 312
 313 2006-05-05  Thiemo Seufer  <ths@mips.com>
 314             David Ung  <davidu@mips.com>
 315
 316         * mips.h (enum): Add macro M_CACHE_AB.
 317
 318 2006-05-04  Thiemo Seufer  <ths@mips.com>
 319             Nigel Stephens  <nigel@mips.com>
 320             David Ung  <davidu@mips.com>
 321
 322         * mips.h: Add INSN_SMARTMIPS define.
 323
 324 2006-04-30  Thiemo Seufer  <ths@mips.com>
 325             David Ung  <davidu@mips.com>
 326
 327         * mips.h: Defines udi bits and masks.  Add description of
 328         characters which may appear in the args field of udi
 329         instructions.
 330
 331 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 332
 333         * mips.h: Improve comments describing the bitfield instruction
 334         fields.
 335
 336 2006-04-26  Julian Brown  <julian@codesourcery.com>
 337
 338         * arm.h (FPU_VFP_EXT_V3): Define constant.
 339         (FPU_NEON_EXT_V1): Likewise.
 340         (FPU_VFP_HARD): Update.
 341         (FPU_VFP_V3): Define macro.
 342         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 343
 344 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 345
 346         * avr.h (AVR_ISA_PWMx): New.
 347
 348 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 349
 350         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 351         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 352         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 353         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 354         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 355
 356 2006-03-10  Paul Brook  <paul@codesourcery.com>
 357
 358         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 359
 360 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 361
 362         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 363         first.  Correct mask of bb "B" opcode.
 364
 365 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 366
 367         * i386.h (i386_optab): Support Intel Merom New Instructions.
 368
 369 2006-02-24  Paul Brook  <paul@codesourcery.com>
 370
 371         * arm.h: Add V7 feature bits.
 372
 373 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 376
 377 2006-01-31  Paul Brook  <paul@codesourcery.com>
 378         Richard Earnshaw <rearnsha@arm.com>
 379
 380         * arm.h: Use ARM_CPU_FEATURE.
 381         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 382         (arm_feature_set): Change to a structure.
 383         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 384         ARM_FEATURE): New macros.
 385
 386 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 387
 388         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 389         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 390         (ADD_PC_INCR_OPCODE): Don't define.
 391
 392 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         PR gas/1874
 395         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 396
 397 2005-11-14  David Ung  <davidu@mips.com>
 398
 399         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 400         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 401         save/restore encoding of the args field.
 402
 403 2005-10-28  Dave Brolley  <brolley@redhat.com>
 404
 405         Contribute the following changes:
 406         2005-02-16  Dave Brolley  <brolley@redhat.com>
 407
 408         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 409         cgen_isa_mask_* to cgen_bitset_*.
 410         * cgen.h: Likewise.
 411
 412         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 413
 414         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 415         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 416         (CGEN_CPU_TABLE): Make isas a ponter.
 417
 418         2003-09-29  Dave Brolley  <brolley@redhat.com>
 419
 420         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 421         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 422         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 423
 424         2002-12-13  Dave Brolley  <brolley@redhat.com>
 425
 426         * cgen.h (symcat.h): #include it.
 427         (cgen-bitset.h): #include it.
 428         (CGEN_ATTR_VALUE_TYPE): Now a union.
 429         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 430         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 431         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 432         * cgen-bitset.h: New file.
 433
 434 2005-09-30  Catherine Moore  <clm@cm00re.com>
 435
 436         * bfin.h: New file.
 437
 438 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 439
 440         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 441         indirect operands.
 442
 443 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 444
 445         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 446         Add FLAG_STRICT to pa10 ftest opcode.
 447
 448 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 449
 450         * hppa.h (pa_opcodes): Remove lha entries.
 451
 452 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 453
 454         * hppa.h (FLAG_STRICT): Revise comment.
 455         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 456         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 457         entries for "fdc".
 458
 459 2005-09-30  Catherine Moore  <clm@cm00re.com>
 460
 461         * bfin.h: New file.
 462
 463 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 464
 465         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 466
 467 2005-09-06  Chao-ying Fu  <fu@mips.com>
 468
 469         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 470         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 471         define.
 472         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 473         (INSN_ASE_MASK): Update to include INSN_MT.
 474         (INSN_MT): New define for MT ASE.
 475
 476 2005-08-25  Chao-ying Fu  <fu@mips.com>
 477
 478         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 479         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 480         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 481         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 482         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 483         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 484         instructions.
 485         (INSN_DSP): New define for DSP ASE.
 486
 487 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 488
 489         * a29k.h: Delete.
 490
 491 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 492
 493         * ppc.h (PPC_OPCODE_E300): Define.
 494
 495 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 496
 497         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 498
 499 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 500
 501         PR gas/336
 502         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 503         and pitlb.
 504
 505 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 506
 507         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 508         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 509         Add movq-s as 64-bit variants of movd-s.
 510
 511 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 512
 513         * hppa.h: Fix punctuation in comment.
 514
 515         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 516         implicit space-register addressing.  Set space-register bits on opcodes
 517         using implicit space-register addressing.  Add various missing pa20
 518         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 519         space-register addressing.  Use "fE" instead of "fe" in various
 520         fstw opcodes.
 521
 522 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 523
 524         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 525
 526 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 527
 528         * i386.h (i386_optab): Support Intel VMX Instructions.
 529
 530 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 531
 532         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 533
 534 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 535
 536         * i386.h (i386_optab): Add new insns.
 537
 538 2005-07-01  Nick Clifton  <nickc@redhat.com>
 539
 540         * sparc.h: Add typedefs to structure declarations.
 541
 542 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 543
 544         PR 1013
 545         * i386.h (i386_optab): Update comments for 64bit addressing on
 546         mov. Allow 64bit addressing for mov and movq.
 547
 548 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 549
 550         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 551         respectively, in various floating-point load and store patterns.
 552
 553 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 554
 555         * hppa.h (FLAG_STRICT): Correct comment.
 556         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 557         PA 2.0 mneumonics when equivalent.  Entries with cache control
 558         completers now require PA 1.1.  Adjust whitespace.
 559
 560 2005-05-19  Anton Blanchard  <anton@samba.org>
 561
 562         * ppc.h (PPC_OPCODE_POWER5): Define.
 563
 564 2005-05-10  Nick Clifton  <nickc@redhat.com>
 565
 566         * Update the address and phone number of the FSF organization in
 567         the GPL notices in the following files:
 568         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 569         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 570         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 571         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 572         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 573         tic54x.h, tic80.h, v850.h, vax.h
 574
 575 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 576
 577         * i386.h (i386_optab): Add ht and hnt.
 578
 579 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 580
 581         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 582         Add xcrypt-ctr.  Provide aliases without hyphens.
 583
 584 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 585
 586         Moved from ../ChangeLog
 587
 588         2005-04-12  Paul Brook  <paul@codesourcery.com>
 589         * m88k.h: Rename psr macros to avoid conflicts.
 590
 591         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 592         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 593         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 594         and ARM_ARCH_V6ZKT2.
 595
 596         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 597         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 598         Remove redundant instruction types.
 599         (struct argument): X_op - new field.
 600         (struct cst4_entry): Remove.
 601         (no_op_insn): Declare.
 602
 603         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 604         * crx.h (enum argtype): Rename types, remove unused types.
 605
 606         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 607         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 608         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 609         (enum operand_type): Rearrange operands, edit comments.
 610         replace us<N> with ui<N> for unsigned immediate.
 611         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 612         displacements (respectively).
 613         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 614         (instruction type): Add NO_TYPE_INS.
 615         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 616         (operand_entry): New field - 'flags'.
 617         (operand flags): New.
 618
 619         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 620         * crx.h (operand_type): Remove redundant types i3, i4,
 621         i5, i8, i12.
 622         Add new unsigned immediate types us3, us4, us5, us16.
 623
 624 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 625
 626         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 627         adjust them accordingly.
 628
 629 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 630
 631         * i386.h (i386_optab): Add rdtscp.
 632
 633 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 634
 635         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 636         between memory and segment register. Allow movq for moving between
 637         general-purpose register and segment register.
 638
 639 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 640
 641         PR gas/707
 642         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 643         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 644         fnstsw.
 645
 646 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 647
 648         * m68k.h (m68008, m68ec030, m68882): Remove.
 649         (m68k_mask): New.
 650         (cpu_m68k, cpu_cf): New.
 651         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 652         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 653
 654 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 655
 656         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 657         * cgen.h (enum cgen_parse_operand_type): Add
 658         CGEN_PARSE_OPERAND_SYMBOLIC.
 659
 660 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 661
 662         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 663         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 664         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 665
 666 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 667
 668         * mips.h (struct mips_opcode): Add new pinfo2 member.
 669         (INSN_ALIAS): New define for opcode table entries that are
 670         specific instances of another entry, such as 'move' for an 'or'
 671         with a zero operand.
 672         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 673         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 674
 675 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 676
 677         * mips.h (CPU_RM9000): Define.
 678         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 679
 680 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 681
 682         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 683         to/from test registers are illegal in 64-bit mode. Add missing
 684         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 685         (previously one had to explicitly encode a rex64 prefix). Re-enable
 686         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 687         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 688
 689 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 690
 691         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 692         available only with SSE2. Change the MMX additions introduced by SSE
 693         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 694         instructions by their now designated identifier (since combining i686
 695         and 3DNow! does not really imply 3DNow!A).
 696
 697 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 698
 699         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 700         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 701
 702 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 703             Vineet Sharma      <vineets@noida.hcltech.com>
 704
 705         * maxq.h: New file: Disassembly information for the maxq port.
 706
 707 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386.h (i386_optab): Put back "movzb".
 710
 711 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 712
 713         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 714         comments.  Remove member cris_ver_sim.  Add members
 715         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 716         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 717         (struct cris_support_reg, struct cris_cond15): New types.
 718         (cris_conds15): Declare.
 719         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 720         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 721         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 722         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 723         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 724         SIZE_FIELD_UNSIGNED.
 725
 726 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 727
 728         * i386.h (sldx_Suf): Remove.
 729         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 730         (q_FP): Define, implying no REX64.
 731         (x_FP, sl_FP): Imply FloatMF.
 732         (i386_optab): Split reg and mem forms of moving from segment registers
 733         so that the memory forms can ignore the 16-/32-bit operand size
 734         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 735         all non-floating-point instructions. Unite 32- and 64-bit forms of
 736         movsx, movzx, and movd. Adjust floating point operations for the above
 737         changes to the *FP macros. Add DefaultSize to floating point control
 738         insns operating on larger memory ranges. Remove left over comments
 739         hinting at certain insns being Intel-syntax ones where the ones
 740         actually meant are already gone.
 741
 742 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 743
 744         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 745         instruction type.
 746
 747 2004-09-30  Paul Brook  <paul@codesourcery.com>
 748
 749         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 750         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 751
 752 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 753
 754         * avr.h: Add support for
 755         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 756
 757 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 758
 759         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 760
 761 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 762
 763         * msp430.h (msp430_opc): Add new instructions.
 764         (msp430_rcodes): Declare new instructions.
 765         (msp430_hcodes): Likewise..
 766
 767 2004-08-13  Nick Clifton  <nickc@redhat.com>
 768
 769         PR/301
 770         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 771         processors.
 772
 773 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 774
 775         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 776
 777 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 780
 781 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 782
 783         * i386.h: Adjust instruction descriptions to better match the
 784         specification.
 785
 786 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 787
 788         * arm.h: Remove all old content.  Replace with architecture defines
 789         from gas/config/tc-arm.c.
 790
 791 2004-07-09  Andreas Schwab  <schwab@suse.de>
 792
 793         * m68k.h: Fix comment.
 794
 795 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 796
 797         * crx.h: New file.
 798
 799 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 800
 801         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 802
 803 2004-05-24  Peter Barada  <peter@the-baradas.com>
 804
 805         * m68k.h: Add 'size' to m68k_opcode.
 806
 807 2004-05-05  Peter Barada  <peter@the-baradas.com>
 808
 809         * m68k.h: Switch from ColdFire chip name to core variant.
 810
 811 2004-04-22  Peter Barada  <peter@the-baradas.com>
 812
 813         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 814         descriptions for new EMAC cases.
 815         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 816         handle Motorola MAC syntax.
 817         Allow disassembly of ColdFire V4e object files.
 818
 819 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 820
 821         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 822
 823 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 824
 825         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 826
 827 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 828
 829         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 830
 831 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 832
 833         * i386.h (i386_optab): Added xstore/xcrypt insns.
 834
 835 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 836
 837         * h8300.h (32bit ldc/stc): Add relaxing support.
 838
 839 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 840
 841         * h8300.h (BITOP): Pass MEMRELAX flag.
 842
 843 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 844
 845         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 846         except for the H8S.
 847
 848 For older changes see ChangeLog-9103
 849 \f
 850 Local Variables:
 851 mode: change-log
 852 left-margin: 8
 853 fill-column: 74
 854 version-control: never
 855 End: