include/opcode/ChangeLog

   1 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
   2
   3         * xgate.h: Header file for XGATE assembler.
   4
   5 2012-04-27  David S. Miller  <davem@davemloft.net>
   6
   7         * sparc.h: Document new arg code' )' for crypto RS3
   8         immediates.
   9
  10         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
  11         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
  12         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
  13         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
  14         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
  15         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
  16         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
  17         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
  18         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
  19         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
  20         HWCAP_CBCOND, HWCAP_CRC32): New defines.
  21
  22 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
  23
  24         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
  25
  26 2012-02-27  Alan Modra  <amodra@gmail.com>
  27
  28         * crx.h (cst4_map): Update declaration.
  29
  30 2012-02-25  Walter Lee  <walt@tilera.com>
  31
  32         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
  33         TILEGX_OPC_LD_TLS.
  34         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
  35         TILEPRO_OPC_LW_TLS_SN.
  36
  37 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
  40         (XRELEASE_PREFIX_OPCODE): Likewise.
  41
  42 2011-12-08  Andrew Pinski  <apinski@cavium.com>
  43             Adam Nemet  <anemet@caviumnetworks.com>
  44
  45         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
  46         (INSN_OCTEON2): New macro.
  47         (CPU_OCTEON2): New macro.
  48         (OPCODE_IS_MEMBER): Add Octeon2.
  49
  50 2011-11-29  Andrew Pinski  <apinski@cavium.com>
  51
  52         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
  53         (INSN_OCTEONP): New macro.
  54         (CPU_OCTEONP): New macro.
  55         (OPCODE_IS_MEMBER): Add Octeon+.
  56         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
  57
  58 2011-11-01  DJ Delorie  <dj@redhat.com>
  59
  60         * rl78.h: New file.
  61
  62 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
  63
  64         * mips.h: Fix a typo in description.
  65
  66 2011-09-21  David S. Miller  <davem@davemloft.net>
  67
  68         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
  69         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
  70         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
  71         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
  72
  73 2011-08-09  Chao-ying Fu  <fu@mips.com>
  74             Maciej W. Rozycki  <macro@codesourcery.com>
  75
  76         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
  77         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
  78         (INSN_ASE_MASK): Add the MCU bit.
  79         (INSN_MCU): New macro.
  80         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
  81         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
  82
  83 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
  84
  85         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
  86         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
  87         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
  88         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
  89         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
  90         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
  91         (INSN2_READ_GPR_MMN): Likewise.
  92         (INSN2_READ_FPR_D): Change the bit used.
  93         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
  94         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
  95         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
  96         (INSN2_COND_BRANCH): Likewise.
  97         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
  98         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
  99         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 100         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 101         (INSN2_MOD_GPR_MN): Likewise.
 102
 103 2011-08-05  David S. Miller  <davem@davemloft.net>
 104
 105         * sparc.h: Document new format codes '4', '5', and '('.
 106         (OPF_LOW4, RS3): New macros.
 107
 108 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 109
 110         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 111         order of flags documented.
 112
 113 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 114
 115         * mips.h: Clarify the description of microMIPS instruction
 116         manipulation macros.
 117         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 118
 119 2011-07-24  Chao-ying Fu  <fu@mips.com>
 120             Maciej W. Rozycki  <macro@codesourcery.com>
 121
 122         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 123         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 124         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 125         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 126         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 127         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 128         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 129         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 130         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 131         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 132         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 133         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 134         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 135         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 136         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 137         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 138         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 139         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 140         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 141         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 142         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 143         (INSN_WRITE_GPR_S): New macro.
 144         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 145         (INSN2_READ_FPR_D): Likewise.
 146         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 147         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 148         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 149         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 150         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 151         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 152         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 153         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 154         (CPU_MICROMIPS): New macro.
 155         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 156         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 157         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 158         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 159         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 160         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 161         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 162         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 163         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 164         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 165         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 166         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 167         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 168         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 169         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 170         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 171         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 172         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 173         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 174         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 175         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 176         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 177         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 178         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 179         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 180         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 181         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 182         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 183         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 184         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 185         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 186         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 187         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 188         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 189         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 190         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 191         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 192         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 193         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 194         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 195         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 196         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 197         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 198         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 199         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 200         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 201         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 202         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 203         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 204         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 205         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 206         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 207         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 208         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 209         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 210         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 211         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 212         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 213         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 214         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 215         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 216         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 217         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 218         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 219         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 220         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 221         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 222         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 223         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 224         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 225         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 226         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 227         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 228         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 229         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 230         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 231         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 232         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 233         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 234         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 235         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 236         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 237         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 238         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 239         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 240         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 241         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 242         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 243         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 244         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 245         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 246         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 247         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 248         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 249         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 250         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 251         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 252         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 253         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 254         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 255         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 256         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 257         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 258         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 259         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 260         (micromips_opcodes): New declaration.
 261         (bfd_micromips_num_opcodes): Likewise.
 262
 263 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 264
 265         * mips.h (INSN_TRAP): Rename to...
 266         (INSN_NO_DELAY_SLOT): ... this.
 267         (INSN_SYNC): Remove macro.
 268
 269 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 270
 271         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 272         a duplicate of AVR_ISA_SPM.
 273
 274 2011-07-01  Nick Clifton  <nickc@redhat.com>
 275
 276         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 277
 278 2011-06-18  Robin Getz  <robin.getz@analog.com>
 279
 280         * bfin.h (is_macmod_signed): New func
 281
 282 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 283
 284         * bfin.h (is_macmod_pmove): Add missing space before func args.
 285         (is_macmod_hmove): Likewise.
 286
 287 2011-06-13  Walter Lee  <walt@tilera.com>
 288
 289         * tilegx.h: New file.
 290         * tilepro.h: New file.
 291
 292 2011-05-31  Paul Brook  <paul@codesourcery.com>
 293
 294         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 295
 296 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 297
 298         * s390.h: Replace S390_OPERAND_REG_EVEN with
 299         S390_OPERAND_REG_PAIR.
 300
 301 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 302
 303         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 304
 305 2011-04-18  Julian Brown  <julian@codesourcery.com>
 306
 307         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 308
 309 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 310
 311         PR gas/12296
 312         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 313
 314 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 315
 316         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 317         New instruction set flags.
 318         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 319
 320 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 321
 322         * mips.h (M_PREF_AB): New enum value.
 323
 324 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 327         M_IU): Define.
 328         (is_macmod_pmove, is_macmod_hmove): New functions.
 329
 330 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 331
 332         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 333
 334 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 335
 336         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 337         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 338
 339 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 340
 341         PR gas/11395
 342         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 343         "bb" entries.
 344
 345 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 346
 347         PR gas/11395
 348         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 349
 350 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 351
 352         * mips.h: Update commentary after last commit.
 353
 354 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 355
 356         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 357         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 358         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 359
 360 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 361
 362         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 363
 364 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 365
 366         * mips.h: Fix previous commit.
 367
 368 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 369
 370         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 371         (INSN_LOONGSON_3A): Clear bit 31.
 372
 373 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 374
 375         PR gas/12198
 376         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 377         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 378         (ARM_ARCH_V6M_ONLY): New define.
 379
 380 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 381
 382         * mips.h (INSN_LOONGSON_3A): Defined.
 383         (CPU_LOONGSON_3A): Defined.
 384         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 385
 386 2010-10-09  Matt Rice  <ratmice@gmail.com>
 387
 388         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 389         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 390
 391 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 392
 393         * arm.h (ARM_EXT_VIRT): New define.
 394         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 395         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 396         Extensions.
 397
 398 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 399
 400         * arm.h (ARM_AEXT_ADIV): New define.
 401         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 402
 403 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 404
 405         * arm.h (ARM_EXT_OS): New define.
 406         (ARM_AEXT_V6SM): Likewise.
 407         (ARM_ARCH_V6SM): Likewise.
 408
 409 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 410
 411         * arm.h (ARM_EXT_MP): Add.
 412         (ARM_ARCH_V7A_MP): Likewise.
 413
 414 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 415
 416         * bfin.h: Declare pseudoChr structs/defines.
 417
 418 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 419
 420         * bfin.h: Strip trailing whitespace.
 421
 422 2010-07-29  DJ Delorie  <dj@redhat.com>
 423
 424         * rx.h (RX_Operand_Type): Add TwoReg.
 425         (RX_Opcode_ID): Remove ediv and ediv2.
 426
 427 2010-07-27  DJ Delorie  <dj@redhat.com>
 428
 429         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 430
 431 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 432             Ina Pandit  <ina.pandit@kpitcummins.com>
 433
 434         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 435         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 436         PROCESSOR_V850E2_ALL.
 437         Remove PROCESSOR_V850EA support.
 438         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 439         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 440         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 441         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 442         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 443         V850_OPERAND_PERCENT.
 444         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 445         V850_NOT_R0.
 446         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 447         and V850E_PUSH_POP
 448
 449 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 450
 451         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 452         (MIPS16_INSN_BRANCH): Rename to...
 453         (MIPS16_INSN_COND_BRANCH): ... this.
 454
 455 2010-07-03  Alan Modra  <amodra@gmail.com>
 456
 457         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 458         Renumber other PPC_OPCODE defines.
 459
 460 2010-07-03  Alan Modra  <amodra@gmail.com>
 461
 462         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 463
 464 2010-06-29  Alan Modra  <amodra@gmail.com>
 465
 466         * maxq.h: Delete file.
 467
 468 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 469
 470         * ppc.h (PPC_OPCODE_E500): Define.
 471
 472 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 473
 474         * opcode/mips.h (INSN_MIPS16): Remove.
 475
 476 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 477
 478         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 479
 480 2010-04-15  Nick Clifton  <nickc@redhat.com>
 481
 482         * alpha.h: Update copyright notice to use GPLv3.
 483         * arc.h: Likewise.
 484         * arm.h: Likewise.
 485         * avr.h: Likewise.
 486         * bfin.h: Likewise.
 487         * cgen.h: Likewise.
 488         * convex.h: Likewise.
 489         * cr16.h: Likewise.
 490         * cris.h: Likewise.
 491         * crx.h: Likewise.
 492         * d10v.h: Likewise.
 493         * d30v.h: Likewise.
 494         * dlx.h: Likewise.
 495         * h8300.h: Likewise.
 496         * hppa.h: Likewise.
 497         * i370.h: Likewise.
 498         * i386.h: Likewise.
 499         * i860.h: Likewise.
 500         * i960.h: Likewise.
 501         * ia64.h: Likewise.
 502         * m68hc11.h: Likewise.
 503         * m68k.h: Likewise.
 504         * m88k.h: Likewise.
 505         * maxq.h: Likewise.
 506         * mips.h: Likewise.
 507         * mmix.h: Likewise.
 508         * mn10200.h: Likewise.
 509         * mn10300.h: Likewise.
 510         * msp430.h: Likewise.
 511         * np1.h: Likewise.
 512         * ns32k.h: Likewise.
 513         * or32.h: Likewise.
 514         * pdp11.h: Likewise.
 515         * pj.h: Likewise.
 516         * pn.h: Likewise.
 517         * ppc.h: Likewise.
 518         * pyr.h: Likewise.
 519         * rx.h: Likewise.
 520         * s390.h: Likewise.
 521         * score-datadep.h: Likewise.
 522         * score-inst.h: Likewise.
 523         * sparc.h: Likewise.
 524         * spu-insns.h: Likewise.
 525         * spu.h: Likewise.
 526         * tic30.h: Likewise.
 527         * tic4x.h: Likewise.
 528         * tic54x.h: Likewise.
 529         * tic80.h: Likewise.
 530         * v850.h: Likewise.
 531         * vax.h: Likewise.
 532
 533 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 534
 535         * tic6x-control-registers.h, tic6x-insn-formats.h,
 536         tic6x-opcode-table.h, tic6x.h: New.
 537
 538 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 539
 540         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 541
 542 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 543
 544         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 545
 546 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * ia64.h (ia64_find_opcode): Remove argument name.
 549         (ia64_find_next_opcode): Likewise.
 550         (ia64_dis_opcode): Likewise.
 551         (ia64_free_opcode): Likewise.
 552         (ia64_find_dependency): Likewise.
 553
 554 2009-11-22  Doug Evans  <dje@sebabeach.org>
 555
 556         * cgen.h: Include bfd_stdint.h.
 557         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 558
 559 2009-11-18  Paul Brook  <paul@codesourcery.com>
 560
 561         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 562
 563 2009-11-17  Paul Brook  <paul@codesourcery.com>
 564         Daniel Jacobowitz  <dan@codesourcery.com>
 565
 566         * arm.h (ARM_EXT_V6_DSP): Define.
 567         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 568         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 569
 570 2009-11-04  DJ Delorie  <dj@redhat.com>
 571
 572         * rx.h (rx_decode_opcode) (mvtipl): Add.
 573         (mvtcp, mvfcp, opecp): Remove.
 574
 575 2009-11-02  Paul Brook  <paul@codesourcery.com>
 576
 577         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 578         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 579         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 580         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 581         FPU_ARCH_NEON_VFP_V4): Define.
 582
 583 2009-10-23  Doug Evans  <dje@sebabeach.org>
 584
 585         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 586         * cgen.h: Update.  Improve multi-inclusion macro name.
 587
 588 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 589
 590         * ppc.h (PPC_OPCODE_476): Define.
 591
 592 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 593
 594         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 595
 596 2009-09-29  DJ Delorie  <dj@redhat.com>
 597
 598         * rx.h: New file.
 599
 600 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 601
 602         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 603
 604 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 605
 606         * ppc.h (PPC_OPCODE_PPCA2): New.
 607
 608 2009-09-05  Martin Thuresson  <martin@mtme.org>
 609
 610         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 611
 612 2009-08-29  Martin Thuresson  <martin@mtme.org>
 613
 614         * tic30.h (template): Rename type template to
 615         insn_template. Updated code to use new name.
 616         * tic54x.h (template): Rename type template to
 617         insn_template.
 618
 619 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 620
 621         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 622
 623 2009-06-11  Anthony Green  <green@moxielogic.com>
 624
 625         * moxie.h (MOXIE_F3_PCREL): Define.
 626         (moxie_form3_opc_info): Grow.
 627
 628 2009-06-06  Anthony Green  <green@moxielogic.com>
 629
 630         * moxie.h (MOXIE_F1_M): Define.
 631
 632 2009-04-15  Anthony Green  <green@moxielogic.com>
 633
 634         * moxie.h: Created.
 635
 636 2009-04-06  DJ Delorie  <dj@redhat.com>
 637
 638         * h8300.h: Add relaxation attributes to MOVA opcodes.
 639
 640 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 641
 642         * ppc.h (ppc_parse_cpu): Declare.
 643
 644 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 645
 646         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 647         and _IMM11 for mbitclr and mbitset.
 648         * score-datadep.h: Update dependency information.
 649
 650 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 651
 652         * ppc.h (PPC_OPCODE_POWER7): New.
 653
 654 2009-02-06  Doug Evans  <dje@google.com>
 655
 656         * i386.h: Add comment regarding sse* insns and prefixes.
 657
 658 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 659
 660         * mips.h (INSN_XLR): Define.
 661         (INSN_CHIP_MASK): Update.
 662         (CPU_XLR): Define.
 663         (OPCODE_IS_MEMBER): Update.
 664         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 665
 666 2009-01-28  Doug Evans  <dje@google.com>
 667
 668         * opcode/i386.h: Add multiple inclusion protection.
 669         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 670         (EDI_REG_NUM): New macros.
 671         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 672         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 673         (REX_PREFIX_P): New macro.
 674
 675 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 676
 677         * ppc.h (struct powerpc_opcode): New field "deprecated".
 678         (PPC_OPCODE_NOPOWER4): Delete.
 679
 680 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 681
 682         * mips.h: Define CPU_R14000, CPU_R16000.
 683         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 684
 685 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 686
 687         * arm.h (FPU_NEON_FP16): New.
 688         (FPU_ARCH_NEON_FP16): New.
 689
 690 2008-11-06  Chao-ying Fu  <fu@mips.com>
 691
 692         * mips.h: Doucument '1' for 5-bit sync type.
 693
 694 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 697         IA64_RS_CR.
 698
 699 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 700
 701         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 702
 703 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 704
 705         * ppc.h (PPC_OPCODE_405): Define.
 706         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 707
 708 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 709
 710         * ppc.h (ppc_cpu_t): New typedef.
 711         (struct powerpc_opcode <flags>): Use it.
 712         (struct powerpc_operand <insert, extract>): Likewise.
 713         (struct powerpc_macro <flags>): Likewise.
 714
 715 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 716
 717         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 718         Update comment before MIPS16 field descriptors to mention MIPS16.
 719         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 720         BBIT.
 721         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 722         New bit masks and shift counts for cins and exts.
 723
 724         * mips.h: Document new field descriptors +Q.
 725         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 726
 727 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 728
 729         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 730         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 731
 732 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 733
 734         * ppc.h: (PPC_OPCODE_E500MC): New.
 735
 736 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         * i386.h (MAX_OPERANDS): Set to 5.
 739         (MAX_MNEM_SIZE): Changed to 20.
 740
 741 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 742
 743         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 744
 745 2008-03-09  Paul Brook  <paul@codesourcery.com>
 746
 747         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 748
 749 2008-03-04  Paul Brook  <paul@codesourcery.com>
 750
 751         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 752         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 753         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 754
 755 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 756             Nick Clifton  <nickc@redhat.com>
 757
 758         PR 3134
 759         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 760         with a 32-bit displacement but without the top bit of the 4th byte
 761         set.
 762
 763 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 764
 765         * cr16.h (cr16_num_optab): Declared.
 766
 767 2008-02-14  Hakan Ardo  <hakan@debian.org>
 768
 769         PR gas/2626
 770         * avr.h (AVR_ISA_2xxe): Define.
 771
 772 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 773
 774         * mips.h: Update copyright.
 775         (INSN_CHIP_MASK): New macro.
 776         (INSN_OCTEON): New macro.
 777         (CPU_OCTEON): New macro.
 778         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 779
 780 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 781
 782         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 783
 784 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 785
 786         * avr.h (AVR_ISA_USB162): Add new opcode set.
 787         (AVR_ISA_AVR3): Likewise.
 788
 789 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 790
 791         * mips.h (INSN_LOONGSON_2E): New.
 792         (INSN_LOONGSON_2F): New.
 793         (CPU_LOONGSON_2E): New.
 794         (CPU_LOONGSON_2F): New.
 795         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 796
 797 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 798
 799         * mips.h (INSN_ISA*): Redefine certain values as an
 800         enumeration.  Update comments.
 801         (mips_isa_table): New.
 802         (ISA_MIPS*): Redefine to match enumeration.
 803         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 804         values.
 805
 806 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 807
 808         * ppc.h (PPC_OPCODE_PPCPS): New.
 809
 810 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 811
 812         * m68k.h: Document j K & E.
 813
 814 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 815
 816         * cr16.h: New file for CR16 target.
 817
 818 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 819
 820         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 821
 822 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 823
 824         * m68k.h (mcfisa_c): New.
 825         (mcfusp, mcf_mask): Adjust.
 826
 827 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 828
 829         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 830         (num_powerpc_operands): Declare.
 831         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 832         (PPC_OPERAND_PLUS1): Define.
 833
 834 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 835
 836         * i386.h (REX_MODE64): Renamed to ...
 837         (REX_W): This.
 838         (REX_EXTX): Renamed to ...
 839         (REX_R): This.
 840         (REX_EXTY): Renamed to ...
 841         (REX_X): This.
 842         (REX_EXTZ): Renamed to ...
 843         (REX_B): This.
 844
 845 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 846
 847         * i386.h: Add entries from config/tc-i386.h and move tables
 848         to opcodes/i386-opc.h.
 849
 850 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 851
 852         * i386.h (FloatDR): Removed.
 853         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 854
 855 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 856
 857         * spu-insns.h: Add soma double-float insns.
 858
 859 2007-02-20  Thiemo Seufer  <ths@mips.com>
 860             Chao-Ying Fu  <fu@mips.com>
 861
 862         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 863         (INSN_DSPR2): Add flag for DSP R2 instructions.
 864         (M_BALIGN): New macro.
 865
 866 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 867
 868         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 869         and Seg3ShortFrom with Shortform.
 870
 871 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 872
 873         PR gas/4027
 874         * i386.h (i386_optab): Put the real "test" before the pseudo
 875         one.
 876
 877 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 878
 879         * m68k.h (m68010up): OR fido_a.
 880
 881 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 882
 883         * m68k.h (fido_a): New.
 884
 885 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 886
 887         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 888         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 889         values.
 890
 891 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 892
 893         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 894
 895 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 896
 897         * score-inst.h (enum score_insn_type): Add Insn_internal.
 898
 899 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 900             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 901             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 902             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 903             Alan Modra  <amodra@bigpond.net.au>
 904
 905         * spu-insns.h: New file.
 906         * spu.h: New file.
 907
 908 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 909
 910         * ppc.h (PPC_OPCODE_CELL): Define.
 911
 912 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 913
 914         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 915         in amdfam10 architecture.
 916
 917 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         * i386.h: Replace CpuMNI with CpuSSSE3.
 920
 921 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 922             Joseph Myers  <joseph@codesourcery.com>
 923             Ian Lance Taylor  <ian@wasabisystems.com>
 924             Ben Elliston  <bje@wasabisystems.com>
 925
 926         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 927
 928 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 929
 930         * score-datadep.h: New file.
 931         * score-inst.h: New file.
 932
 933 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 934
 935         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 936         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 937         movdq2q and movq2dq.
 938
 939 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 940            Michael Meissner             <michael.meissner@amd.com>
 941
 942         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 943
 944 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 945
 946         * i386.h (i386_optab): Add "nop" with memory reference.
 947
 948 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 949
 950         * i386.h (i386_optab): Update comment for 64bit NOP.
 951
 952 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 953             Anton Blanchard  <anton@samba.org>
 954
 955         * ppc.h (PPC_OPCODE_POWER6): Define.
 956         Adjust whitespace.
 957
 958 2006-06-05  Thiemo Seufer  <ths@mips.com>
 959
 960         * mips.h: Improve description of MT flags.
 961
 962 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 963
 964         * m68k.h (mcf_mask): Define.
 965
 966 2006-05-05  Thiemo Seufer  <ths@mips.com>
 967             David Ung  <davidu@mips.com>
 968
 969         * mips.h (enum): Add macro M_CACHE_AB.
 970
 971 2006-05-04  Thiemo Seufer  <ths@mips.com>
 972             Nigel Stephens  <nigel@mips.com>
 973             David Ung  <davidu@mips.com>
 974
 975         * mips.h: Add INSN_SMARTMIPS define.
 976
 977 2006-04-30  Thiemo Seufer  <ths@mips.com>
 978             David Ung  <davidu@mips.com>
 979
 980         * mips.h: Defines udi bits and masks.  Add description of
 981         characters which may appear in the args field of udi
 982         instructions.
 983
 984 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 985
 986         * mips.h: Improve comments describing the bitfield instruction
 987         fields.
 988
 989 2006-04-26  Julian Brown  <julian@codesourcery.com>
 990
 991         * arm.h (FPU_VFP_EXT_V3): Define constant.
 992         (FPU_NEON_EXT_V1): Likewise.
 993         (FPU_VFP_HARD): Update.
 994         (FPU_VFP_V3): Define macro.
 995         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 996
 997 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 998
 999         * avr.h (AVR_ISA_PWMx): New.
1000
1001 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1002
1003         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1004         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1005         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1006         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1007         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1008
1009 2006-03-10  Paul Brook  <paul@codesourcery.com>
1010
1011         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1012
1013 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1014
1015         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1016         first.  Correct mask of bb "B" opcode.
1017
1018 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1019
1020         * i386.h (i386_optab): Support Intel Merom New Instructions.
1021
1022 2006-02-24  Paul Brook  <paul@codesourcery.com>
1023
1024         * arm.h: Add V7 feature bits.
1025
1026 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1027
1028         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1029
1030 2006-01-31  Paul Brook  <paul@codesourcery.com>
1031         Richard Earnshaw <rearnsha@arm.com>
1032
1033         * arm.h: Use ARM_CPU_FEATURE.
1034         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1035         (arm_feature_set): Change to a structure.
1036         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1037         ARM_FEATURE): New macros.
1038
1039 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1040
1041         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1042         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1043         (ADD_PC_INCR_OPCODE): Don't define.
1044
1045 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         PR gas/1874
1048         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1049
1050 2005-11-14  David Ung  <davidu@mips.com>
1051
1052         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1053         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1054         save/restore encoding of the args field.
1055
1056 2005-10-28  Dave Brolley  <brolley@redhat.com>
1057
1058         Contribute the following changes:
1059         2005-02-16  Dave Brolley  <brolley@redhat.com>
1060
1061         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1062         cgen_isa_mask_* to cgen_bitset_*.
1063         * cgen.h: Likewise.
1064
1065         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1066
1067         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1068         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1069         (CGEN_CPU_TABLE): Make isas a ponter.
1070
1071         2003-09-29  Dave Brolley  <brolley@redhat.com>
1072
1073         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1074         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1075         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1076
1077         2002-12-13  Dave Brolley  <brolley@redhat.com>
1078
1079         * cgen.h (symcat.h): #include it.
1080         (cgen-bitset.h): #include it.
1081         (CGEN_ATTR_VALUE_TYPE): Now a union.
1082         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1083         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1084         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1085         * cgen-bitset.h: New file.
1086
1087 2005-09-30  Catherine Moore  <clm@cm00re.com>
1088
1089         * bfin.h: New file.
1090
1091 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1092
1093         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1094         indirect operands.
1095
1096 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1097
1098         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1099         Add FLAG_STRICT to pa10 ftest opcode.
1100
1101 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1102
1103         * hppa.h (pa_opcodes): Remove lha entries.
1104
1105 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1106
1107         * hppa.h (FLAG_STRICT): Revise comment.
1108         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1109         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1110         entries for "fdc".
1111
1112 2005-09-30  Catherine Moore  <clm@cm00re.com>
1113
1114         * bfin.h: New file.
1115
1116 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1117
1118         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1119
1120 2005-09-06  Chao-ying Fu  <fu@mips.com>
1121
1122         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1123         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1124         define.
1125         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1126         (INSN_ASE_MASK): Update to include INSN_MT.
1127         (INSN_MT): New define for MT ASE.
1128
1129 2005-08-25  Chao-ying Fu  <fu@mips.com>
1130
1131         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1132         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1133         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1134         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1135         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1136         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1137         instructions.
1138         (INSN_DSP): New define for DSP ASE.
1139
1140 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1141
1142         * a29k.h: Delete.
1143
1144 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1145
1146         * ppc.h (PPC_OPCODE_E300): Define.
1147
1148 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1149
1150         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1151
1152 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1153
1154         PR gas/336
1155         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1156         and pitlb.
1157
1158 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1159
1160         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1161         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1162         Add movq-s as 64-bit variants of movd-s.
1163
1164 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1165
1166         * hppa.h: Fix punctuation in comment.
1167
1168         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1169         implicit space-register addressing.  Set space-register bits on opcodes
1170         using implicit space-register addressing.  Add various missing pa20
1171         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1172         space-register addressing.  Use "fE" instead of "fe" in various
1173         fstw opcodes.
1174
1175 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1176
1177         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1178
1179 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1180
1181         * i386.h (i386_optab): Support Intel VMX Instructions.
1182
1183 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1184
1185         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1186
1187 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1188
1189         * i386.h (i386_optab): Add new insns.
1190
1191 2005-07-01  Nick Clifton  <nickc@redhat.com>
1192
1193         * sparc.h: Add typedefs to structure declarations.
1194
1195 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1196
1197         PR 1013
1198         * i386.h (i386_optab): Update comments for 64bit addressing on
1199         mov. Allow 64bit addressing for mov and movq.
1200
1201 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1202
1203         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1204         respectively, in various floating-point load and store patterns.
1205
1206 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1207
1208         * hppa.h (FLAG_STRICT): Correct comment.
1209         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1210         PA 2.0 mneumonics when equivalent.  Entries with cache control
1211         completers now require PA 1.1.  Adjust whitespace.
1212
1213 2005-05-19  Anton Blanchard  <anton@samba.org>
1214
1215         * ppc.h (PPC_OPCODE_POWER5): Define.
1216
1217 2005-05-10  Nick Clifton  <nickc@redhat.com>
1218
1219         * Update the address and phone number of the FSF organization in
1220         the GPL notices in the following files:
1221         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1222         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1223         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1224         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1225         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1226         tic54x.h, tic80.h, v850.h, vax.h
1227
1228 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1229
1230         * i386.h (i386_optab): Add ht and hnt.
1231
1232 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1233
1234         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1235         Add xcrypt-ctr.  Provide aliases without hyphens.
1236
1237 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1238
1239         Moved from ../ChangeLog
1240
1241         2005-04-12  Paul Brook  <paul@codesourcery.com>
1242         * m88k.h: Rename psr macros to avoid conflicts.
1243
1244         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1245         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1246         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1247         and ARM_ARCH_V6ZKT2.
1248
1249         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1250         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1251         Remove redundant instruction types.
1252         (struct argument): X_op - new field.
1253         (struct cst4_entry): Remove.
1254         (no_op_insn): Declare.
1255
1256         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1257         * crx.h (enum argtype): Rename types, remove unused types.
1258
1259         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1260         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1261         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1262         (enum operand_type): Rearrange operands, edit comments.
1263         replace us<N> with ui<N> for unsigned immediate.
1264         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1265         displacements (respectively).
1266         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1267         (instruction type): Add NO_TYPE_INS.
1268         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1269         (operand_entry): New field - 'flags'.
1270         (operand flags): New.
1271
1272         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1273         * crx.h (operand_type): Remove redundant types i3, i4,
1274         i5, i8, i12.
1275         Add new unsigned immediate types us3, us4, us5, us16.
1276
1277 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1278
1279         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1280         adjust them accordingly.
1281
1282 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1283
1284         * i386.h (i386_optab): Add rdtscp.
1285
1286 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1289         between memory and segment register. Allow movq for moving between
1290         general-purpose register and segment register.
1291
1292 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1293
1294         PR gas/707
1295         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1296         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1297         fnstsw.
1298
1299 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1300
1301         * m68k.h (m68008, m68ec030, m68882): Remove.
1302         (m68k_mask): New.
1303         (cpu_m68k, cpu_cf): New.
1304         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1305         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1306
1307 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1308
1309         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1310         * cgen.h (enum cgen_parse_operand_type): Add
1311         CGEN_PARSE_OPERAND_SYMBOLIC.
1312
1313 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1314
1315         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1316         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1317         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1318
1319 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1320
1321         * mips.h (struct mips_opcode): Add new pinfo2 member.
1322         (INSN_ALIAS): New define for opcode table entries that are
1323         specific instances of another entry, such as 'move' for an 'or'
1324         with a zero operand.
1325         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1326         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1327
1328 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1329
1330         * mips.h (CPU_RM9000): Define.
1331         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1332
1333 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1334
1335         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1336         to/from test registers are illegal in 64-bit mode. Add missing
1337         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1338         (previously one had to explicitly encode a rex64 prefix). Re-enable
1339         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1340         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1341
1342 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1343
1344         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1345         available only with SSE2. Change the MMX additions introduced by SSE
1346         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1347         instructions by their now designated identifier (since combining i686
1348         and 3DNow! does not really imply 3DNow!A).
1349
1350 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1351
1352         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1353         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1354
1355 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1356             Vineet Sharma      <vineets@noida.hcltech.com>
1357
1358         * maxq.h: New file: Disassembly information for the maxq port.
1359
1360 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1361
1362         * i386.h (i386_optab): Put back "movzb".
1363
1364 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1365
1366         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1367         comments.  Remove member cris_ver_sim.  Add members
1368         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1369         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1370         (struct cris_support_reg, struct cris_cond15): New types.
1371         (cris_conds15): Declare.
1372         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1373         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1374         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1375         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1376         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1377         SIZE_FIELD_UNSIGNED.
1378
1379 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1380
1381         * i386.h (sldx_Suf): Remove.
1382         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1383         (q_FP): Define, implying no REX64.
1384         (x_FP, sl_FP): Imply FloatMF.
1385         (i386_optab): Split reg and mem forms of moving from segment registers
1386         so that the memory forms can ignore the 16-/32-bit operand size
1387         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1388         all non-floating-point instructions. Unite 32- and 64-bit forms of
1389         movsx, movzx, and movd. Adjust floating point operations for the above
1390         changes to the *FP macros. Add DefaultSize to floating point control
1391         insns operating on larger memory ranges. Remove left over comments
1392         hinting at certain insns being Intel-syntax ones where the ones
1393         actually meant are already gone.
1394
1395 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1396
1397         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1398         instruction type.
1399
1400 2004-09-30  Paul Brook  <paul@codesourcery.com>
1401
1402         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1403         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1404
1405 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1406
1407         * avr.h: Add support for
1408         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1409
1410 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1411
1412         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1413
1414 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1415
1416         * msp430.h (msp430_opc): Add new instructions.
1417         (msp430_rcodes): Declare new instructions.
1418         (msp430_hcodes): Likewise..
1419
1420 2004-08-13  Nick Clifton  <nickc@redhat.com>
1421
1422         PR/301
1423         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1424         processors.
1425
1426 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1427
1428         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1429
1430 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1433
1434 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1435
1436         * i386.h: Adjust instruction descriptions to better match the
1437         specification.
1438
1439 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1440
1441         * arm.h: Remove all old content.  Replace with architecture defines
1442         from gas/config/tc-arm.c.
1443
1444 2004-07-09  Andreas Schwab  <schwab@suse.de>
1445
1446         * m68k.h: Fix comment.
1447
1448 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1449
1450         * crx.h: New file.
1451
1452 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1453
1454         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1455
1456 2004-05-24  Peter Barada  <peter@the-baradas.com>
1457
1458         * m68k.h: Add 'size' to m68k_opcode.
1459
1460 2004-05-05  Peter Barada  <peter@the-baradas.com>
1461
1462         * m68k.h: Switch from ColdFire chip name to core variant.
1463
1464 2004-04-22  Peter Barada  <peter@the-baradas.com>
1465
1466         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1467         descriptions for new EMAC cases.
1468         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1469         handle Motorola MAC syntax.
1470         Allow disassembly of ColdFire V4e object files.
1471
1472 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1473
1474         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1475
1476 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1477
1478         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1479
1480 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1481
1482         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1483
1484 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1485
1486         * i386.h (i386_optab): Added xstore/xcrypt insns.
1487
1488 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1489
1490         * h8300.h (32bit ldc/stc): Add relaxing support.
1491
1492 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1493
1494         * h8300.h (BITOP): Pass MEMRELAX flag.
1495
1496 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1497
1498         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1499         except for the H8S.
1500
1501 For older changes see ChangeLog-9103
1502 \f
1503 Local Variables:
1504 mode: change-log
1505 left-margin: 8
1506 fill-column: 74
1507 version-control: never
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