include/opcode/ChangeLog

   1 2007-08-08  Ben Elliston  <bje@au.ibm.com>
   2
   3         * ppc.h (PPC_OPCODE_PPCPS): New.
   4
   5 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
   6
   7         * m68k.h: Document j K & E.
   8
   9 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  10
  11         * cr16.h: New file for CR16 target.
  12
  13 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  14
  15         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  16
  17 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  18
  19         * m68k.h (mcfisa_c): New.
  20         (mcfusp, mcf_mask): Adjust.
  21
  22 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  23
  24         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  25         (num_powerpc_operands): Declare.
  26         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  27         (PPC_OPERAND_PLUS1): Define.
  28
  29 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386.h (REX_MODE64): Renamed to ...
  32         (REX_W): This.
  33         (REX_EXTX): Renamed to ...
  34         (REX_R): This.
  35         (REX_EXTY): Renamed to ...
  36         (REX_X): This.
  37         (REX_EXTZ): Renamed to ...
  38         (REX_B): This.
  39
  40 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  41
  42         * i386.h: Add entries from config/tc-i386.h and move tables
  43         to opcodes/i386-opc.h.
  44
  45 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         * i386.h (FloatDR): Removed.
  48         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  49
  50 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  51
  52         * spu-insns.h: Add soma double-float insns.
  53
  54 2007-02-20  Thiemo Seufer  <ths@mips.com>
  55             Chao-Ying Fu  <fu@mips.com>
  56
  57         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  58         (INSN_DSPR2): Add flag for DSP R2 instructions.
  59         (M_BALIGN): New macro.
  60
  61 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  62
  63         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  64         and Seg3ShortFrom with Shortform.
  65
  66 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         PR gas/4027
  69         * i386.h (i386_optab): Put the real "test" before the pseudo
  70         one.
  71
  72 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  73
  74         * m68k.h (m68010up): OR fido_a.
  75
  76 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  77
  78         * m68k.h (fido_a): New.
  79
  80 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  81
  82         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  83         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  84         values.
  85
  86 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  89
  90 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  91
  92         * score-inst.h (enum score_insn_type): Add Insn_internal.
  93
  94 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  95             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  96             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  97             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  98             Alan Modra  <amodra@bigpond.net.au>
  99
 100         * spu-insns.h: New file.
 101         * spu.h: New file.
 102
 103 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 104
 105         * ppc.h (PPC_OPCODE_CELL): Define.
 106
 107 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 108
 109         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 110         in amdfam10 architecture.
 111
 112 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386.h: Replace CpuMNI with CpuSSSE3.
 115
 116 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 117             Joseph Myers  <joseph@codesourcery.com>
 118             Ian Lance Taylor  <ian@wasabisystems.com>
 119             Ben Elliston  <bje@wasabisystems.com>
 120
 121         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 122
 123 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 124
 125         * score-datadep.h: New file.
 126         * score-inst.h: New file.
 127
 128 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 131         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 132         movdq2q and movq2dq.
 133
 134 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 135            Michael Meissner             <michael.meissner@amd.com>
 136
 137         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 138
 139 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 140
 141         * i386.h (i386_optab): Add "nop" with memory reference.
 142
 143 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 144
 145         * i386.h (i386_optab): Update comment for 64bit NOP.
 146
 147 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 148             Anton Blanchard  <anton@samba.org>
 149
 150         * ppc.h (PPC_OPCODE_POWER6): Define.
 151         Adjust whitespace.
 152
 153 2006-06-05  Thiemo Seufer  <ths@mips.com>
 154
 155         * mips.h: Improve description of MT flags.
 156
 157 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 158
 159         * m68k.h (mcf_mask): Define.
 160
 161 2006-05-05  Thiemo Seufer  <ths@mips.com>
 162             David Ung  <davidu@mips.com>
 163
 164         * mips.h (enum): Add macro M_CACHE_AB.
 165
 166 2006-05-04  Thiemo Seufer  <ths@mips.com>
 167             Nigel Stephens  <nigel@mips.com>
 168             David Ung  <davidu@mips.com>
 169
 170         * mips.h: Add INSN_SMARTMIPS define.
 171
 172 2006-04-30  Thiemo Seufer  <ths@mips.com>
 173             David Ung  <davidu@mips.com>
 174
 175         * mips.h: Defines udi bits and masks.  Add description of
 176         characters which may appear in the args field of udi
 177         instructions.
 178
 179 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 180
 181         * mips.h: Improve comments describing the bitfield instruction
 182         fields.
 183
 184 2006-04-26  Julian Brown  <julian@codesourcery.com>
 185
 186         * arm.h (FPU_VFP_EXT_V3): Define constant.
 187         (FPU_NEON_EXT_V1): Likewise.
 188         (FPU_VFP_HARD): Update.
 189         (FPU_VFP_V3): Define macro.
 190         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 191
 192 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 193
 194         * avr.h (AVR_ISA_PWMx): New.
 195
 196 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 197
 198         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 199         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 200         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 201         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 202         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 203
 204 2006-03-10  Paul Brook  <paul@codesourcery.com>
 205
 206         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 207
 208 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 209
 210         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 211         first.  Correct mask of bb "B" opcode.
 212
 213 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 214
 215         * i386.h (i386_optab): Support Intel Merom New Instructions.
 216
 217 2006-02-24  Paul Brook  <paul@codesourcery.com>
 218
 219         * arm.h: Add V7 feature bits.
 220
 221 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 224
 225 2006-01-31  Paul Brook  <paul@codesourcery.com>
 226         Richard Earnshaw <rearnsha@arm.com>
 227
 228         * arm.h: Use ARM_CPU_FEATURE.
 229         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 230         (arm_feature_set): Change to a structure.
 231         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 232         ARM_FEATURE): New macros.
 233
 234 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 235
 236         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 237         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 238         (ADD_PC_INCR_OPCODE): Don't define.
 239
 240 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         PR gas/1874
 243         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 244
 245 2005-11-14  David Ung  <davidu@mips.com>
 246
 247         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 248         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 249         save/restore encoding of the args field.
 250
 251 2005-10-28  Dave Brolley  <brolley@redhat.com>
 252
 253         Contribute the following changes:
 254         2005-02-16  Dave Brolley  <brolley@redhat.com>
 255
 256         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 257         cgen_isa_mask_* to cgen_bitset_*.
 258         * cgen.h: Likewise.
 259
 260         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 261
 262         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 263         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 264         (CGEN_CPU_TABLE): Make isas a ponter.
 265
 266         2003-09-29  Dave Brolley  <brolley@redhat.com>
 267
 268         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 269         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 270         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 271
 272         2002-12-13  Dave Brolley  <brolley@redhat.com>
 273
 274         * cgen.h (symcat.h): #include it.
 275         (cgen-bitset.h): #include it.
 276         (CGEN_ATTR_VALUE_TYPE): Now a union.
 277         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 278         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 279         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 280         * cgen-bitset.h: New file.
 281
 282 2005-09-30  Catherine Moore  <clm@cm00re.com>
 283
 284         * bfin.h: New file.
 285
 286 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 287
 288         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 289         indirect operands.
 290
 291 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 292
 293         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 294         Add FLAG_STRICT to pa10 ftest opcode.
 295
 296 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 297
 298         * hppa.h (pa_opcodes): Remove lha entries.
 299
 300 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 301
 302         * hppa.h (FLAG_STRICT): Revise comment.
 303         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 304         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 305         entries for "fdc".
 306
 307 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 308
 309         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 310
 311 2005-09-06  Chao-ying Fu  <fu@mips.com>
 312
 313         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 314         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 315         define.
 316         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 317         (INSN_ASE_MASK): Update to include INSN_MT.
 318         (INSN_MT): New define for MT ASE.
 319
 320 2005-08-25  Chao-ying Fu  <fu@mips.com>
 321
 322         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 323         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 324         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 325         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 326         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 327         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 328         instructions.
 329         (INSN_DSP): New define for DSP ASE.
 330
 331 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 332
 333         * a29k.h: Delete.
 334
 335 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 336
 337         * ppc.h (PPC_OPCODE_E300): Define.
 338
 339 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 340
 341         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 342
 343 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 344
 345         PR gas/336
 346         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 347         and pitlb.
 348
 349 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 350
 351         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 352         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 353         Add movq-s as 64-bit variants of movd-s.
 354
 355 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 356
 357         * hppa.h: Fix punctuation in comment.
 358
 359         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 360         implicit space-register addressing.  Set space-register bits on opcodes
 361         using implicit space-register addressing.  Add various missing pa20
 362         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 363         space-register addressing.  Use "fE" instead of "fe" in various
 364         fstw opcodes.
 365
 366 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 367
 368         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 369
 370 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 371
 372         * i386.h (i386_optab): Support Intel VMX Instructions.
 373
 374 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 375
 376         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 377
 378 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 379
 380         * i386.h (i386_optab): Add new insns.
 381
 382 2005-07-01  Nick Clifton  <nickc@redhat.com>
 383
 384         * sparc.h: Add typedefs to structure declarations.
 385
 386 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         PR 1013
 389         * i386.h (i386_optab): Update comments for 64bit addressing on
 390         mov. Allow 64bit addressing for mov and movq.
 391
 392 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 393
 394         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 395         respectively, in various floating-point load and store patterns.
 396
 397 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 398
 399         * hppa.h (FLAG_STRICT): Correct comment.
 400         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 401         PA 2.0 mneumonics when equivalent.  Entries with cache control
 402         completers now require PA 1.1.  Adjust whitespace.
 403
 404 2005-05-19  Anton Blanchard  <anton@samba.org>
 405
 406         * ppc.h (PPC_OPCODE_POWER5): Define.
 407
 408 2005-05-10  Nick Clifton  <nickc@redhat.com>
 409
 410         * Update the address and phone number of the FSF organization in
 411         the GPL notices in the following files:
 412         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 413         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 414         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 415         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 416         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 417         tic54x.h, tic80.h, v850.h, vax.h
 418
 419 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 420
 421         * i386.h (i386_optab): Add ht and hnt.
 422
 423 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 424
 425         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 426         Add xcrypt-ctr.  Provide aliases without hyphens.
 427
 428 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 429
 430         Moved from ../ChangeLog
 431
 432         2005-04-12  Paul Brook  <paul@codesourcery.com>
 433         * m88k.h: Rename psr macros to avoid conflicts.
 434
 435         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 436         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 437         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 438         and ARM_ARCH_V6ZKT2.
 439
 440         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 441         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 442         Remove redundant instruction types.
 443         (struct argument): X_op - new field.
 444         (struct cst4_entry): Remove.
 445         (no_op_insn): Declare.
 446
 447         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 448         * crx.h (enum argtype): Rename types, remove unused types.
 449
 450         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 451         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 452         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 453         (enum operand_type): Rearrange operands, edit comments.
 454         replace us<N> with ui<N> for unsigned immediate.
 455         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 456         displacements (respectively).
 457         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 458         (instruction type): Add NO_TYPE_INS.
 459         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 460         (operand_entry): New field - 'flags'.
 461         (operand flags): New.
 462
 463         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 464         * crx.h (operand_type): Remove redundant types i3, i4,
 465         i5, i8, i12.
 466         Add new unsigned immediate types us3, us4, us5, us16.
 467
 468 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 469
 470         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 471         adjust them accordingly.
 472
 473 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 474
 475         * i386.h (i386_optab): Add rdtscp.
 476
 477 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 478
 479         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 480         between memory and segment register. Allow movq for moving between
 481         general-purpose register and segment register.
 482
 483 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 484
 485         PR gas/707
 486         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 487         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 488         fnstsw.
 489
 490 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 491
 492         * m68k.h (m68008, m68ec030, m68882): Remove.
 493         (m68k_mask): New.
 494         (cpu_m68k, cpu_cf): New.
 495         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 496         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 497
 498 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 499
 500         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 501         * cgen.h (enum cgen_parse_operand_type): Add
 502         CGEN_PARSE_OPERAND_SYMBOLIC.
 503
 504 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 505
 506         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 507         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 508         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 509
 510 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 511
 512         * mips.h (struct mips_opcode): Add new pinfo2 member.
 513         (INSN_ALIAS): New define for opcode table entries that are
 514         specific instances of another entry, such as 'move' for an 'or'
 515         with a zero operand.
 516         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 517         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 518
 519 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 520
 521         * mips.h (CPU_RM9000): Define.
 522         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 523
 524 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 525
 526         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 527         to/from test registers are illegal in 64-bit mode. Add missing
 528         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 529         (previously one had to explicitly encode a rex64 prefix). Re-enable
 530         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 531         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 532
 533 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 534
 535         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 536         available only with SSE2. Change the MMX additions introduced by SSE
 537         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 538         instructions by their now designated identifier (since combining i686
 539         and 3DNow! does not really imply 3DNow!A).
 540
 541 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 544         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 545
 546 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 547             Vineet Sharma      <vineets@noida.hcltech.com>
 548
 549         * maxq.h: New file: Disassembly information for the maxq port.
 550
 551 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         * i386.h (i386_optab): Put back "movzb".
 554
 555 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 556
 557         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 558         comments.  Remove member cris_ver_sim.  Add members
 559         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 560         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 561         (struct cris_support_reg, struct cris_cond15): New types.
 562         (cris_conds15): Declare.
 563         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 564         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 565         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 566         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 567         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 568         SIZE_FIELD_UNSIGNED.
 569
 570 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 571
 572         * i386.h (sldx_Suf): Remove.
 573         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 574         (q_FP): Define, implying no REX64.
 575         (x_FP, sl_FP): Imply FloatMF.
 576         (i386_optab): Split reg and mem forms of moving from segment registers
 577         so that the memory forms can ignore the 16-/32-bit operand size
 578         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 579         all non-floating-point instructions. Unite 32- and 64-bit forms of
 580         movsx, movzx, and movd. Adjust floating point operations for the above
 581         changes to the *FP macros. Add DefaultSize to floating point control
 582         insns operating on larger memory ranges. Remove left over comments
 583         hinting at certain insns being Intel-syntax ones where the ones
 584         actually meant are already gone.
 585
 586 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 587
 588         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 589         instruction type.
 590
 591 2004-09-30  Paul Brook  <paul@codesourcery.com>
 592
 593         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 594         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 595
 596 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 597
 598         * avr.h: Add support for
 599         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 600
 601 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 602
 603         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 604
 605 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 606
 607         * msp430.h (msp430_opc): Add new instructions.
 608         (msp430_rcodes): Declare new instructions.
 609         (msp430_hcodes): Likewise..
 610
 611 2004-08-13  Nick Clifton  <nickc@redhat.com>
 612
 613         PR/301
 614         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 615         processors.
 616
 617 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 618
 619         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 620
 621 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 622
 623         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 624
 625 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 626
 627         * i386.h: Adjust instruction descriptions to better match the
 628         specification.
 629
 630 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 631
 632         * arm.h: Remove all old content.  Replace with architecture defines
 633         from gas/config/tc-arm.c.
 634
 635 2004-07-09  Andreas Schwab  <schwab@suse.de>
 636
 637         * m68k.h: Fix comment.
 638
 639 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 640
 641         * crx.h: New file.
 642
 643 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 644
 645         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 646
 647 2004-05-24  Peter Barada  <peter@the-baradas.com>
 648
 649         * m68k.h: Add 'size' to m68k_opcode.
 650
 651 2004-05-05  Peter Barada  <peter@the-baradas.com>
 652
 653         * m68k.h: Switch from ColdFire chip name to core variant.
 654
 655 2004-04-22  Peter Barada  <peter@the-baradas.com>
 656
 657         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 658         descriptions for new EMAC cases.
 659         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 660         handle Motorola MAC syntax.
 661         Allow disassembly of ColdFire V4e object files.
 662
 663 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 664
 665         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 666
 667 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 668
 669         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 670
 671 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 672
 673         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 674
 675 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 676
 677         * i386.h (i386_optab): Added xstore/xcrypt insns.
 678
 679 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 680
 681         * h8300.h (32bit ldc/stc): Add relaxing support.
 682
 683 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 684
 685         * h8300.h (BITOP): Pass MEMRELAX flag.
 686
 687 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 688
 689         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 690         except for the H8S.
 691
 692 For older changes see ChangeLog-9103
 693 \f
 694 Local Variables:
 695 mode: change-log
 696 left-margin: 8
 697 fill-column: 74
 698 version-control: never
 699 End: