include/opcode/ChangeLog

   1 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Put back "movzb".
   4
   5 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
   6
   7         * cris.h (enum cris_insn_version_usage): Tweak formatting and
   8         comments.  Remove member cris_ver_sim.  Add members
   9         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  10         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  11         (struct cris_support_reg, struct cris_cond15): New types.
  12         (cris_conds15): Declare.
  13         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  14         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  15         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  16         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  17         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  18         SIZE_FIELD_UNSIGNED.
  19
  20 2004-11-04 Jan Beulich <jbeulich@novell.com>
  21
  22         * i386.h (sldx_Suf): Remove.
  23         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  24         (q_FP): Define, implying no REX64.
  25         (x_FP, sl_FP): Imply FloatMF.
  26         (i386_optab): Split reg and mem forms of moving from segment registers
  27         so that the memory forms can ignore the 16-/32-bit operand size
  28         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  29         all non-floating-point instructions. Unite 32- and 64-bit forms of
  30         movsx, movzx, and movd. Adjust floating point operations for the above
  31         changes to the *FP macros. Add DefaultSize to floating point control
  32         insns operating on larger memory ranges. Remove left over comments
  33         hinting at certain insns being Intel-syntax ones where the ones
  34         actually meant are already gone.
  35
  36 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  37
  38         * crx.h: Add COPS_REG_INS - Coprocessor Special register
  39         instruction type.
  40
  41 2004-09-30  Paul Brook  <paul@codesourcery.com>
  42
  43         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
  44         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
  45
  46 2004-09-11  Theodore A. Roth  <troth@openavr.org>
  47
  48         * avr.h: Add support for
  49         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
  50
  51 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
  52
  53         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
  54
  55 2004-08-24  Dmitry Diky  <diwil@spec.ru>
  56
  57         * msp430.h (msp430_opc): Add new instructions.
  58         (msp430_rcodes): Declare new instructions.
  59         (msp430_hcodes): Likewise..
  60
  61 2004-08-13  Nick Clifton  <nickc@redhat.com>
  62
  63         PR/301
  64         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
  65         processors.
  66
  67 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
  68
  69         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
  70
  71 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
  74
  75 2004-07-21  Jan Beulich  <jbeulich@novell.com>
  76
  77         * i386.h: Adjust instruction descriptions to better match the
  78         specification.
  79
  80 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
  81
  82         * arm.h: Remove all old content.  Replace with architecture defines
  83         from gas/config/tc-arm.c.
  84
  85 2004-07-09  Andreas Schwab  <schwab@suse.de>
  86
  87         * m68k.h: Fix comment.
  88
  89 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  90
  91         * crx.h: New file.
  92
  93 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  94
  95         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
  96
  97 2004-05-24  Peter Barada  <peter@the-baradas.com>
  98
  99         * m68k.h: Add 'size' to m68k_opcode.
 100
 101 2004-05-05  Peter Barada  <peter@the-baradas.com>
 102
 103         * m68k.h: Switch from ColdFire chip name to core variant.
 104
 105 2004-04-22  Peter Barada  <peter@the-baradas.com>
 106
 107         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 108         descriptions for new EMAC cases.
 109         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 110         handle Motorola MAC syntax.
 111         Allow disassembly of ColdFire V4e object files.
 112
 113 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 114
 115         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 116
 117 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 118
 119         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 120
 121 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 122
 123         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 124
 125 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 126
 127         * i386.h (i386_optab): Added xstore/xcrypt insns.
 128
 129 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 130
 131         * h8300.h (32bit ldc/stc): Add relaxing support.
 132
 133 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 134
 135         * h8300.h (BITOP): Pass MEMRELAX flag.
 136
 137 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 138
 139         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 140         except for the H8S.
 141
 142 For older changes see ChangeLog-9103
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