1 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
3 * nios2.h (enum iw_format_type): New.
4 (struct nios2_opcode): Update comments. Add size and format fields.
5 (NIOS2_INSN_OPTARG): New.
6 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
7 (struct nios2_reg): Add regtype field.
8 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
9 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
10 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
11 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
12 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
13 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
14 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
15 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
16 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
17 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
18 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
19 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
20 (OP_MASK_OP, OP_SH_OP): Delete.
21 (OP_MASK_IOP, OP_SH_IOP): Delete.
22 (OP_MASK_IRD, OP_SH_IRD): Delete.
23 (OP_MASK_IRT, OP_SH_IRT): Delete.
24 (OP_MASK_IRS, OP_SH_IRS): Delete.
25 (OP_MASK_ROP, OP_SH_ROP): Delete.
26 (OP_MASK_RRD, OP_SH_RRD): Delete.
27 (OP_MASK_RRT, OP_SH_RRT): Delete.
28 (OP_MASK_RRS, OP_SH_RRS): Delete.
29 (OP_MASK_JOP, OP_SH_JOP): Delete.
30 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
31 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
32 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
33 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
34 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
35 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
36 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
37 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
38 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
39 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
40 (OP_MASK_<insn>, OP_MASK): Delete.
41 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
42 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
43 Include nios2r1.h to define new instruction opcode constants
45 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
46 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
47 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
48 (NUMOPCODES, NUMREGISTERS): Delete.
49 * nios2r1.h: New file.
51 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
53 * sparc.h (HWCAP2_VIS3B): Documentation improved.
55 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
57 * sparc.h (sparc_opcode): new field `hwcaps2'.
58 (HWCAP2_FJATHPLUS): New define.
59 (HWCAP2_VIS3B): Likewise.
60 (HWCAP2_ADP): Likewise.
61 (HWCAP2_SPARC5): Likewise.
62 (HWCAP2_MWAIT): Likewise.
63 (HWCAP2_XMPMUL): Likewise.
64 (HWCAP2_XMONT): Likewise.
65 (HWCAP2_NSEC): Likewise.
66 (HWCAP2_FJATHHPC): Likewise.
67 (HWCAP2_FJDES): Likewise.
68 (HWCAP2_FJAES): Likewise.
69 Document the new operand kind `{', corresponding to the mcdper
70 ancillary state register.
71 Document the new operand kind }, which represents frsd floating
72 point registers (double precision) which must be the same than
73 frs1 in its containing instruction.
75 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
77 * nds32.h: Add new opcode declaration.
79 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
80 Matthew Fortune <matthew.fortune@imgtec.com>
82 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
83 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
84 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
85 +I, +O, +R, +:, +\, +", +;
86 (mips_check_prev_operand): New struct.
87 (INSN2_FORBIDDEN_SLOT): New define.
88 (INSN_ISA32R6): New define.
89 (INSN_ISA64R6): New define.
90 (INSN_UPTO32R6): New define.
91 (INSN_UPTO64R6): New define.
92 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
93 (ISA_MIPS32R6): New define.
94 (ISA_MIPS64R6): New define.
95 (CPU_MIPS32R6): New define.
96 (CPU_MIPS64R6): New define.
97 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
99 2014-09-03 Jiong Wang <jiong.wang@arm.com>
101 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
102 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
103 (aarch64_insn_class): Add lse_atomic.
104 (F_LSE_SZ): New field added.
105 (opcode_has_special_coder): Recognize F_LSE_SZ.
107 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
109 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
112 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
114 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
115 (INSN_LOAD_COPROC): New define.
116 (INSN_COPROC_MOVE_DELAY): Rename to...
117 (INSN_COPROC_MOVE): New define.
119 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
120 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
121 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
122 Soundararajan <Sounderarajan.D@atmel.com>
124 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
125 (AVR_ISA_2xxxa): Define ISA without LPM.
126 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
127 Add doc for contraint used in 16 bit lds/sts.
128 Adjust ISA group for icall, ijmp, pop and push.
129 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
131 2014-05-19 Nick Clifton <nickc@redhat.com>
133 * msp430.h (struct msp430_operand_s): Add vshift field.
135 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
137 * mips.h (INSN_ISA_MASK): Updated.
138 (INSN_ISA32R3): New define.
139 (INSN_ISA32R5): New define.
140 (INSN_ISA64R3): New define.
141 (INSN_ISA64R5): New define.
142 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
143 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
144 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
146 (INSN_UPTO32R3): New define.
147 (INSN_UPTO32R5): New define.
148 (INSN_UPTO64R3): New define.
149 (INSN_UPTO64R5): New define.
150 (ISA_MIPS32R3): New define.
151 (ISA_MIPS32R5): New define.
152 (ISA_MIPS64R3): New define.
153 (ISA_MIPS64R5): New define.
154 (CPU_MIPS32R3): New define.
155 (CPU_MIPS32R5): New define.
156 (CPU_MIPS64R3): New define.
157 (CPU_MIPS64R5): New define.
159 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
161 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
163 2014-04-22 Christian Svensson <blue@cmd.nu>
167 2014-03-05 Alan Modra <amodra@gmail.com>
169 Update copyright years.
171 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
173 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
176 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
177 Wei-Cheng Wang <cole945@gmail.com>
179 * nds32.h: New file for Andes NDS32.
181 2013-12-07 Mike Frysinger <vapier@gentoo.org>
183 * bfin.h: Remove +x file mode.
185 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
187 * aarch64.h (aarch64_pstatefields): Change element type to
190 2013-11-18 Renlin Li <Renlin.Li@arm.com>
192 * arm.h (ARM_AEXT_V7VE): New define.
193 (ARM_ARCH_V7VE): New define.
194 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
196 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
200 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
202 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
203 (aarch64_sys_reg_writeonly_p): Ditto.
205 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
207 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
208 (aarch64_sys_reg_writeonly_p): Ditto.
210 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
212 * aarch64.h (aarch64_sys_reg): New typedef.
213 (aarch64_sys_regs): Change to define with the new type.
214 (aarch64_sys_reg_deprecated_p): Declare.
216 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
218 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
219 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
221 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
223 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
224 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
225 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
226 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
227 For MIPS, update extension character sequences after +.
228 (ASE_MSA): New define.
229 (ASE_MSA64): New define.
230 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
231 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
232 For microMIPS, update extension character sequences after +.
234 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
239 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
241 * mips.h: Remove references to "+I" and imm2_expr.
243 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
245 * mips.h (M_DEXT, M_DINS): Delete.
247 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
249 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
250 (mips_optional_operand_p): New function.
252 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
253 Richard Sandiford <rdsandiford@googlemail.com>
255 * mips.h: Document new VU0 operand characters.
256 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
257 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
258 (OP_REG_R5900_ACC): New mips_reg_operand_types.
259 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
260 (mips_vu0_channel_mask): Declare.
262 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
264 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
265 (mips_int_operand_min, mips_int_operand_max): New functions.
266 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
268 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
270 * mips.h (mips_decode_reg_operand): New function.
271 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
272 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
273 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
275 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
276 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
277 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
278 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
279 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
280 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
281 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
282 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
283 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
284 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
285 macros to cover the gaps.
286 (INSN2_MOD_SP): Replace with...
287 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
288 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
289 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
290 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
291 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
294 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
296 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
297 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
298 (MIPS16_INSN_COND_BRANCH): Delete.
300 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
301 Kirill Yukhin <kirill.yukhin@intel.com>
302 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
304 * i386.h (BND_PREFIX_OPCODE): New.
306 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
308 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
309 OP_SAVE_RESTORE_LIST.
310 (decode_mips16_operand): Declare.
312 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
314 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
315 (mips_operand, mips_int_operand, mips_mapped_int_operand)
316 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
317 (mips_pcrel_operand): New structures.
318 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
319 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
320 (decode_mips_operand, decode_micromips_operand): Declare.
322 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
324 * mips.h: Document MIPS16 "I" opcode.
326 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
328 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
329 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
330 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
331 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
332 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
333 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
334 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
335 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
336 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
337 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
338 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
339 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
340 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
342 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
343 (M_USD_AB): ...these.
345 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
347 * mips.h: Remove documentation of "[" and "]". Update documentation
348 of "k" and the MDMX formats.
350 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
352 * mips.h: Update documentation of "+s" and "+S".
354 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
356 * mips.h: Document "+i".
358 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
360 * mips.h: Remove "mi" documentation. Update "mh" documentation.
361 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
363 (INSN2_WRITE_GPR_MHI): Rename to...
364 (INSN2_WRITE_GPR_MH): ...this.
366 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
368 * mips.h: Remove documentation of "+D" and "+T".
370 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
372 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
373 Use "source" rather than "destination" for microMIPS "G".
375 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
377 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
380 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
382 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
384 2013-06-17 Catherine Moore <clm@codesourcery.com>
385 Maciej W. Rozycki <macro@codesourcery.com>
386 Chao-Ying Fu <fu@mips.com>
388 * mips.h (OP_SH_EVAOFFSET): Define.
389 (OP_MASK_EVAOFFSET): Define.
390 (INSN_ASE_MASK): Delete.
392 (M_CACHEE_AB, M_CACHEE_OB): New.
393 (M_LBE_OB, M_LBE_AB): New.
394 (M_LBUE_OB, M_LBUE_AB): New.
395 (M_LHE_OB, M_LHE_AB): New.
396 (M_LHUE_OB, M_LHUE_AB): New.
397 (M_LLE_AB, M_LLE_OB): New.
398 (M_LWE_OB, M_LWE_AB): New.
399 (M_LWLE_AB, M_LWLE_OB): New.
400 (M_LWRE_AB, M_LWRE_OB): New.
401 (M_PREFE_AB, M_PREFE_OB): New.
402 (M_SCE_AB, M_SCE_OB): New.
403 (M_SBE_OB, M_SBE_AB): New.
404 (M_SHE_OB, M_SHE_AB): New.
405 (M_SWE_OB, M_SWE_AB): New.
406 (M_SWLE_AB, M_SWLE_OB): New.
407 (M_SWRE_AB, M_SWRE_OB): New.
408 (MICROMIPSOP_SH_EVAOFFSET): Define.
409 (MICROMIPSOP_MASK_EVAOFFSET): Define.
411 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
413 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
415 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
417 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
419 2013-05-09 Andrew Pinski <apinski@cavium.com>
421 * mips.h (OP_MASK_CODE10): Correct definition.
422 (OP_SH_CODE10): Likewise.
423 Add a comment that "+J" is used now for OP_*CODE10.
424 (INSN_ASE_MASK): Update.
425 (INSN_VIRT): New macro.
426 (INSN_VIRT64): New macro
428 2013-05-02 Nick Clifton <nickc@redhat.com>
430 * msp430.h: Add patterns for MSP430X instructions.
432 2013-04-06 David S. Miller <davem@davemloft.net>
434 * sparc.h (F_PREFERRED): Define.
435 (F_PREF_ALIAS): Define.
437 2013-04-03 Nick Clifton <nickc@redhat.com>
439 * v850.h (V850_INVERSE_PCREL): Define.
441 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
444 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
446 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
449 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
451 * tic6xc-opcode-table.h: Add 16-bit insns.
452 * tic6x.h: Add support for 16-bit insns.
454 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
456 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
457 and mov.b/w/l Rs,@(d:32,ERd).
459 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
462 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
463 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
464 tic6x_operand_xregpair operand coding type.
465 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
466 opcode field, usu ORXREGD1324 for the src2 operand and remove the
469 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
472 * tic6x.h (enum tic6x_coding_method): Add
473 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
474 separately the msb and lsb of a register pair. This is needed to
475 encode the opcodes in the same way as TI assembler does.
476 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
477 and rsqrdp opcodes to use the new field coding types.
479 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
481 * arm.h (CRC_EXT_ARMV8): New constant.
482 (ARCH_CRC_ARMV8): New macro.
484 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
486 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
488 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
489 Andrew Jenner <andrew@codesourcery.com>
491 Based on patches from Altera Corporation.
495 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
497 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
499 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
502 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
504 2013-01-24 Nick Clifton <nickc@redhat.com>
506 * v850.h: Add e3v5 support.
508 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
510 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
512 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
514 * ppc.h (PPC_OPCODE_POWER8): New define.
515 (PPC_OPCODE_HTM): Likewise.
517 2013-01-10 Will Newton <will.newton@imgtec.com>
521 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
523 * cr16.h (make_instruction): Rename to cr16_make_instruction.
524 (match_opcode): Rename to cr16_match_opcode.
526 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
528 * mips.h: Add support for r5900 instructions including lq and sq.
530 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
532 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
533 (make_instruction,match_opcode): Added function prototypes.
534 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
536 2012-11-23 Alan Modra <amodra@gmail.com>
538 * ppc.h (ppc_parse_cpu): Update prototype.
540 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
542 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
543 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
545 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
547 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
549 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
551 * ia64.h (ia64_opnd): Add new operand types.
553 2012-08-21 David S. Miller <davem@davemloft.net>
555 * sparc.h (F3F4): New macro.
557 2012-08-13 Ian Bolton <ian.bolton@arm.com>
558 Laurent Desnogues <laurent.desnogues@arm.com>
559 Jim MacArthur <jim.macarthur@arm.com>
560 Marcus Shawcroft <marcus.shawcroft@arm.com>
561 Nigel Stephens <nigel.stephens@arm.com>
562 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
563 Richard Earnshaw <rearnsha@arm.com>
564 Sofiane Naci <sofiane.naci@arm.com>
565 Tejas Belagod <tejas.belagod@arm.com>
566 Yufeng Zhang <yufeng.zhang@arm.com>
568 * aarch64.h: New file.
570 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
571 Maciej W. Rozycki <macro@codesourcery.com>
573 * mips.h (mips_opcode): Add the exclusions field.
574 (OPCODE_IS_MEMBER): Remove macro.
575 (cpu_is_member): New inline function.
576 (opcode_is_member): Likewise.
578 2012-07-31 Chao-Ying Fu <fu@mips.com>
579 Catherine Moore <clm@codesourcery.com>
580 Maciej W. Rozycki <macro@codesourcery.com>
582 * mips.h: Document microMIPS DSP ASE usage.
583 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
584 microMIPS DSP ASE support.
585 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
586 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
587 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
588 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
589 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
590 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
591 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
593 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
595 * mips.h: Fix a typo in description.
597 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
599 * avr.h: (AVR_ISA_XCH): New define.
600 (AVR_ISA_XMEGA): Use it.
601 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
603 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
605 * m68hc11.h: Add XGate definitions.
606 (struct m68hc11_opcode): Add xg_mask field.
608 2012-05-14 Catherine Moore <clm@codesourcery.com>
609 Maciej W. Rozycki <macro@codesourcery.com>
610 Rhonda Wittels <rhonda@codesourcery.com>
612 * ppc.h (PPC_OPCODE_VLE): New definition.
613 (PPC_OP_SA): New macro.
614 (PPC_OP_SE_VLE): New macro.
615 (PPC_OP): Use a variable shift amount.
616 (powerpc_operand): Update comments.
617 (PPC_OPSHIFT_INV): New macro.
618 (PPC_OPERAND_CR): Replace with...
619 (PPC_OPERAND_CR_BIT): ...this and
620 (PPC_OPERAND_CR_REG): ...this.
623 2012-05-03 Sean Keys <skeys@ipdatasys.com>
625 * xgate.h: Header file for XGATE assembler.
627 2012-04-27 David S. Miller <davem@davemloft.net>
629 * sparc.h: Document new arg code' )' for crypto RS3
632 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
633 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
634 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
635 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
636 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
637 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
638 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
639 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
640 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
641 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
642 HWCAP_CBCOND, HWCAP_CRC32): New defines.
644 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
646 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
648 2012-02-27 Alan Modra <amodra@gmail.com>
650 * crx.h (cst4_map): Update declaration.
652 2012-02-25 Walter Lee <walt@tilera.com>
654 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
656 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
657 TILEPRO_OPC_LW_TLS_SN.
659 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
661 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
662 (XRELEASE_PREFIX_OPCODE): Likewise.
664 2011-12-08 Andrew Pinski <apinski@cavium.com>
665 Adam Nemet <anemet@caviumnetworks.com>
667 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
668 (INSN_OCTEON2): New macro.
669 (CPU_OCTEON2): New macro.
670 (OPCODE_IS_MEMBER): Add Octeon2.
672 2011-11-29 Andrew Pinski <apinski@cavium.com>
674 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
675 (INSN_OCTEONP): New macro.
676 (CPU_OCTEONP): New macro.
677 (OPCODE_IS_MEMBER): Add Octeon+.
678 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
680 2011-11-01 DJ Delorie <dj@redhat.com>
684 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
686 * mips.h: Fix a typo in description.
688 2011-09-21 David S. Miller <davem@davemloft.net>
690 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
691 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
692 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
693 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
695 2011-08-09 Chao-ying Fu <fu@mips.com>
696 Maciej W. Rozycki <macro@codesourcery.com>
698 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
699 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
700 (INSN_ASE_MASK): Add the MCU bit.
701 (INSN_MCU): New macro.
702 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
703 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
705 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
707 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
708 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
709 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
710 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
711 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
712 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
713 (INSN2_READ_GPR_MMN): Likewise.
714 (INSN2_READ_FPR_D): Change the bit used.
715 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
716 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
717 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
718 (INSN2_COND_BRANCH): Likewise.
719 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
720 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
721 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
722 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
723 (INSN2_MOD_GPR_MN): Likewise.
725 2011-08-05 David S. Miller <davem@davemloft.net>
727 * sparc.h: Document new format codes '4', '5', and '('.
728 (OPF_LOW4, RS3): New macros.
730 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
732 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
733 order of flags documented.
735 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
737 * mips.h: Clarify the description of microMIPS instruction
739 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
741 2011-07-24 Chao-ying Fu <fu@mips.com>
742 Maciej W. Rozycki <macro@codesourcery.com>
744 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
745 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
746 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
747 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
748 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
749 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
750 (OP_MASK_RS3, OP_SH_RS3): Likewise.
751 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
752 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
753 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
754 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
755 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
756 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
757 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
758 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
759 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
760 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
761 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
762 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
763 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
764 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
765 (INSN_WRITE_GPR_S): New macro.
766 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
767 (INSN2_READ_FPR_D): Likewise.
768 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
769 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
770 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
771 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
772 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
773 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
774 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
775 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
776 (CPU_MICROMIPS): New macro.
777 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
778 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
779 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
780 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
781 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
782 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
783 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
784 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
785 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
786 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
787 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
788 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
789 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
790 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
791 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
792 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
793 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
794 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
795 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
796 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
797 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
798 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
799 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
800 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
801 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
802 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
803 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
804 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
805 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
806 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
807 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
808 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
809 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
810 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
811 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
812 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
813 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
814 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
815 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
816 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
817 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
818 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
819 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
820 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
821 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
822 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
823 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
824 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
825 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
826 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
827 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
828 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
829 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
830 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
831 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
832 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
833 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
834 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
835 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
836 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
837 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
838 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
839 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
840 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
841 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
842 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
843 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
844 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
845 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
846 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
847 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
848 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
849 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
850 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
851 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
852 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
853 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
854 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
855 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
856 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
857 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
858 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
859 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
860 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
861 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
862 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
863 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
864 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
865 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
866 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
867 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
868 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
869 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
870 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
871 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
872 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
873 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
874 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
875 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
876 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
877 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
878 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
879 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
880 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
881 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
882 (micromips_opcodes): New declaration.
883 (bfd_micromips_num_opcodes): Likewise.
885 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
887 * mips.h (INSN_TRAP): Rename to...
888 (INSN_NO_DELAY_SLOT): ... this.
889 (INSN_SYNC): Remove macro.
891 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
893 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
894 a duplicate of AVR_ISA_SPM.
896 2011-07-01 Nick Clifton <nickc@redhat.com>
898 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
900 2011-06-18 Robin Getz <robin.getz@analog.com>
902 * bfin.h (is_macmod_signed): New func
904 2011-06-18 Mike Frysinger <vapier@gentoo.org>
906 * bfin.h (is_macmod_pmove): Add missing space before func args.
907 (is_macmod_hmove): Likewise.
909 2011-06-13 Walter Lee <walt@tilera.com>
911 * tilegx.h: New file.
912 * tilepro.h: New file.
914 2011-05-31 Paul Brook <paul@codesourcery.com>
916 * arm.h (ARM_ARCH_V7R_IDIV): Define.
918 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
920 * s390.h: Replace S390_OPERAND_REG_EVEN with
921 S390_OPERAND_REG_PAIR.
923 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
925 * s390.h: Add S390_OPCODE_REG_EVEN flag.
927 2011-04-18 Julian Brown <julian@codesourcery.com>
929 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
931 2011-04-11 Dan McDonald <dan@wellkeeper.com>
934 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
936 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
938 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
939 New instruction set flags.
940 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
942 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
944 * mips.h (M_PREF_AB): New enum value.
946 2011-02-12 Mike Frysinger <vapier@gentoo.org>
948 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
950 (is_macmod_pmove, is_macmod_hmove): New functions.
952 2011-02-11 Mike Frysinger <vapier@gentoo.org>
954 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
956 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
958 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
959 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
961 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
964 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
967 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
970 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
972 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
974 * mips.h: Update commentary after last commit.
976 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
978 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
979 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
980 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
982 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
984 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
986 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
988 * mips.h: Fix previous commit.
990 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
992 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
993 (INSN_LOONGSON_3A): Clear bit 31.
995 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
998 * arm.h (ARM_AEXT_V6M_ONLY): New define.
999 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1000 (ARM_ARCH_V6M_ONLY): New define.
1002 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1004 * mips.h (INSN_LOONGSON_3A): Defined.
1005 (CPU_LOONGSON_3A): Defined.
1006 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1008 2010-10-09 Matt Rice <ratmice@gmail.com>
1010 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1011 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1013 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1015 * arm.h (ARM_EXT_VIRT): New define.
1016 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1017 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1020 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1022 * arm.h (ARM_AEXT_ADIV): New define.
1023 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1025 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1027 * arm.h (ARM_EXT_OS): New define.
1028 (ARM_AEXT_V6SM): Likewise.
1029 (ARM_ARCH_V6SM): Likewise.
1031 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1033 * arm.h (ARM_EXT_MP): Add.
1034 (ARM_ARCH_V7A_MP): Likewise.
1036 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1038 * bfin.h: Declare pseudoChr structs/defines.
1040 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1042 * bfin.h: Strip trailing whitespace.
1044 2010-07-29 DJ Delorie <dj@redhat.com>
1046 * rx.h (RX_Operand_Type): Add TwoReg.
1047 (RX_Opcode_ID): Remove ediv and ediv2.
1049 2010-07-27 DJ Delorie <dj@redhat.com>
1051 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1053 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1054 Ina Pandit <ina.pandit@kpitcummins.com>
1056 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1057 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1058 PROCESSOR_V850E2_ALL.
1059 Remove PROCESSOR_V850EA support.
1060 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1061 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1062 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1063 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1064 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1065 V850_OPERAND_PERCENT.
1066 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1068 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1071 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1073 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1074 (MIPS16_INSN_BRANCH): Rename to...
1075 (MIPS16_INSN_COND_BRANCH): ... this.
1077 2010-07-03 Alan Modra <amodra@gmail.com>
1079 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1080 Renumber other PPC_OPCODE defines.
1082 2010-07-03 Alan Modra <amodra@gmail.com>
1084 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1086 2010-06-29 Alan Modra <amodra@gmail.com>
1088 * maxq.h: Delete file.
1090 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1092 * ppc.h (PPC_OPCODE_E500): Define.
1094 2010-05-26 Catherine Moore <clm@codesourcery.com>
1096 * opcode/mips.h (INSN_MIPS16): Remove.
1098 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1100 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1102 2010-04-15 Nick Clifton <nickc@redhat.com>
1104 * alpha.h: Update copyright notice to use GPLv3.
1110 * convex.h: Likewise.
1117 * h8300.h: Likewise.
1124 * m68hc11.h: Likewise.
1130 * mn10200.h: Likewise.
1131 * mn10300.h: Likewise.
1132 * msp430.h: Likewise.
1134 * ns32k.h: Likewise.
1136 * pdp11.h: Likewise.
1143 * score-datadep.h: Likewise.
1144 * score-inst.h: Likewise.
1145 * sparc.h: Likewise.
1146 * spu-insns.h: Likewise.
1148 * tic30.h: Likewise.
1149 * tic4x.h: Likewise.
1150 * tic54x.h: Likewise.
1151 * tic80.h: Likewise.
1155 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1157 * tic6x-control-registers.h, tic6x-insn-formats.h,
1158 tic6x-opcode-table.h, tic6x.h: New.
1160 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1162 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1164 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1166 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1168 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1170 * ia64.h (ia64_find_opcode): Remove argument name.
1171 (ia64_find_next_opcode): Likewise.
1172 (ia64_dis_opcode): Likewise.
1173 (ia64_free_opcode): Likewise.
1174 (ia64_find_dependency): Likewise.
1176 2009-11-22 Doug Evans <dje@sebabeach.org>
1178 * cgen.h: Include bfd_stdint.h.
1179 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1181 2009-11-18 Paul Brook <paul@codesourcery.com>
1183 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1185 2009-11-17 Paul Brook <paul@codesourcery.com>
1186 Daniel Jacobowitz <dan@codesourcery.com>
1188 * arm.h (ARM_EXT_V6_DSP): Define.
1189 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1190 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1192 2009-11-04 DJ Delorie <dj@redhat.com>
1194 * rx.h (rx_decode_opcode) (mvtipl): Add.
1195 (mvtcp, mvfcp, opecp): Remove.
1197 2009-11-02 Paul Brook <paul@codesourcery.com>
1199 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1200 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1201 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1202 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1203 FPU_ARCH_NEON_VFP_V4): Define.
1205 2009-10-23 Doug Evans <dje@sebabeach.org>
1207 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1208 * cgen.h: Update. Improve multi-inclusion macro name.
1210 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1212 * ppc.h (PPC_OPCODE_476): Define.
1214 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1216 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1218 2009-09-29 DJ Delorie <dj@redhat.com>
1222 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1224 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1226 2009-09-21 Ben Elliston <bje@au.ibm.com>
1228 * ppc.h (PPC_OPCODE_PPCA2): New.
1230 2009-09-05 Martin Thuresson <martin@mtme.org>
1232 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1234 2009-08-29 Martin Thuresson <martin@mtme.org>
1236 * tic30.h (template): Rename type template to
1237 insn_template. Updated code to use new name.
1238 * tic54x.h (template): Rename type template to
1241 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1243 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1245 2009-06-11 Anthony Green <green@moxielogic.com>
1247 * moxie.h (MOXIE_F3_PCREL): Define.
1248 (moxie_form3_opc_info): Grow.
1250 2009-06-06 Anthony Green <green@moxielogic.com>
1252 * moxie.h (MOXIE_F1_M): Define.
1254 2009-04-15 Anthony Green <green@moxielogic.com>
1258 2009-04-06 DJ Delorie <dj@redhat.com>
1260 * h8300.h: Add relaxation attributes to MOVA opcodes.
1262 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1264 * ppc.h (ppc_parse_cpu): Declare.
1266 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1268 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1269 and _IMM11 for mbitclr and mbitset.
1270 * score-datadep.h: Update dependency information.
1272 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1274 * ppc.h (PPC_OPCODE_POWER7): New.
1276 2009-02-06 Doug Evans <dje@google.com>
1278 * i386.h: Add comment regarding sse* insns and prefixes.
1280 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1282 * mips.h (INSN_XLR): Define.
1283 (INSN_CHIP_MASK): Update.
1285 (OPCODE_IS_MEMBER): Update.
1286 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1288 2009-01-28 Doug Evans <dje@google.com>
1290 * opcode/i386.h: Add multiple inclusion protection.
1291 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1292 (EDI_REG_NUM): New macros.
1293 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1294 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1295 (REX_PREFIX_P): New macro.
1297 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1299 * ppc.h (struct powerpc_opcode): New field "deprecated".
1300 (PPC_OPCODE_NOPOWER4): Delete.
1302 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1304 * mips.h: Define CPU_R14000, CPU_R16000.
1305 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1307 2008-11-18 Catherine Moore <clm@codesourcery.com>
1309 * arm.h (FPU_NEON_FP16): New.
1310 (FPU_ARCH_NEON_FP16): New.
1312 2008-11-06 Chao-ying Fu <fu@mips.com>
1314 * mips.h: Doucument '1' for 5-bit sync type.
1316 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1318 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1321 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1323 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1325 2008-07-30 Michael J. Eager <eager@eagercon.com>
1327 * ppc.h (PPC_OPCODE_405): Define.
1328 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1330 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1332 * ppc.h (ppc_cpu_t): New typedef.
1333 (struct powerpc_opcode <flags>): Use it.
1334 (struct powerpc_operand <insert, extract>): Likewise.
1335 (struct powerpc_macro <flags>): Likewise.
1337 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1339 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1340 Update comment before MIPS16 field descriptors to mention MIPS16.
1341 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1343 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1344 New bit masks and shift counts for cins and exts.
1346 * mips.h: Document new field descriptors +Q.
1347 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1349 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1351 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1352 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1354 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1356 * ppc.h: (PPC_OPCODE_E500MC): New.
1358 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1360 * i386.h (MAX_OPERANDS): Set to 5.
1361 (MAX_MNEM_SIZE): Changed to 20.
1363 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1365 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1367 2008-03-09 Paul Brook <paul@codesourcery.com>
1369 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1371 2008-03-04 Paul Brook <paul@codesourcery.com>
1373 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1374 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1375 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1377 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1378 Nick Clifton <nickc@redhat.com>
1381 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1382 with a 32-bit displacement but without the top bit of the 4th byte
1385 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1387 * cr16.h (cr16_num_optab): Declared.
1389 2008-02-14 Hakan Ardo <hakan@debian.org>
1392 * avr.h (AVR_ISA_2xxe): Define.
1394 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1396 * mips.h: Update copyright.
1397 (INSN_CHIP_MASK): New macro.
1398 (INSN_OCTEON): New macro.
1399 (CPU_OCTEON): New macro.
1400 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1402 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1404 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1406 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1408 * avr.h (AVR_ISA_USB162): Add new opcode set.
1409 (AVR_ISA_AVR3): Likewise.
1411 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1413 * mips.h (INSN_LOONGSON_2E): New.
1414 (INSN_LOONGSON_2F): New.
1415 (CPU_LOONGSON_2E): New.
1416 (CPU_LOONGSON_2F): New.
1417 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1419 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1421 * mips.h (INSN_ISA*): Redefine certain values as an
1422 enumeration. Update comments.
1423 (mips_isa_table): New.
1424 (ISA_MIPS*): Redefine to match enumeration.
1425 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1428 2007-08-08 Ben Elliston <bje@au.ibm.com>
1430 * ppc.h (PPC_OPCODE_PPCPS): New.
1432 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1434 * m68k.h: Document j K & E.
1436 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1438 * cr16.h: New file for CR16 target.
1440 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1442 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1444 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1446 * m68k.h (mcfisa_c): New.
1447 (mcfusp, mcf_mask): Adjust.
1449 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1451 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1452 (num_powerpc_operands): Declare.
1453 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1454 (PPC_OPERAND_PLUS1): Define.
1456 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1458 * i386.h (REX_MODE64): Renamed to ...
1460 (REX_EXTX): Renamed to ...
1462 (REX_EXTY): Renamed to ...
1464 (REX_EXTZ): Renamed to ...
1467 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1469 * i386.h: Add entries from config/tc-i386.h and move tables
1470 to opcodes/i386-opc.h.
1472 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1474 * i386.h (FloatDR): Removed.
1475 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1477 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1479 * spu-insns.h: Add soma double-float insns.
1481 2007-02-20 Thiemo Seufer <ths@mips.com>
1482 Chao-Ying Fu <fu@mips.com>
1484 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1485 (INSN_DSPR2): Add flag for DSP R2 instructions.
1486 (M_BALIGN): New macro.
1488 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1490 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1491 and Seg3ShortFrom with Shortform.
1493 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1496 * i386.h (i386_optab): Put the real "test" before the pseudo
1499 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1501 * m68k.h (m68010up): OR fido_a.
1503 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1505 * m68k.h (fido_a): New.
1507 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1509 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1510 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1513 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1515 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1517 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1519 * score-inst.h (enum score_insn_type): Add Insn_internal.
1521 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1522 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1523 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1524 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1525 Alan Modra <amodra@bigpond.net.au>
1527 * spu-insns.h: New file.
1530 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1532 * ppc.h (PPC_OPCODE_CELL): Define.
1534 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1536 * i386.h : Modify opcode to support for the change in POPCNT opcode
1537 in amdfam10 architecture.
1539 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1541 * i386.h: Replace CpuMNI with CpuSSSE3.
1543 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1544 Joseph Myers <joseph@codesourcery.com>
1545 Ian Lance Taylor <ian@wasabisystems.com>
1546 Ben Elliston <bje@wasabisystems.com>
1548 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1550 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1552 * score-datadep.h: New file.
1553 * score-inst.h: New file.
1555 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1557 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1558 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1559 movdq2q and movq2dq.
1561 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1562 Michael Meissner <michael.meissner@amd.com>
1564 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1566 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1568 * i386.h (i386_optab): Add "nop" with memory reference.
1570 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1572 * i386.h (i386_optab): Update comment for 64bit NOP.
1574 2006-06-06 Ben Elliston <bje@au.ibm.com>
1575 Anton Blanchard <anton@samba.org>
1577 * ppc.h (PPC_OPCODE_POWER6): Define.
1580 2006-06-05 Thiemo Seufer <ths@mips.com>
1582 * mips.h: Improve description of MT flags.
1584 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1586 * m68k.h (mcf_mask): Define.
1588 2006-05-05 Thiemo Seufer <ths@mips.com>
1589 David Ung <davidu@mips.com>
1591 * mips.h (enum): Add macro M_CACHE_AB.
1593 2006-05-04 Thiemo Seufer <ths@mips.com>
1594 Nigel Stephens <nigel@mips.com>
1595 David Ung <davidu@mips.com>
1597 * mips.h: Add INSN_SMARTMIPS define.
1599 2006-04-30 Thiemo Seufer <ths@mips.com>
1600 David Ung <davidu@mips.com>
1602 * mips.h: Defines udi bits and masks. Add description of
1603 characters which may appear in the args field of udi
1606 2006-04-26 Thiemo Seufer <ths@networkno.de>
1608 * mips.h: Improve comments describing the bitfield instruction
1611 2006-04-26 Julian Brown <julian@codesourcery.com>
1613 * arm.h (FPU_VFP_EXT_V3): Define constant.
1614 (FPU_NEON_EXT_V1): Likewise.
1615 (FPU_VFP_HARD): Update.
1616 (FPU_VFP_V3): Define macro.
1617 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1619 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1621 * avr.h (AVR_ISA_PWMx): New.
1623 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1625 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1626 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1627 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1628 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1629 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1631 2006-03-10 Paul Brook <paul@codesourcery.com>
1633 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1635 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1637 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1638 first. Correct mask of bb "B" opcode.
1640 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1642 * i386.h (i386_optab): Support Intel Merom New Instructions.
1644 2006-02-24 Paul Brook <paul@codesourcery.com>
1646 * arm.h: Add V7 feature bits.
1648 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1650 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1652 2006-01-31 Paul Brook <paul@codesourcery.com>
1653 Richard Earnshaw <rearnsha@arm.com>
1655 * arm.h: Use ARM_CPU_FEATURE.
1656 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1657 (arm_feature_set): Change to a structure.
1658 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1659 ARM_FEATURE): New macros.
1661 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1663 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1664 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1665 (ADD_PC_INCR_OPCODE): Don't define.
1667 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1670 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1672 2005-11-14 David Ung <davidu@mips.com>
1674 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1675 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1676 save/restore encoding of the args field.
1678 2005-10-28 Dave Brolley <brolley@redhat.com>
1680 Contribute the following changes:
1681 2005-02-16 Dave Brolley <brolley@redhat.com>
1683 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1684 cgen_isa_mask_* to cgen_bitset_*.
1687 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1689 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1690 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1691 (CGEN_CPU_TABLE): Make isas a ponter.
1693 2003-09-29 Dave Brolley <brolley@redhat.com>
1695 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1696 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1697 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1699 2002-12-13 Dave Brolley <brolley@redhat.com>
1701 * cgen.h (symcat.h): #include it.
1702 (cgen-bitset.h): #include it.
1703 (CGEN_ATTR_VALUE_TYPE): Now a union.
1704 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1705 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1706 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1707 * cgen-bitset.h: New file.
1709 2005-09-30 Catherine Moore <clm@cm00re.com>
1713 2005-10-24 Jan Beulich <jbeulich@novell.com>
1715 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1718 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1720 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1721 Add FLAG_STRICT to pa10 ftest opcode.
1723 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1725 * hppa.h (pa_opcodes): Remove lha entries.
1727 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1729 * hppa.h (FLAG_STRICT): Revise comment.
1730 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1731 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1734 2005-09-30 Catherine Moore <clm@cm00re.com>
1738 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1740 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1742 2005-09-06 Chao-ying Fu <fu@mips.com>
1744 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1745 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1747 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1748 (INSN_ASE_MASK): Update to include INSN_MT.
1749 (INSN_MT): New define for MT ASE.
1751 2005-08-25 Chao-ying Fu <fu@mips.com>
1753 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1754 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1755 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1756 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1757 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1758 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1760 (INSN_DSP): New define for DSP ASE.
1762 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1766 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1768 * ppc.h (PPC_OPCODE_E300): Define.
1770 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1772 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1774 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1777 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1780 2005-07-27 Jan Beulich <jbeulich@novell.com>
1782 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1783 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1784 Add movq-s as 64-bit variants of movd-s.
1786 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1788 * hppa.h: Fix punctuation in comment.
1790 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1791 implicit space-register addressing. Set space-register bits on opcodes
1792 using implicit space-register addressing. Add various missing pa20
1793 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1794 space-register addressing. Use "fE" instead of "fe" in various
1797 2005-07-18 Jan Beulich <jbeulich@novell.com>
1799 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1801 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1803 * i386.h (i386_optab): Support Intel VMX Instructions.
1805 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1807 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1809 2005-07-05 Jan Beulich <jbeulich@novell.com>
1811 * i386.h (i386_optab): Add new insns.
1813 2005-07-01 Nick Clifton <nickc@redhat.com>
1815 * sparc.h: Add typedefs to structure declarations.
1817 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1820 * i386.h (i386_optab): Update comments for 64bit addressing on
1821 mov. Allow 64bit addressing for mov and movq.
1823 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1825 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1826 respectively, in various floating-point load and store patterns.
1828 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1830 * hppa.h (FLAG_STRICT): Correct comment.
1831 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1832 PA 2.0 mneumonics when equivalent. Entries with cache control
1833 completers now require PA 1.1. Adjust whitespace.
1835 2005-05-19 Anton Blanchard <anton@samba.org>
1837 * ppc.h (PPC_OPCODE_POWER5): Define.
1839 2005-05-10 Nick Clifton <nickc@redhat.com>
1841 * Update the address and phone number of the FSF organization in
1842 the GPL notices in the following files:
1843 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1844 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1845 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1846 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1847 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1848 tic54x.h, tic80.h, v850.h, vax.h
1850 2005-05-09 Jan Beulich <jbeulich@novell.com>
1852 * i386.h (i386_optab): Add ht and hnt.
1854 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1856 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1857 Add xcrypt-ctr. Provide aliases without hyphens.
1859 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1861 Moved from ../ChangeLog
1863 2005-04-12 Paul Brook <paul@codesourcery.com>
1864 * m88k.h: Rename psr macros to avoid conflicts.
1866 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1867 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1868 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1869 and ARM_ARCH_V6ZKT2.
1871 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1872 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1873 Remove redundant instruction types.
1874 (struct argument): X_op - new field.
1875 (struct cst4_entry): Remove.
1876 (no_op_insn): Declare.
1878 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1879 * crx.h (enum argtype): Rename types, remove unused types.
1881 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1882 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1883 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1884 (enum operand_type): Rearrange operands, edit comments.
1885 replace us<N> with ui<N> for unsigned immediate.
1886 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1887 displacements (respectively).
1888 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1889 (instruction type): Add NO_TYPE_INS.
1890 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1891 (operand_entry): New field - 'flags'.
1892 (operand flags): New.
1894 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1895 * crx.h (operand_type): Remove redundant types i3, i4,
1897 Add new unsigned immediate types us3, us4, us5, us16.
1899 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1901 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1902 adjust them accordingly.
1904 2005-04-01 Jan Beulich <jbeulich@novell.com>
1906 * i386.h (i386_optab): Add rdtscp.
1908 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1910 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1911 between memory and segment register. Allow movq for moving between
1912 general-purpose register and segment register.
1914 2005-02-09 Jan Beulich <jbeulich@novell.com>
1917 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1918 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1921 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1923 * m68k.h (m68008, m68ec030, m68882): Remove.
1925 (cpu_m68k, cpu_cf): New.
1926 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1927 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1929 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1931 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1932 * cgen.h (enum cgen_parse_operand_type): Add
1933 CGEN_PARSE_OPERAND_SYMBOLIC.
1935 2005-01-21 Fred Fish <fnf@specifixinc.com>
1937 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1938 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1939 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1941 2005-01-19 Fred Fish <fnf@specifixinc.com>
1943 * mips.h (struct mips_opcode): Add new pinfo2 member.
1944 (INSN_ALIAS): New define for opcode table entries that are
1945 specific instances of another entry, such as 'move' for an 'or'
1946 with a zero operand.
1947 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1948 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1950 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1952 * mips.h (CPU_RM9000): Define.
1953 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1955 2004-11-25 Jan Beulich <jbeulich@novell.com>
1957 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1958 to/from test registers are illegal in 64-bit mode. Add missing
1959 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1960 (previously one had to explicitly encode a rex64 prefix). Re-enable
1961 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1962 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1964 2004-11-23 Jan Beulich <jbeulich@novell.com>
1966 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1967 available only with SSE2. Change the MMX additions introduced by SSE
1968 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1969 instructions by their now designated identifier (since combining i686
1970 and 3DNow! does not really imply 3DNow!A).
1972 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1974 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1975 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1977 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1978 Vineet Sharma <vineets@noida.hcltech.com>
1980 * maxq.h: New file: Disassembly information for the maxq port.
1982 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1984 * i386.h (i386_optab): Put back "movzb".
1986 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1988 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1989 comments. Remove member cris_ver_sim. Add members
1990 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1991 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1992 (struct cris_support_reg, struct cris_cond15): New types.
1993 (cris_conds15): Declare.
1994 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1995 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1996 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1997 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1998 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1999 SIZE_FIELD_UNSIGNED.
2001 2004-11-04 Jan Beulich <jbeulich@novell.com>
2003 * i386.h (sldx_Suf): Remove.
2004 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2005 (q_FP): Define, implying no REX64.
2006 (x_FP, sl_FP): Imply FloatMF.
2007 (i386_optab): Split reg and mem forms of moving from segment registers
2008 so that the memory forms can ignore the 16-/32-bit operand size
2009 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2010 all non-floating-point instructions. Unite 32- and 64-bit forms of
2011 movsx, movzx, and movd. Adjust floating point operations for the above
2012 changes to the *FP macros. Add DefaultSize to floating point control
2013 insns operating on larger memory ranges. Remove left over comments
2014 hinting at certain insns being Intel-syntax ones where the ones
2015 actually meant are already gone.
2017 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2019 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2022 2004-09-30 Paul Brook <paul@codesourcery.com>
2024 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2025 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2027 2004-09-11 Theodore A. Roth <troth@openavr.org>
2029 * avr.h: Add support for
2030 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2032 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2034 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2036 2004-08-24 Dmitry Diky <diwil@spec.ru>
2038 * msp430.h (msp430_opc): Add new instructions.
2039 (msp430_rcodes): Declare new instructions.
2040 (msp430_hcodes): Likewise..
2042 2004-08-13 Nick Clifton <nickc@redhat.com>
2045 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2048 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2050 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2052 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2054 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2056 2004-07-21 Jan Beulich <jbeulich@novell.com>
2058 * i386.h: Adjust instruction descriptions to better match the
2061 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2063 * arm.h: Remove all old content. Replace with architecture defines
2064 from gas/config/tc-arm.c.
2066 2004-07-09 Andreas Schwab <schwab@suse.de>
2068 * m68k.h: Fix comment.
2070 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2074 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2076 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2078 2004-05-24 Peter Barada <peter@the-baradas.com>
2080 * m68k.h: Add 'size' to m68k_opcode.
2082 2004-05-05 Peter Barada <peter@the-baradas.com>
2084 * m68k.h: Switch from ColdFire chip name to core variant.
2086 2004-04-22 Peter Barada <peter@the-baradas.com>
2088 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2089 descriptions for new EMAC cases.
2090 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2091 handle Motorola MAC syntax.
2092 Allow disassembly of ColdFire V4e object files.
2094 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2096 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2098 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2100 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2102 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2104 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2106 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2108 * i386.h (i386_optab): Added xstore/xcrypt insns.
2110 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2112 * h8300.h (32bit ldc/stc): Add relaxing support.
2114 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2116 * h8300.h (BITOP): Pass MEMRELAX flag.
2118 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2120 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2123 For older changes see ChangeLog-9103
2125 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2127 Copying and distribution of this file, with or without modification,
2128 are permitted in any medium without royalty provided the copyright
2129 notice and this notice are preserved.
2135 version-control: never
projects / deliverable / binutils-gdb.git / blob