1 2011-11-29 Andrew Pinski <apinski@cavium.com>
3 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
4 (INSN_OCTEONP): New macro.
5 (CPU_OCTEONP): New macro.
6 (OPCODE_IS_MEMBER): Add Octeon+.
7 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
9 2011-11-01 DJ Delorie <dj@redhat.com>
13 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
15 * mips.h: Fix a typo in description.
17 2011-09-21 David S. Miller <davem@davemloft.net>
19 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
20 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
21 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
22 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
24 2011-08-09 Chao-ying Fu <fu@mips.com>
25 Maciej W. Rozycki <macro@codesourcery.com>
27 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
28 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
29 (INSN_ASE_MASK): Add the MCU bit.
30 (INSN_MCU): New macro.
31 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
32 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
34 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
36 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
37 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
38 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
39 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
40 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
41 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
42 (INSN2_READ_GPR_MMN): Likewise.
43 (INSN2_READ_FPR_D): Change the bit used.
44 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
45 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
46 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
47 (INSN2_COND_BRANCH): Likewise.
48 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
49 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
50 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
51 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
52 (INSN2_MOD_GPR_MN): Likewise.
54 2011-08-05 David S. Miller <davem@davemloft.net>
56 * sparc.h: Document new format codes '4', '5', and '('.
57 (OPF_LOW4, RS3): New macros.
59 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
61 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
62 order of flags documented.
64 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
66 * mips.h: Clarify the description of microMIPS instruction
68 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
70 2011-07-24 Chao-ying Fu <fu@mips.com>
71 Maciej W. Rozycki <macro@codesourcery.com>
73 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
74 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
75 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
76 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
77 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
78 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
79 (OP_MASK_RS3, OP_SH_RS3): Likewise.
80 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
81 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
82 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
83 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
84 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
85 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
86 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
87 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
88 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
89 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
90 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
91 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
92 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
93 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
94 (INSN_WRITE_GPR_S): New macro.
95 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
96 (INSN2_READ_FPR_D): Likewise.
97 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
98 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
99 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
100 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
101 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
102 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
103 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
104 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
105 (CPU_MICROMIPS): New macro.
106 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
107 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
108 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
109 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
110 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
111 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
112 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
113 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
114 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
115 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
116 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
117 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
118 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
119 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
120 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
121 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
122 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
123 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
124 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
125 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
126 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
127 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
128 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
129 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
130 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
131 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
132 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
133 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
134 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
135 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
136 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
137 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
138 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
139 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
140 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
141 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
142 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
143 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
144 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
145 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
146 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
147 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
148 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
149 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
150 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
151 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
152 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
153 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
154 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
155 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
156 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
157 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
158 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
159 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
160 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
161 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
162 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
163 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
164 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
165 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
166 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
167 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
168 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
169 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
170 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
171 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
172 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
173 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
174 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
175 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
176 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
177 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
178 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
179 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
180 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
181 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
182 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
183 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
184 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
185 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
186 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
187 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
188 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
189 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
190 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
191 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
192 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
193 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
194 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
195 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
196 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
197 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
198 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
199 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
200 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
201 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
202 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
203 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
204 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
205 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
206 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
207 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
208 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
209 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
210 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
211 (micromips_opcodes): New declaration.
212 (bfd_micromips_num_opcodes): Likewise.
214 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
216 * mips.h (INSN_TRAP): Rename to...
217 (INSN_NO_DELAY_SLOT): ... this.
218 (INSN_SYNC): Remove macro.
220 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
222 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
223 a duplicate of AVR_ISA_SPM.
225 2011-07-01 Nick Clifton <nickc@redhat.com>
227 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
229 2011-06-18 Robin Getz <robin.getz@analog.com>
231 * bfin.h (is_macmod_signed): New func
233 2011-06-18 Mike Frysinger <vapier@gentoo.org>
235 * bfin.h (is_macmod_pmove): Add missing space before func args.
236 (is_macmod_hmove): Likewise.
238 2011-06-13 Walter Lee <walt@tilera.com>
240 * tilegx.h: New file.
241 * tilepro.h: New file.
243 2011-05-31 Paul Brook <paul@codesourcery.com>
245 * arm.h (ARM_ARCH_V7R_IDIV): Define.
247 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
249 * s390.h: Replace S390_OPERAND_REG_EVEN with
250 S390_OPERAND_REG_PAIR.
252 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
254 * s390.h: Add S390_OPCODE_REG_EVEN flag.
256 2011-04-18 Julian Brown <julian@codesourcery.com>
258 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
260 2011-04-11 Dan McDonald <dan@wellkeeper.com>
263 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
265 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
267 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
268 New instruction set flags.
269 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
271 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
273 * mips.h (M_PREF_AB): New enum value.
275 2011-02-12 Mike Frysinger <vapier@gentoo.org>
277 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
279 (is_macmod_pmove, is_macmod_hmove): New functions.
281 2011-02-11 Mike Frysinger <vapier@gentoo.org>
283 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
285 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
287 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
288 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
290 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
293 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
296 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
299 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
301 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
303 * mips.h: Update commentary after last commit.
305 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
307 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
308 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
309 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
311 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
313 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
315 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
317 * mips.h: Fix previous commit.
319 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
321 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
322 (INSN_LOONGSON_3A): Clear bit 31.
324 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
327 * arm.h (ARM_AEXT_V6M_ONLY): New define.
328 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
329 (ARM_ARCH_V6M_ONLY): New define.
331 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
333 * mips.h (INSN_LOONGSON_3A): Defined.
334 (CPU_LOONGSON_3A): Defined.
335 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
337 2010-10-09 Matt Rice <ratmice@gmail.com>
339 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
340 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
342 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
344 * arm.h (ARM_EXT_VIRT): New define.
345 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
346 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
349 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
351 * arm.h (ARM_AEXT_ADIV): New define.
352 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
354 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
356 * arm.h (ARM_EXT_OS): New define.
357 (ARM_AEXT_V6SM): Likewise.
358 (ARM_ARCH_V6SM): Likewise.
360 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
362 * arm.h (ARM_EXT_MP): Add.
363 (ARM_ARCH_V7A_MP): Likewise.
365 2010-09-22 Mike Frysinger <vapier@gentoo.org>
367 * bfin.h: Declare pseudoChr structs/defines.
369 2010-09-21 Mike Frysinger <vapier@gentoo.org>
371 * bfin.h: Strip trailing whitespace.
373 2010-07-29 DJ Delorie <dj@redhat.com>
375 * rx.h (RX_Operand_Type): Add TwoReg.
376 (RX_Opcode_ID): Remove ediv and ediv2.
378 2010-07-27 DJ Delorie <dj@redhat.com>
380 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
382 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
383 Ina Pandit <ina.pandit@kpitcummins.com>
385 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
386 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
387 PROCESSOR_V850E2_ALL.
388 Remove PROCESSOR_V850EA support.
389 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
390 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
391 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
392 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
393 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
394 V850_OPERAND_PERCENT.
395 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
397 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
400 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
402 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
403 (MIPS16_INSN_BRANCH): Rename to...
404 (MIPS16_INSN_COND_BRANCH): ... this.
406 2010-07-03 Alan Modra <amodra@gmail.com>
408 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
409 Renumber other PPC_OPCODE defines.
411 2010-07-03 Alan Modra <amodra@gmail.com>
413 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
415 2010-06-29 Alan Modra <amodra@gmail.com>
417 * maxq.h: Delete file.
419 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
421 * ppc.h (PPC_OPCODE_E500): Define.
423 2010-05-26 Catherine Moore <clm@codesourcery.com>
425 * opcode/mips.h (INSN_MIPS16): Remove.
427 2010-04-21 Joseph Myers <joseph@codesourcery.com>
429 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
431 2010-04-15 Nick Clifton <nickc@redhat.com>
433 * alpha.h: Update copyright notice to use GPLv3.
439 * convex.h: Likewise.
453 * m68hc11.h: Likewise.
459 * mn10200.h: Likewise.
460 * mn10300.h: Likewise.
461 * msp430.h: Likewise.
472 * score-datadep.h: Likewise.
473 * score-inst.h: Likewise.
475 * spu-insns.h: Likewise.
479 * tic54x.h: Likewise.
484 2010-03-25 Joseph Myers <joseph@codesourcery.com>
486 * tic6x-control-registers.h, tic6x-insn-formats.h,
487 tic6x-opcode-table.h, tic6x.h: New.
489 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
491 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
493 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
495 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
497 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
499 * ia64.h (ia64_find_opcode): Remove argument name.
500 (ia64_find_next_opcode): Likewise.
501 (ia64_dis_opcode): Likewise.
502 (ia64_free_opcode): Likewise.
503 (ia64_find_dependency): Likewise.
505 2009-11-22 Doug Evans <dje@sebabeach.org>
507 * cgen.h: Include bfd_stdint.h.
508 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
510 2009-11-18 Paul Brook <paul@codesourcery.com>
512 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
514 2009-11-17 Paul Brook <paul@codesourcery.com>
515 Daniel Jacobowitz <dan@codesourcery.com>
517 * arm.h (ARM_EXT_V6_DSP): Define.
518 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
519 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
521 2009-11-04 DJ Delorie <dj@redhat.com>
523 * rx.h (rx_decode_opcode) (mvtipl): Add.
524 (mvtcp, mvfcp, opecp): Remove.
526 2009-11-02 Paul Brook <paul@codesourcery.com>
528 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
529 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
530 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
531 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
532 FPU_ARCH_NEON_VFP_V4): Define.
534 2009-10-23 Doug Evans <dje@sebabeach.org>
536 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
537 * cgen.h: Update. Improve multi-inclusion macro name.
539 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
541 * ppc.h (PPC_OPCODE_476): Define.
543 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
545 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
547 2009-09-29 DJ Delorie <dj@redhat.com>
551 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
553 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
555 2009-09-21 Ben Elliston <bje@au.ibm.com>
557 * ppc.h (PPC_OPCODE_PPCA2): New.
559 2009-09-05 Martin Thuresson <martin@mtme.org>
561 * ia64.h (struct ia64_operand): Renamed member class to op_class.
563 2009-08-29 Martin Thuresson <martin@mtme.org>
565 * tic30.h (template): Rename type template to
566 insn_template. Updated code to use new name.
567 * tic54x.h (template): Rename type template to
570 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
572 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
574 2009-06-11 Anthony Green <green@moxielogic.com>
576 * moxie.h (MOXIE_F3_PCREL): Define.
577 (moxie_form3_opc_info): Grow.
579 2009-06-06 Anthony Green <green@moxielogic.com>
581 * moxie.h (MOXIE_F1_M): Define.
583 2009-04-15 Anthony Green <green@moxielogic.com>
587 2009-04-06 DJ Delorie <dj@redhat.com>
589 * h8300.h: Add relaxation attributes to MOVA opcodes.
591 2009-03-10 Alan Modra <amodra@bigpond.net.au>
593 * ppc.h (ppc_parse_cpu): Declare.
595 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
597 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
598 and _IMM11 for mbitclr and mbitset.
599 * score-datadep.h: Update dependency information.
601 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
603 * ppc.h (PPC_OPCODE_POWER7): New.
605 2009-02-06 Doug Evans <dje@google.com>
607 * i386.h: Add comment regarding sse* insns and prefixes.
609 2009-02-03 Sandip Matte <sandip@rmicorp.com>
611 * mips.h (INSN_XLR): Define.
612 (INSN_CHIP_MASK): Update.
614 (OPCODE_IS_MEMBER): Update.
615 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
617 2009-01-28 Doug Evans <dje@google.com>
619 * opcode/i386.h: Add multiple inclusion protection.
620 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
621 (EDI_REG_NUM): New macros.
622 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
623 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
624 (REX_PREFIX_P): New macro.
626 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
628 * ppc.h (struct powerpc_opcode): New field "deprecated".
629 (PPC_OPCODE_NOPOWER4): Delete.
631 2008-11-28 Joshua Kinard <kumba@gentoo.org>
633 * mips.h: Define CPU_R14000, CPU_R16000.
634 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
636 2008-11-18 Catherine Moore <clm@codesourcery.com>
638 * arm.h (FPU_NEON_FP16): New.
639 (FPU_ARCH_NEON_FP16): New.
641 2008-11-06 Chao-ying Fu <fu@mips.com>
643 * mips.h: Doucument '1' for 5-bit sync type.
645 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
647 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
650 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
652 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
654 2008-07-30 Michael J. Eager <eager@eagercon.com>
656 * ppc.h (PPC_OPCODE_405): Define.
657 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
659 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
661 * ppc.h (ppc_cpu_t): New typedef.
662 (struct powerpc_opcode <flags>): Use it.
663 (struct powerpc_operand <insert, extract>): Likewise.
664 (struct powerpc_macro <flags>): Likewise.
666 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
668 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
669 Update comment before MIPS16 field descriptors to mention MIPS16.
670 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
672 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
673 New bit masks and shift counts for cins and exts.
675 * mips.h: Document new field descriptors +Q.
676 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
678 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
680 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
681 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
683 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
685 * ppc.h: (PPC_OPCODE_E500MC): New.
687 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
689 * i386.h (MAX_OPERANDS): Set to 5.
690 (MAX_MNEM_SIZE): Changed to 20.
692 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
694 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
696 2008-03-09 Paul Brook <paul@codesourcery.com>
698 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
700 2008-03-04 Paul Brook <paul@codesourcery.com>
702 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
703 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
704 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
706 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
707 Nick Clifton <nickc@redhat.com>
710 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
711 with a 32-bit displacement but without the top bit of the 4th byte
714 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
716 * cr16.h (cr16_num_optab): Declared.
718 2008-02-14 Hakan Ardo <hakan@debian.org>
721 * avr.h (AVR_ISA_2xxe): Define.
723 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
725 * mips.h: Update copyright.
726 (INSN_CHIP_MASK): New macro.
727 (INSN_OCTEON): New macro.
728 (CPU_OCTEON): New macro.
729 (OPCODE_IS_MEMBER): Handle Octeon instructions.
731 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
733 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
735 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
737 * avr.h (AVR_ISA_USB162): Add new opcode set.
738 (AVR_ISA_AVR3): Likewise.
740 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
742 * mips.h (INSN_LOONGSON_2E): New.
743 (INSN_LOONGSON_2F): New.
744 (CPU_LOONGSON_2E): New.
745 (CPU_LOONGSON_2F): New.
746 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
748 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
750 * mips.h (INSN_ISA*): Redefine certain values as an
751 enumeration. Update comments.
752 (mips_isa_table): New.
753 (ISA_MIPS*): Redefine to match enumeration.
754 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
757 2007-08-08 Ben Elliston <bje@au.ibm.com>
759 * ppc.h (PPC_OPCODE_PPCPS): New.
761 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
763 * m68k.h: Document j K & E.
765 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
767 * cr16.h: New file for CR16 target.
769 2007-05-02 Alan Modra <amodra@bigpond.net.au>
771 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
773 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
775 * m68k.h (mcfisa_c): New.
776 (mcfusp, mcf_mask): Adjust.
778 2007-04-20 Alan Modra <amodra@bigpond.net.au>
780 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
781 (num_powerpc_operands): Declare.
782 (PPC_OPERAND_SIGNED et al): Redefine as hex.
783 (PPC_OPERAND_PLUS1): Define.
785 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
787 * i386.h (REX_MODE64): Renamed to ...
789 (REX_EXTX): Renamed to ...
791 (REX_EXTY): Renamed to ...
793 (REX_EXTZ): Renamed to ...
796 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
798 * i386.h: Add entries from config/tc-i386.h and move tables
799 to opcodes/i386-opc.h.
801 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
803 * i386.h (FloatDR): Removed.
804 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
806 2007-03-01 Alan Modra <amodra@bigpond.net.au>
808 * spu-insns.h: Add soma double-float insns.
810 2007-02-20 Thiemo Seufer <ths@mips.com>
811 Chao-Ying Fu <fu@mips.com>
813 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
814 (INSN_DSPR2): Add flag for DSP R2 instructions.
815 (M_BALIGN): New macro.
817 2007-02-14 Alan Modra <amodra@bigpond.net.au>
819 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
820 and Seg3ShortFrom with Shortform.
822 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
825 * i386.h (i386_optab): Put the real "test" before the pseudo
828 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
830 * m68k.h (m68010up): OR fido_a.
832 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
834 * m68k.h (fido_a): New.
836 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
838 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
839 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
842 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
844 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
846 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
848 * score-inst.h (enum score_insn_type): Add Insn_internal.
850 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
851 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
852 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
853 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
854 Alan Modra <amodra@bigpond.net.au>
856 * spu-insns.h: New file.
859 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
861 * ppc.h (PPC_OPCODE_CELL): Define.
863 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
865 * i386.h : Modify opcode to support for the change in POPCNT opcode
866 in amdfam10 architecture.
868 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
870 * i386.h: Replace CpuMNI with CpuSSSE3.
872 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
873 Joseph Myers <joseph@codesourcery.com>
874 Ian Lance Taylor <ian@wasabisystems.com>
875 Ben Elliston <bje@wasabisystems.com>
877 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
879 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
881 * score-datadep.h: New file.
882 * score-inst.h: New file.
884 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
886 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
887 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
890 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
891 Michael Meissner <michael.meissner@amd.com>
893 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
895 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
897 * i386.h (i386_optab): Add "nop" with memory reference.
899 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
901 * i386.h (i386_optab): Update comment for 64bit NOP.
903 2006-06-06 Ben Elliston <bje@au.ibm.com>
904 Anton Blanchard <anton@samba.org>
906 * ppc.h (PPC_OPCODE_POWER6): Define.
909 2006-06-05 Thiemo Seufer <ths@mips.com>
911 * mips.h: Improve description of MT flags.
913 2006-05-25 Richard Sandiford <richard@codesourcery.com>
915 * m68k.h (mcf_mask): Define.
917 2006-05-05 Thiemo Seufer <ths@mips.com>
918 David Ung <davidu@mips.com>
920 * mips.h (enum): Add macro M_CACHE_AB.
922 2006-05-04 Thiemo Seufer <ths@mips.com>
923 Nigel Stephens <nigel@mips.com>
924 David Ung <davidu@mips.com>
926 * mips.h: Add INSN_SMARTMIPS define.
928 2006-04-30 Thiemo Seufer <ths@mips.com>
929 David Ung <davidu@mips.com>
931 * mips.h: Defines udi bits and masks. Add description of
932 characters which may appear in the args field of udi
935 2006-04-26 Thiemo Seufer <ths@networkno.de>
937 * mips.h: Improve comments describing the bitfield instruction
940 2006-04-26 Julian Brown <julian@codesourcery.com>
942 * arm.h (FPU_VFP_EXT_V3): Define constant.
943 (FPU_NEON_EXT_V1): Likewise.
944 (FPU_VFP_HARD): Update.
945 (FPU_VFP_V3): Define macro.
946 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
948 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
950 * avr.h (AVR_ISA_PWMx): New.
952 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
954 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
955 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
956 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
957 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
958 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
960 2006-03-10 Paul Brook <paul@codesourcery.com>
962 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
964 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
966 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
967 first. Correct mask of bb "B" opcode.
969 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
971 * i386.h (i386_optab): Support Intel Merom New Instructions.
973 2006-02-24 Paul Brook <paul@codesourcery.com>
975 * arm.h: Add V7 feature bits.
977 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
979 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
981 2006-01-31 Paul Brook <paul@codesourcery.com>
982 Richard Earnshaw <rearnsha@arm.com>
984 * arm.h: Use ARM_CPU_FEATURE.
985 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
986 (arm_feature_set): Change to a structure.
987 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
988 ARM_FEATURE): New macros.
990 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
992 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
993 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
994 (ADD_PC_INCR_OPCODE): Don't define.
996 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
999 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1001 2005-11-14 David Ung <davidu@mips.com>
1003 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1004 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1005 save/restore encoding of the args field.
1007 2005-10-28 Dave Brolley <brolley@redhat.com>
1009 Contribute the following changes:
1010 2005-02-16 Dave Brolley <brolley@redhat.com>
1012 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1013 cgen_isa_mask_* to cgen_bitset_*.
1016 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1018 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1019 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1020 (CGEN_CPU_TABLE): Make isas a ponter.
1022 2003-09-29 Dave Brolley <brolley@redhat.com>
1024 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1025 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1026 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1028 2002-12-13 Dave Brolley <brolley@redhat.com>
1030 * cgen.h (symcat.h): #include it.
1031 (cgen-bitset.h): #include it.
1032 (CGEN_ATTR_VALUE_TYPE): Now a union.
1033 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1034 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1035 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1036 * cgen-bitset.h: New file.
1038 2005-09-30 Catherine Moore <clm@cm00re.com>
1042 2005-10-24 Jan Beulich <jbeulich@novell.com>
1044 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1047 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1049 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1050 Add FLAG_STRICT to pa10 ftest opcode.
1052 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1054 * hppa.h (pa_opcodes): Remove lha entries.
1056 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1058 * hppa.h (FLAG_STRICT): Revise comment.
1059 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1060 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1063 2005-09-30 Catherine Moore <clm@cm00re.com>
1067 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1069 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1071 2005-09-06 Chao-ying Fu <fu@mips.com>
1073 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1074 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1076 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1077 (INSN_ASE_MASK): Update to include INSN_MT.
1078 (INSN_MT): New define for MT ASE.
1080 2005-08-25 Chao-ying Fu <fu@mips.com>
1082 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1083 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1084 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1085 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1086 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1087 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1089 (INSN_DSP): New define for DSP ASE.
1091 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1095 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1097 * ppc.h (PPC_OPCODE_E300): Define.
1099 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1101 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1103 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1106 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1109 2005-07-27 Jan Beulich <jbeulich@novell.com>
1111 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1112 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1113 Add movq-s as 64-bit variants of movd-s.
1115 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1117 * hppa.h: Fix punctuation in comment.
1119 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1120 implicit space-register addressing. Set space-register bits on opcodes
1121 using implicit space-register addressing. Add various missing pa20
1122 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1123 space-register addressing. Use "fE" instead of "fe" in various
1126 2005-07-18 Jan Beulich <jbeulich@novell.com>
1128 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1130 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1132 * i386.h (i386_optab): Support Intel VMX Instructions.
1134 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1136 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1138 2005-07-05 Jan Beulich <jbeulich@novell.com>
1140 * i386.h (i386_optab): Add new insns.
1142 2005-07-01 Nick Clifton <nickc@redhat.com>
1144 * sparc.h: Add typedefs to structure declarations.
1146 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1149 * i386.h (i386_optab): Update comments for 64bit addressing on
1150 mov. Allow 64bit addressing for mov and movq.
1152 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1154 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1155 respectively, in various floating-point load and store patterns.
1157 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1159 * hppa.h (FLAG_STRICT): Correct comment.
1160 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1161 PA 2.0 mneumonics when equivalent. Entries with cache control
1162 completers now require PA 1.1. Adjust whitespace.
1164 2005-05-19 Anton Blanchard <anton@samba.org>
1166 * ppc.h (PPC_OPCODE_POWER5): Define.
1168 2005-05-10 Nick Clifton <nickc@redhat.com>
1170 * Update the address and phone number of the FSF organization in
1171 the GPL notices in the following files:
1172 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1173 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1174 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1175 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1176 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1177 tic54x.h, tic80.h, v850.h, vax.h
1179 2005-05-09 Jan Beulich <jbeulich@novell.com>
1181 * i386.h (i386_optab): Add ht and hnt.
1183 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1185 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1186 Add xcrypt-ctr. Provide aliases without hyphens.
1188 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1190 Moved from ../ChangeLog
1192 2005-04-12 Paul Brook <paul@codesourcery.com>
1193 * m88k.h: Rename psr macros to avoid conflicts.
1195 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1196 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1197 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1198 and ARM_ARCH_V6ZKT2.
1200 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1201 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1202 Remove redundant instruction types.
1203 (struct argument): X_op - new field.
1204 (struct cst4_entry): Remove.
1205 (no_op_insn): Declare.
1207 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1208 * crx.h (enum argtype): Rename types, remove unused types.
1210 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1211 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1212 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1213 (enum operand_type): Rearrange operands, edit comments.
1214 replace us<N> with ui<N> for unsigned immediate.
1215 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1216 displacements (respectively).
1217 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1218 (instruction type): Add NO_TYPE_INS.
1219 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1220 (operand_entry): New field - 'flags'.
1221 (operand flags): New.
1223 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1224 * crx.h (operand_type): Remove redundant types i3, i4,
1226 Add new unsigned immediate types us3, us4, us5, us16.
1228 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1230 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1231 adjust them accordingly.
1233 2005-04-01 Jan Beulich <jbeulich@novell.com>
1235 * i386.h (i386_optab): Add rdtscp.
1237 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1239 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1240 between memory and segment register. Allow movq for moving between
1241 general-purpose register and segment register.
1243 2005-02-09 Jan Beulich <jbeulich@novell.com>
1246 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1247 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1250 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1252 * m68k.h (m68008, m68ec030, m68882): Remove.
1254 (cpu_m68k, cpu_cf): New.
1255 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1256 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1258 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1260 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1261 * cgen.h (enum cgen_parse_operand_type): Add
1262 CGEN_PARSE_OPERAND_SYMBOLIC.
1264 2005-01-21 Fred Fish <fnf@specifixinc.com>
1266 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1267 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1268 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1270 2005-01-19 Fred Fish <fnf@specifixinc.com>
1272 * mips.h (struct mips_opcode): Add new pinfo2 member.
1273 (INSN_ALIAS): New define for opcode table entries that are
1274 specific instances of another entry, such as 'move' for an 'or'
1275 with a zero operand.
1276 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1277 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1279 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1281 * mips.h (CPU_RM9000): Define.
1282 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1284 2004-11-25 Jan Beulich <jbeulich@novell.com>
1286 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1287 to/from test registers are illegal in 64-bit mode. Add missing
1288 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1289 (previously one had to explicitly encode a rex64 prefix). Re-enable
1290 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1291 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1293 2004-11-23 Jan Beulich <jbeulich@novell.com>
1295 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1296 available only with SSE2. Change the MMX additions introduced by SSE
1297 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1298 instructions by their now designated identifier (since combining i686
1299 and 3DNow! does not really imply 3DNow!A).
1301 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1303 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1304 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1306 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1307 Vineet Sharma <vineets@noida.hcltech.com>
1309 * maxq.h: New file: Disassembly information for the maxq port.
1311 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1313 * i386.h (i386_optab): Put back "movzb".
1315 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1317 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1318 comments. Remove member cris_ver_sim. Add members
1319 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1320 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1321 (struct cris_support_reg, struct cris_cond15): New types.
1322 (cris_conds15): Declare.
1323 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1324 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1325 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1326 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1327 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1328 SIZE_FIELD_UNSIGNED.
1330 2004-11-04 Jan Beulich <jbeulich@novell.com>
1332 * i386.h (sldx_Suf): Remove.
1333 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1334 (q_FP): Define, implying no REX64.
1335 (x_FP, sl_FP): Imply FloatMF.
1336 (i386_optab): Split reg and mem forms of moving from segment registers
1337 so that the memory forms can ignore the 16-/32-bit operand size
1338 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1339 all non-floating-point instructions. Unite 32- and 64-bit forms of
1340 movsx, movzx, and movd. Adjust floating point operations for the above
1341 changes to the *FP macros. Add DefaultSize to floating point control
1342 insns operating on larger memory ranges. Remove left over comments
1343 hinting at certain insns being Intel-syntax ones where the ones
1344 actually meant are already gone.
1346 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1348 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1351 2004-09-30 Paul Brook <paul@codesourcery.com>
1353 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1354 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1356 2004-09-11 Theodore A. Roth <troth@openavr.org>
1358 * avr.h: Add support for
1359 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1361 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1363 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1365 2004-08-24 Dmitry Diky <diwil@spec.ru>
1367 * msp430.h (msp430_opc): Add new instructions.
1368 (msp430_rcodes): Declare new instructions.
1369 (msp430_hcodes): Likewise..
1371 2004-08-13 Nick Clifton <nickc@redhat.com>
1374 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1377 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1379 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1381 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1383 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1385 2004-07-21 Jan Beulich <jbeulich@novell.com>
1387 * i386.h: Adjust instruction descriptions to better match the
1390 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1392 * arm.h: Remove all old content. Replace with architecture defines
1393 from gas/config/tc-arm.c.
1395 2004-07-09 Andreas Schwab <schwab@suse.de>
1397 * m68k.h: Fix comment.
1399 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1403 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1405 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1407 2004-05-24 Peter Barada <peter@the-baradas.com>
1409 * m68k.h: Add 'size' to m68k_opcode.
1411 2004-05-05 Peter Barada <peter@the-baradas.com>
1413 * m68k.h: Switch from ColdFire chip name to core variant.
1415 2004-04-22 Peter Barada <peter@the-baradas.com>
1417 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1418 descriptions for new EMAC cases.
1419 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1420 handle Motorola MAC syntax.
1421 Allow disassembly of ColdFire V4e object files.
1423 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1425 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1427 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1429 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1431 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1433 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1435 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1437 * i386.h (i386_optab): Added xstore/xcrypt insns.
1439 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1441 * h8300.h (32bit ldc/stc): Add relaxing support.
1443 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1445 * h8300.h (BITOP): Pass MEMRELAX flag.
1447 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1449 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1452 For older changes see ChangeLog-9103
1458 version-control: never