1 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
5 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
7 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
9 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
11 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
12 (aarch64_sys_ins_reg_has_xt): Declare.
14 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
16 * aarch64.h (AARCH64_FEATURE_RAS): New.
17 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
19 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
21 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
23 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
24 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
27 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
29 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
31 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
33 * aarch64.h (aarch64_op): Add OP_BFC.
35 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
37 * aarch64.h (AARCH64_FEATURE_F16): New.
38 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
41 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
43 * aarch64.h (AARCH64_FEATURE_V8_1): New.
44 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
46 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
48 * arm.h (ARM_EXT2_V8_2A): New.
49 (ARM_ARCH_V8_2A): New.
51 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
53 * aarch64.h (AARCH64_FEATURE_V8_2): New.
54 (AARCH64_ARCH_V8_2): New.
56 2015-11-11 Alan Modra <amodra@gmail.com>
57 Peter Bergner <bergner@vnet.ibm.com>
59 * ppc.h (PPC_OPCODE_POWER9): New define.
60 (PPC_OPCODE_VSX3): Likewise.
62 2015-11-02 Nick Clifton <nickc@redhat.com>
64 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
66 2015-11-02 Nick Clifton <nickc@redhat.com>
68 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
70 2015-10-28 Yao Qi <yao.qi@linaro.org>
72 * aarch64.h (aarch64_decode_insn): Update declaration.
74 2015-10-07 Yao Qi <yao.qi@linaro.org>
76 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
79 2015-10-07 Yao Qi <yao.qi@linaro.org>
81 * aarch64.h [__cplusplus]: Wrap in extern "C".
83 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
84 Cupertino Miranda <cmiranda@synopsys.com>
86 * arc-func.h: New file.
89 2015-10-02 Yao Qi <yao.qi@linaro.org>
91 * aarch64.h (aarch64_zero_register_p): Move the declaration
94 2015-10-02 Yao Qi <yao.qi@linaro.org>
96 * aarch64.h (aarch64_decode_insn): Declare it.
98 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
100 * s390.h (S390_INSTR_FLAG_HTM): New flag.
101 (S390_INSTR_FLAG_VX): New flag.
102 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
104 2015-09-23 Nick Clifton <nickc@redhat.com>
106 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
109 2015-09-22 Nick Clifton <nickc@redhat.com>
111 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
113 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
115 * visium.h (gen_reg_table): Make static.
116 (fp_reg_table): Likewise.
117 (cc_table): Likewise.
119 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
121 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
122 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
123 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
124 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
126 2015-07-03 Alan Modra <amodra@gmail.com>
128 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
130 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
131 Cesar Philippidis <cesar@codesourcery.com>
133 * nios2.h (enum iw_format_type): Add R2 formats.
134 (enum overflow_type): Add signed_immed12_overflow and
135 enumeration_overflow for R2.
136 (struct nios2_opcode): Document new argument letters for R2.
137 (REG_3BIT, REG_LDWM, REG_POP): Define.
138 (includes): Include nios2r2.h.
139 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
140 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
141 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
142 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
143 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
144 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
146 * nios2r2.h: New file.
148 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
150 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
151 (ppc_optional_operand_value): New inline function.
153 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
155 * aarch64.h (AARCH64_V8_1): New.
157 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
159 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
160 (ARM_ARCH_V8_1A): New.
161 (ARM_ARCH_V8_1A_FP): New.
162 (ARM_ARCH_V8_1A_SIMD): New.
163 (ARM_ARCH_V8_1A_CRYPTOV1): New.
164 (ARM_FEATURE_CORE): New.
166 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
168 * arm.h (ARM_EXT2_PAN): New.
169 (ARM_FEATURE_CORE_HIGH): New.
171 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
173 * arm.h (ARM_FEATURE_ALL): New.
175 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
177 * aarch64.h (AARCH64_FEATURE_RDMA): New.
179 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
181 * aarch64.h (AARCH64_FEATURE_LOR): New.
183 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
185 * aarch64.h (AARCH64_FEATURE_PAN): New.
186 (aarch64_sys_reg_supported_p): Declare.
187 (aarch64_pstatefield_supported_p): Declare.
189 2015-04-30 DJ Delorie <dj@redhat.com>
191 * rl78.h (RL78_Dis_Isa): New.
192 (rl78_decode_opcode): Add ISA parameter.
194 2015-03-24 Terry Guo <terry.guo@arm.com>
196 * arm.h (arm_feature_set): Extended to provide more available bits.
197 (ARM_ANY): Updated to follow above new definition.
198 (ARM_CPU_HAS_FEATURE): Likewise.
199 (ARM_CPU_IS_ANY): Likewise.
200 (ARM_MERGE_FEATURE_SETS): Likewise.
201 (ARM_CLEAR_FEATURE): Likewise.
202 (ARM_FEATURE): Likewise.
203 (ARM_FEATURE_COPY): New macro.
204 (ARM_FEATURE_EQUAL): Likewise.
205 (ARM_FEATURE_ZERO): Likewise.
206 (ARM_FEATURE_CORE_EQUAL): Likewise.
207 (ARM_FEATURE_LOW): Likewise.
208 (ARM_FEATURE_CORE_LOW): Likewise.
209 (ARM_FEATURE_CORE_COPROC): Likewise.
211 2015-02-19 Pedro Alves <palves@redhat.com>
213 * cgen.h [__cplusplus]: Wrap in extern "C".
214 * msp430-decode.h [__cplusplus]: Likewise.
215 * nios2.h [__cplusplus]: Likewise.
216 * rl78.h [__cplusplus]: Likewise.
217 * rx.h [__cplusplus]: Likewise.
218 * tilegx.h [__cplusplus]: Likewise.
220 2015-01-28 James Bowman <james.bowman@ftdichip.com>
224 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
226 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
228 2015-01-01 Alan Modra <amodra@gmail.com>
230 Update year range in copyright notice of all files.
232 2014-12-27 Anthony Green <green@moxielogic.com>
234 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
235 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
237 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
239 * visium.h: New file.
241 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
243 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
244 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
245 (NIOS2_INSN_OPTARG): Renumber.
247 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
249 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
250 declaration. Fix obsolete comment.
252 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
254 * nios2.h (enum iw_format_type): New.
255 (struct nios2_opcode): Update comments. Add size and format fields.
256 (NIOS2_INSN_OPTARG): New.
257 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
258 (struct nios2_reg): Add regtype field.
259 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
260 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
261 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
262 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
263 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
264 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
265 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
266 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
267 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
268 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
269 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
270 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
271 (OP_MASK_OP, OP_SH_OP): Delete.
272 (OP_MASK_IOP, OP_SH_IOP): Delete.
273 (OP_MASK_IRD, OP_SH_IRD): Delete.
274 (OP_MASK_IRT, OP_SH_IRT): Delete.
275 (OP_MASK_IRS, OP_SH_IRS): Delete.
276 (OP_MASK_ROP, OP_SH_ROP): Delete.
277 (OP_MASK_RRD, OP_SH_RRD): Delete.
278 (OP_MASK_RRT, OP_SH_RRT): Delete.
279 (OP_MASK_RRS, OP_SH_RRS): Delete.
280 (OP_MASK_JOP, OP_SH_JOP): Delete.
281 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
282 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
283 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
284 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
285 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
286 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
287 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
288 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
289 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
290 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
291 (OP_MASK_<insn>, OP_MASK): Delete.
292 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
293 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
294 Include nios2r1.h to define new instruction opcode constants
296 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
297 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
298 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
299 (NUMOPCODES, NUMREGISTERS): Delete.
300 * nios2r1.h: New file.
302 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
304 * sparc.h (HWCAP2_VIS3B): Documentation improved.
306 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
308 * sparc.h (sparc_opcode): new field `hwcaps2'.
309 (HWCAP2_FJATHPLUS): New define.
310 (HWCAP2_VIS3B): Likewise.
311 (HWCAP2_ADP): Likewise.
312 (HWCAP2_SPARC5): Likewise.
313 (HWCAP2_MWAIT): Likewise.
314 (HWCAP2_XMPMUL): Likewise.
315 (HWCAP2_XMONT): Likewise.
316 (HWCAP2_NSEC): Likewise.
317 (HWCAP2_FJATHHPC): Likewise.
318 (HWCAP2_FJDES): Likewise.
319 (HWCAP2_FJAES): Likewise.
320 Document the new operand kind `{', corresponding to the mcdper
321 ancillary state register.
322 Document the new operand kind }, which represents frsd floating
323 point registers (double precision) which must be the same than
324 frs1 in its containing instruction.
326 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
328 * nds32.h: Add new opcode declaration.
330 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
331 Matthew Fortune <matthew.fortune@imgtec.com>
333 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
334 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
335 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
336 +I, +O, +R, +:, +\, +", +;
337 (mips_check_prev_operand): New struct.
338 (INSN2_FORBIDDEN_SLOT): New define.
339 (INSN_ISA32R6): New define.
340 (INSN_ISA64R6): New define.
341 (INSN_UPTO32R6): New define.
342 (INSN_UPTO64R6): New define.
343 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
344 (ISA_MIPS32R6): New define.
345 (ISA_MIPS64R6): New define.
346 (CPU_MIPS32R6): New define.
347 (CPU_MIPS64R6): New define.
348 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
350 2014-09-03 Jiong Wang <jiong.wang@arm.com>
352 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
353 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
354 (aarch64_insn_class): Add lse_atomic.
355 (F_LSE_SZ): New field added.
356 (opcode_has_special_coder): Recognize F_LSE_SZ.
358 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
360 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
363 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
365 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
366 (INSN_LOAD_COPROC): New define.
367 (INSN_COPROC_MOVE_DELAY): Rename to...
368 (INSN_COPROC_MOVE): New define.
370 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
371 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
372 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
373 Soundararajan <Sounderarajan.D@atmel.com>
375 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
376 (AVR_ISA_2xxxa): Define ISA without LPM.
377 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
378 Add doc for contraint used in 16 bit lds/sts.
379 Adjust ISA group for icall, ijmp, pop and push.
380 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
382 2014-05-19 Nick Clifton <nickc@redhat.com>
384 * msp430.h (struct msp430_operand_s): Add vshift field.
386 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
388 * mips.h (INSN_ISA_MASK): Updated.
389 (INSN_ISA32R3): New define.
390 (INSN_ISA32R5): New define.
391 (INSN_ISA64R3): New define.
392 (INSN_ISA64R5): New define.
393 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
394 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
395 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
397 (INSN_UPTO32R3): New define.
398 (INSN_UPTO32R5): New define.
399 (INSN_UPTO64R3): New define.
400 (INSN_UPTO64R5): New define.
401 (ISA_MIPS32R3): New define.
402 (ISA_MIPS32R5): New define.
403 (ISA_MIPS64R3): New define.
404 (ISA_MIPS64R5): New define.
405 (CPU_MIPS32R3): New define.
406 (CPU_MIPS32R5): New define.
407 (CPU_MIPS64R3): New define.
408 (CPU_MIPS64R5): New define.
410 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
412 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
414 2014-04-22 Christian Svensson <blue@cmd.nu>
418 2014-03-05 Alan Modra <amodra@gmail.com>
420 Update copyright years.
422 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
424 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
427 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
428 Wei-Cheng Wang <cole945@gmail.com>
430 * nds32.h: New file for Andes NDS32.
432 2013-12-07 Mike Frysinger <vapier@gentoo.org>
434 * bfin.h: Remove +x file mode.
436 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
438 * aarch64.h (aarch64_pstatefields): Change element type to
441 2013-11-18 Renlin Li <Renlin.Li@arm.com>
443 * arm.h (ARM_AEXT_V7VE): New define.
444 (ARM_ARCH_V7VE): New define.
445 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
447 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
451 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
453 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
454 (aarch64_sys_reg_writeonly_p): Ditto.
456 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
458 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
459 (aarch64_sys_reg_writeonly_p): Ditto.
461 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
463 * aarch64.h (aarch64_sys_reg): New typedef.
464 (aarch64_sys_regs): Change to define with the new type.
465 (aarch64_sys_reg_deprecated_p): Declare.
467 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
469 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
470 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
472 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
474 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
475 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
476 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
477 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
478 For MIPS, update extension character sequences after +.
479 (ASE_MSA): New define.
480 (ASE_MSA64): New define.
481 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
482 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
483 For microMIPS, update extension character sequences after +.
485 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
490 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
492 * mips.h: Remove references to "+I" and imm2_expr.
494 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
496 * mips.h (M_DEXT, M_DINS): Delete.
498 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
500 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
501 (mips_optional_operand_p): New function.
503 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
504 Richard Sandiford <rdsandiford@googlemail.com>
506 * mips.h: Document new VU0 operand characters.
507 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
508 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
509 (OP_REG_R5900_ACC): New mips_reg_operand_types.
510 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
511 (mips_vu0_channel_mask): Declare.
513 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
515 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
516 (mips_int_operand_min, mips_int_operand_max): New functions.
517 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
519 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
521 * mips.h (mips_decode_reg_operand): New function.
522 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
523 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
524 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
526 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
527 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
528 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
529 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
530 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
531 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
532 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
533 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
534 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
535 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
536 macros to cover the gaps.
537 (INSN2_MOD_SP): Replace with...
538 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
539 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
540 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
541 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
542 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
545 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
547 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
548 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
549 (MIPS16_INSN_COND_BRANCH): Delete.
551 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
552 Kirill Yukhin <kirill.yukhin@intel.com>
553 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
555 * i386.h (BND_PREFIX_OPCODE): New.
557 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
559 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
560 OP_SAVE_RESTORE_LIST.
561 (decode_mips16_operand): Declare.
563 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
565 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
566 (mips_operand, mips_int_operand, mips_mapped_int_operand)
567 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
568 (mips_pcrel_operand): New structures.
569 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
570 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
571 (decode_mips_operand, decode_micromips_operand): Declare.
573 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
575 * mips.h: Document MIPS16 "I" opcode.
577 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
579 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
580 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
581 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
582 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
583 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
584 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
585 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
586 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
587 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
588 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
589 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
590 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
591 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
593 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
594 (M_USD_AB): ...these.
596 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
598 * mips.h: Remove documentation of "[" and "]". Update documentation
599 of "k" and the MDMX formats.
601 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
603 * mips.h: Update documentation of "+s" and "+S".
605 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
607 * mips.h: Document "+i".
609 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
611 * mips.h: Remove "mi" documentation. Update "mh" documentation.
612 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
614 (INSN2_WRITE_GPR_MHI): Rename to...
615 (INSN2_WRITE_GPR_MH): ...this.
617 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
619 * mips.h: Remove documentation of "+D" and "+T".
621 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
623 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
624 Use "source" rather than "destination" for microMIPS "G".
626 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
628 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
631 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
633 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
635 2013-06-17 Catherine Moore <clm@codesourcery.com>
636 Maciej W. Rozycki <macro@codesourcery.com>
637 Chao-Ying Fu <fu@mips.com>
639 * mips.h (OP_SH_EVAOFFSET): Define.
640 (OP_MASK_EVAOFFSET): Define.
641 (INSN_ASE_MASK): Delete.
643 (M_CACHEE_AB, M_CACHEE_OB): New.
644 (M_LBE_OB, M_LBE_AB): New.
645 (M_LBUE_OB, M_LBUE_AB): New.
646 (M_LHE_OB, M_LHE_AB): New.
647 (M_LHUE_OB, M_LHUE_AB): New.
648 (M_LLE_AB, M_LLE_OB): New.
649 (M_LWE_OB, M_LWE_AB): New.
650 (M_LWLE_AB, M_LWLE_OB): New.
651 (M_LWRE_AB, M_LWRE_OB): New.
652 (M_PREFE_AB, M_PREFE_OB): New.
653 (M_SCE_AB, M_SCE_OB): New.
654 (M_SBE_OB, M_SBE_AB): New.
655 (M_SHE_OB, M_SHE_AB): New.
656 (M_SWE_OB, M_SWE_AB): New.
657 (M_SWLE_AB, M_SWLE_OB): New.
658 (M_SWRE_AB, M_SWRE_OB): New.
659 (MICROMIPSOP_SH_EVAOFFSET): Define.
660 (MICROMIPSOP_MASK_EVAOFFSET): Define.
662 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
664 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
666 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
668 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
670 2013-05-09 Andrew Pinski <apinski@cavium.com>
672 * mips.h (OP_MASK_CODE10): Correct definition.
673 (OP_SH_CODE10): Likewise.
674 Add a comment that "+J" is used now for OP_*CODE10.
675 (INSN_ASE_MASK): Update.
676 (INSN_VIRT): New macro.
677 (INSN_VIRT64): New macro
679 2013-05-02 Nick Clifton <nickc@redhat.com>
681 * msp430.h: Add patterns for MSP430X instructions.
683 2013-04-06 David S. Miller <davem@davemloft.net>
685 * sparc.h (F_PREFERRED): Define.
686 (F_PREF_ALIAS): Define.
688 2013-04-03 Nick Clifton <nickc@redhat.com>
690 * v850.h (V850_INVERSE_PCREL): Define.
692 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
695 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
697 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
700 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
702 * tic6xc-opcode-table.h: Add 16-bit insns.
703 * tic6x.h: Add support for 16-bit insns.
705 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
707 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
708 and mov.b/w/l Rs,@(d:32,ERd).
710 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
713 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
714 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
715 tic6x_operand_xregpair operand coding type.
716 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
717 opcode field, usu ORXREGD1324 for the src2 operand and remove the
720 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
723 * tic6x.h (enum tic6x_coding_method): Add
724 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
725 separately the msb and lsb of a register pair. This is needed to
726 encode the opcodes in the same way as TI assembler does.
727 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
728 and rsqrdp opcodes to use the new field coding types.
730 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
732 * arm.h (CRC_EXT_ARMV8): New constant.
733 (ARCH_CRC_ARMV8): New macro.
735 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
737 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
739 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
740 Andrew Jenner <andrew@codesourcery.com>
742 Based on patches from Altera Corporation.
746 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
748 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
750 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
753 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
755 2013-01-24 Nick Clifton <nickc@redhat.com>
757 * v850.h: Add e3v5 support.
759 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
761 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
763 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
765 * ppc.h (PPC_OPCODE_POWER8): New define.
766 (PPC_OPCODE_HTM): Likewise.
768 2013-01-10 Will Newton <will.newton@imgtec.com>
772 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
774 * cr16.h (make_instruction): Rename to cr16_make_instruction.
775 (match_opcode): Rename to cr16_match_opcode.
777 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
779 * mips.h: Add support for r5900 instructions including lq and sq.
781 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
783 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
784 (make_instruction,match_opcode): Added function prototypes.
785 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
787 2012-11-23 Alan Modra <amodra@gmail.com>
789 * ppc.h (ppc_parse_cpu): Update prototype.
791 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
793 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
794 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
796 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
798 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
800 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
802 * ia64.h (ia64_opnd): Add new operand types.
804 2012-08-21 David S. Miller <davem@davemloft.net>
806 * sparc.h (F3F4): New macro.
808 2012-08-13 Ian Bolton <ian.bolton@arm.com>
809 Laurent Desnogues <laurent.desnogues@arm.com>
810 Jim MacArthur <jim.macarthur@arm.com>
811 Marcus Shawcroft <marcus.shawcroft@arm.com>
812 Nigel Stephens <nigel.stephens@arm.com>
813 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
814 Richard Earnshaw <rearnsha@arm.com>
815 Sofiane Naci <sofiane.naci@arm.com>
816 Tejas Belagod <tejas.belagod@arm.com>
817 Yufeng Zhang <yufeng.zhang@arm.com>
819 * aarch64.h: New file.
821 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
822 Maciej W. Rozycki <macro@codesourcery.com>
824 * mips.h (mips_opcode): Add the exclusions field.
825 (OPCODE_IS_MEMBER): Remove macro.
826 (cpu_is_member): New inline function.
827 (opcode_is_member): Likewise.
829 2012-07-31 Chao-Ying Fu <fu@mips.com>
830 Catherine Moore <clm@codesourcery.com>
831 Maciej W. Rozycki <macro@codesourcery.com>
833 * mips.h: Document microMIPS DSP ASE usage.
834 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
835 microMIPS DSP ASE support.
836 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
837 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
838 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
839 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
840 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
841 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
842 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
844 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
846 * mips.h: Fix a typo in description.
848 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
850 * avr.h: (AVR_ISA_XCH): New define.
851 (AVR_ISA_XMEGA): Use it.
852 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
854 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
856 * m68hc11.h: Add XGate definitions.
857 (struct m68hc11_opcode): Add xg_mask field.
859 2012-05-14 Catherine Moore <clm@codesourcery.com>
860 Maciej W. Rozycki <macro@codesourcery.com>
861 Rhonda Wittels <rhonda@codesourcery.com>
863 * ppc.h (PPC_OPCODE_VLE): New definition.
864 (PPC_OP_SA): New macro.
865 (PPC_OP_SE_VLE): New macro.
866 (PPC_OP): Use a variable shift amount.
867 (powerpc_operand): Update comments.
868 (PPC_OPSHIFT_INV): New macro.
869 (PPC_OPERAND_CR): Replace with...
870 (PPC_OPERAND_CR_BIT): ...this and
871 (PPC_OPERAND_CR_REG): ...this.
874 2012-05-03 Sean Keys <skeys@ipdatasys.com>
876 * xgate.h: Header file for XGATE assembler.
878 2012-04-27 David S. Miller <davem@davemloft.net>
880 * sparc.h: Document new arg code' )' for crypto RS3
883 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
884 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
885 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
886 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
887 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
888 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
889 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
890 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
891 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
892 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
893 HWCAP_CBCOND, HWCAP_CRC32): New defines.
895 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
897 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
899 2012-02-27 Alan Modra <amodra@gmail.com>
901 * crx.h (cst4_map): Update declaration.
903 2012-02-25 Walter Lee <walt@tilera.com>
905 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
907 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
908 TILEPRO_OPC_LW_TLS_SN.
910 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
912 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
913 (XRELEASE_PREFIX_OPCODE): Likewise.
915 2011-12-08 Andrew Pinski <apinski@cavium.com>
916 Adam Nemet <anemet@caviumnetworks.com>
918 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
919 (INSN_OCTEON2): New macro.
920 (CPU_OCTEON2): New macro.
921 (OPCODE_IS_MEMBER): Add Octeon2.
923 2011-11-29 Andrew Pinski <apinski@cavium.com>
925 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
926 (INSN_OCTEONP): New macro.
927 (CPU_OCTEONP): New macro.
928 (OPCODE_IS_MEMBER): Add Octeon+.
929 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
931 2011-11-01 DJ Delorie <dj@redhat.com>
935 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
937 * mips.h: Fix a typo in description.
939 2011-09-21 David S. Miller <davem@davemloft.net>
941 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
942 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
943 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
944 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
946 2011-08-09 Chao-ying Fu <fu@mips.com>
947 Maciej W. Rozycki <macro@codesourcery.com>
949 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
950 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
951 (INSN_ASE_MASK): Add the MCU bit.
952 (INSN_MCU): New macro.
953 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
954 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
956 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
958 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
959 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
960 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
961 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
962 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
963 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
964 (INSN2_READ_GPR_MMN): Likewise.
965 (INSN2_READ_FPR_D): Change the bit used.
966 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
967 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
968 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
969 (INSN2_COND_BRANCH): Likewise.
970 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
971 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
972 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
973 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
974 (INSN2_MOD_GPR_MN): Likewise.
976 2011-08-05 David S. Miller <davem@davemloft.net>
978 * sparc.h: Document new format codes '4', '5', and '('.
979 (OPF_LOW4, RS3): New macros.
981 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
983 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
984 order of flags documented.
986 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
988 * mips.h: Clarify the description of microMIPS instruction
990 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
992 2011-07-24 Chao-ying Fu <fu@mips.com>
993 Maciej W. Rozycki <macro@codesourcery.com>
995 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
996 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
997 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
998 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
999 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1000 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1001 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1002 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1003 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1004 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1005 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1006 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1007 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1008 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1009 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1010 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1011 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1012 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1013 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1014 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1015 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1016 (INSN_WRITE_GPR_S): New macro.
1017 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1018 (INSN2_READ_FPR_D): Likewise.
1019 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1020 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1021 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1022 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1023 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1024 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1025 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1026 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1027 (CPU_MICROMIPS): New macro.
1028 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1029 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1030 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1031 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1032 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1033 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1034 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1035 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1036 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1037 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1038 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1039 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1040 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1041 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1042 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1043 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1044 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1045 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1046 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1047 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1048 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1049 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1050 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1051 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1052 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1053 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1054 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1055 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1056 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1057 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1058 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1059 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1060 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1061 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1062 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1063 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1064 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1065 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1066 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1067 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1068 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1069 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1070 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1071 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1072 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1073 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1074 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1075 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1076 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1077 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1078 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1079 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1080 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1081 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1082 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1083 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1084 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1085 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1086 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1087 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1088 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1089 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1090 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1091 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1092 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1093 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1094 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1095 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1096 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1097 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1098 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1099 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1100 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1101 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1102 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1103 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1104 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1105 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1106 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1107 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1108 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1109 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1110 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1111 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1112 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1113 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1114 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1115 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1116 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1117 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1118 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1119 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1120 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1121 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1122 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1123 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1124 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1125 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1126 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1127 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1128 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1129 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1130 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1131 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1132 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1133 (micromips_opcodes): New declaration.
1134 (bfd_micromips_num_opcodes): Likewise.
1136 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1138 * mips.h (INSN_TRAP): Rename to...
1139 (INSN_NO_DELAY_SLOT): ... this.
1140 (INSN_SYNC): Remove macro.
1142 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1144 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1145 a duplicate of AVR_ISA_SPM.
1147 2011-07-01 Nick Clifton <nickc@redhat.com>
1149 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1151 2011-06-18 Robin Getz <robin.getz@analog.com>
1153 * bfin.h (is_macmod_signed): New func
1155 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1157 * bfin.h (is_macmod_pmove): Add missing space before func args.
1158 (is_macmod_hmove): Likewise.
1160 2011-06-13 Walter Lee <walt@tilera.com>
1162 * tilegx.h: New file.
1163 * tilepro.h: New file.
1165 2011-05-31 Paul Brook <paul@codesourcery.com>
1167 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1169 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1171 * s390.h: Replace S390_OPERAND_REG_EVEN with
1172 S390_OPERAND_REG_PAIR.
1174 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1176 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1178 2011-04-18 Julian Brown <julian@codesourcery.com>
1180 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1182 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1185 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1187 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1189 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1190 New instruction set flags.
1191 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1193 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1195 * mips.h (M_PREF_AB): New enum value.
1197 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1199 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1201 (is_macmod_pmove, is_macmod_hmove): New functions.
1203 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1205 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1207 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1209 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1210 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1212 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1215 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1218 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1221 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1223 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1225 * mips.h: Update commentary after last commit.
1227 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1229 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1230 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1231 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1233 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1235 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1237 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1239 * mips.h: Fix previous commit.
1241 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1243 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1244 (INSN_LOONGSON_3A): Clear bit 31.
1246 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1249 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1250 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1251 (ARM_ARCH_V6M_ONLY): New define.
1253 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1255 * mips.h (INSN_LOONGSON_3A): Defined.
1256 (CPU_LOONGSON_3A): Defined.
1257 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1259 2010-10-09 Matt Rice <ratmice@gmail.com>
1261 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1262 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1264 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1266 * arm.h (ARM_EXT_VIRT): New define.
1267 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1268 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1271 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1273 * arm.h (ARM_AEXT_ADIV): New define.
1274 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1276 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1278 * arm.h (ARM_EXT_OS): New define.
1279 (ARM_AEXT_V6SM): Likewise.
1280 (ARM_ARCH_V6SM): Likewise.
1282 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1284 * arm.h (ARM_EXT_MP): Add.
1285 (ARM_ARCH_V7A_MP): Likewise.
1287 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1289 * bfin.h: Declare pseudoChr structs/defines.
1291 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1293 * bfin.h: Strip trailing whitespace.
1295 2010-07-29 DJ Delorie <dj@redhat.com>
1297 * rx.h (RX_Operand_Type): Add TwoReg.
1298 (RX_Opcode_ID): Remove ediv and ediv2.
1300 2010-07-27 DJ Delorie <dj@redhat.com>
1302 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1304 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1305 Ina Pandit <ina.pandit@kpitcummins.com>
1307 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1308 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1309 PROCESSOR_V850E2_ALL.
1310 Remove PROCESSOR_V850EA support.
1311 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1312 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1313 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1314 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1315 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1316 V850_OPERAND_PERCENT.
1317 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1319 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1322 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1324 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1325 (MIPS16_INSN_BRANCH): Rename to...
1326 (MIPS16_INSN_COND_BRANCH): ... this.
1328 2010-07-03 Alan Modra <amodra@gmail.com>
1330 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1331 Renumber other PPC_OPCODE defines.
1333 2010-07-03 Alan Modra <amodra@gmail.com>
1335 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1337 2010-06-29 Alan Modra <amodra@gmail.com>
1339 * maxq.h: Delete file.
1341 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1343 * ppc.h (PPC_OPCODE_E500): Define.
1345 2010-05-26 Catherine Moore <clm@codesourcery.com>
1347 * opcode/mips.h (INSN_MIPS16): Remove.
1349 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1351 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1353 2010-04-15 Nick Clifton <nickc@redhat.com>
1355 * alpha.h: Update copyright notice to use GPLv3.
1361 * convex.h: Likewise.
1368 * h8300.h: Likewise.
1375 * m68hc11.h: Likewise.
1381 * mn10200.h: Likewise.
1382 * mn10300.h: Likewise.
1383 * msp430.h: Likewise.
1385 * ns32k.h: Likewise.
1387 * pdp11.h: Likewise.
1394 * score-datadep.h: Likewise.
1395 * score-inst.h: Likewise.
1396 * sparc.h: Likewise.
1397 * spu-insns.h: Likewise.
1399 * tic30.h: Likewise.
1400 * tic4x.h: Likewise.
1401 * tic54x.h: Likewise.
1402 * tic80.h: Likewise.
1406 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1408 * tic6x-control-registers.h, tic6x-insn-formats.h,
1409 tic6x-opcode-table.h, tic6x.h: New.
1411 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1413 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1415 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1417 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1419 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1421 * ia64.h (ia64_find_opcode): Remove argument name.
1422 (ia64_find_next_opcode): Likewise.
1423 (ia64_dis_opcode): Likewise.
1424 (ia64_free_opcode): Likewise.
1425 (ia64_find_dependency): Likewise.
1427 2009-11-22 Doug Evans <dje@sebabeach.org>
1429 * cgen.h: Include bfd_stdint.h.
1430 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1432 2009-11-18 Paul Brook <paul@codesourcery.com>
1434 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1436 2009-11-17 Paul Brook <paul@codesourcery.com>
1437 Daniel Jacobowitz <dan@codesourcery.com>
1439 * arm.h (ARM_EXT_V6_DSP): Define.
1440 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1441 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1443 2009-11-04 DJ Delorie <dj@redhat.com>
1445 * rx.h (rx_decode_opcode) (mvtipl): Add.
1446 (mvtcp, mvfcp, opecp): Remove.
1448 2009-11-02 Paul Brook <paul@codesourcery.com>
1450 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1451 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1452 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1453 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1454 FPU_ARCH_NEON_VFP_V4): Define.
1456 2009-10-23 Doug Evans <dje@sebabeach.org>
1458 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1459 * cgen.h: Update. Improve multi-inclusion macro name.
1461 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1463 * ppc.h (PPC_OPCODE_476): Define.
1465 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1467 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1469 2009-09-29 DJ Delorie <dj@redhat.com>
1473 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1475 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1477 2009-09-21 Ben Elliston <bje@au.ibm.com>
1479 * ppc.h (PPC_OPCODE_PPCA2): New.
1481 2009-09-05 Martin Thuresson <martin@mtme.org>
1483 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1485 2009-08-29 Martin Thuresson <martin@mtme.org>
1487 * tic30.h (template): Rename type template to
1488 insn_template. Updated code to use new name.
1489 * tic54x.h (template): Rename type template to
1492 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1494 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1496 2009-06-11 Anthony Green <green@moxielogic.com>
1498 * moxie.h (MOXIE_F3_PCREL): Define.
1499 (moxie_form3_opc_info): Grow.
1501 2009-06-06 Anthony Green <green@moxielogic.com>
1503 * moxie.h (MOXIE_F1_M): Define.
1505 2009-04-15 Anthony Green <green@moxielogic.com>
1509 2009-04-06 DJ Delorie <dj@redhat.com>
1511 * h8300.h: Add relaxation attributes to MOVA opcodes.
1513 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1515 * ppc.h (ppc_parse_cpu): Declare.
1517 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1519 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1520 and _IMM11 for mbitclr and mbitset.
1521 * score-datadep.h: Update dependency information.
1523 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1525 * ppc.h (PPC_OPCODE_POWER7): New.
1527 2009-02-06 Doug Evans <dje@google.com>
1529 * i386.h: Add comment regarding sse* insns and prefixes.
1531 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1533 * mips.h (INSN_XLR): Define.
1534 (INSN_CHIP_MASK): Update.
1536 (OPCODE_IS_MEMBER): Update.
1537 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1539 2009-01-28 Doug Evans <dje@google.com>
1541 * opcode/i386.h: Add multiple inclusion protection.
1542 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1543 (EDI_REG_NUM): New macros.
1544 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1545 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1546 (REX_PREFIX_P): New macro.
1548 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1550 * ppc.h (struct powerpc_opcode): New field "deprecated".
1551 (PPC_OPCODE_NOPOWER4): Delete.
1553 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1555 * mips.h: Define CPU_R14000, CPU_R16000.
1556 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1558 2008-11-18 Catherine Moore <clm@codesourcery.com>
1560 * arm.h (FPU_NEON_FP16): New.
1561 (FPU_ARCH_NEON_FP16): New.
1563 2008-11-06 Chao-ying Fu <fu@mips.com>
1565 * mips.h: Doucument '1' for 5-bit sync type.
1567 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1569 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1572 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1574 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1576 2008-07-30 Michael J. Eager <eager@eagercon.com>
1578 * ppc.h (PPC_OPCODE_405): Define.
1579 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1581 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1583 * ppc.h (ppc_cpu_t): New typedef.
1584 (struct powerpc_opcode <flags>): Use it.
1585 (struct powerpc_operand <insert, extract>): Likewise.
1586 (struct powerpc_macro <flags>): Likewise.
1588 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1590 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1591 Update comment before MIPS16 field descriptors to mention MIPS16.
1592 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1594 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1595 New bit masks and shift counts for cins and exts.
1597 * mips.h: Document new field descriptors +Q.
1598 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1600 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1602 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1603 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1605 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1607 * ppc.h: (PPC_OPCODE_E500MC): New.
1609 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1611 * i386.h (MAX_OPERANDS): Set to 5.
1612 (MAX_MNEM_SIZE): Changed to 20.
1614 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1616 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1618 2008-03-09 Paul Brook <paul@codesourcery.com>
1620 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1622 2008-03-04 Paul Brook <paul@codesourcery.com>
1624 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1625 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1626 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1628 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1629 Nick Clifton <nickc@redhat.com>
1632 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1633 with a 32-bit displacement but without the top bit of the 4th byte
1636 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1638 * cr16.h (cr16_num_optab): Declared.
1640 2008-02-14 Hakan Ardo <hakan@debian.org>
1643 * avr.h (AVR_ISA_2xxe): Define.
1645 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1647 * mips.h: Update copyright.
1648 (INSN_CHIP_MASK): New macro.
1649 (INSN_OCTEON): New macro.
1650 (CPU_OCTEON): New macro.
1651 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1653 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1655 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1657 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1659 * avr.h (AVR_ISA_USB162): Add new opcode set.
1660 (AVR_ISA_AVR3): Likewise.
1662 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1664 * mips.h (INSN_LOONGSON_2E): New.
1665 (INSN_LOONGSON_2F): New.
1666 (CPU_LOONGSON_2E): New.
1667 (CPU_LOONGSON_2F): New.
1668 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1670 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1672 * mips.h (INSN_ISA*): Redefine certain values as an
1673 enumeration. Update comments.
1674 (mips_isa_table): New.
1675 (ISA_MIPS*): Redefine to match enumeration.
1676 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1679 2007-08-08 Ben Elliston <bje@au.ibm.com>
1681 * ppc.h (PPC_OPCODE_PPCPS): New.
1683 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1685 * m68k.h: Document j K & E.
1687 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1689 * cr16.h: New file for CR16 target.
1691 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1693 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1695 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1697 * m68k.h (mcfisa_c): New.
1698 (mcfusp, mcf_mask): Adjust.
1700 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1702 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1703 (num_powerpc_operands): Declare.
1704 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1705 (PPC_OPERAND_PLUS1): Define.
1707 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1709 * i386.h (REX_MODE64): Renamed to ...
1711 (REX_EXTX): Renamed to ...
1713 (REX_EXTY): Renamed to ...
1715 (REX_EXTZ): Renamed to ...
1718 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1720 * i386.h: Add entries from config/tc-i386.h and move tables
1721 to opcodes/i386-opc.h.
1723 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1725 * i386.h (FloatDR): Removed.
1726 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1728 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1730 * spu-insns.h: Add soma double-float insns.
1732 2007-02-20 Thiemo Seufer <ths@mips.com>
1733 Chao-Ying Fu <fu@mips.com>
1735 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1736 (INSN_DSPR2): Add flag for DSP R2 instructions.
1737 (M_BALIGN): New macro.
1739 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1741 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1742 and Seg3ShortFrom with Shortform.
1744 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386.h (i386_optab): Put the real "test" before the pseudo
1750 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1752 * m68k.h (m68010up): OR fido_a.
1754 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1756 * m68k.h (fido_a): New.
1758 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1760 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1761 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1764 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1766 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1768 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1770 * score-inst.h (enum score_insn_type): Add Insn_internal.
1772 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1773 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1774 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1775 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1776 Alan Modra <amodra@bigpond.net.au>
1778 * spu-insns.h: New file.
1781 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1783 * ppc.h (PPC_OPCODE_CELL): Define.
1785 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1787 * i386.h : Modify opcode to support for the change in POPCNT opcode
1788 in amdfam10 architecture.
1790 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1792 * i386.h: Replace CpuMNI with CpuSSSE3.
1794 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1795 Joseph Myers <joseph@codesourcery.com>
1796 Ian Lance Taylor <ian@wasabisystems.com>
1797 Ben Elliston <bje@wasabisystems.com>
1799 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1801 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1803 * score-datadep.h: New file.
1804 * score-inst.h: New file.
1806 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1808 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1809 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1810 movdq2q and movq2dq.
1812 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1813 Michael Meissner <michael.meissner@amd.com>
1815 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1817 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1819 * i386.h (i386_optab): Add "nop" with memory reference.
1821 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1823 * i386.h (i386_optab): Update comment for 64bit NOP.
1825 2006-06-06 Ben Elliston <bje@au.ibm.com>
1826 Anton Blanchard <anton@samba.org>
1828 * ppc.h (PPC_OPCODE_POWER6): Define.
1831 2006-06-05 Thiemo Seufer <ths@mips.com>
1833 * mips.h: Improve description of MT flags.
1835 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1837 * m68k.h (mcf_mask): Define.
1839 2006-05-05 Thiemo Seufer <ths@mips.com>
1840 David Ung <davidu@mips.com>
1842 * mips.h (enum): Add macro M_CACHE_AB.
1844 2006-05-04 Thiemo Seufer <ths@mips.com>
1845 Nigel Stephens <nigel@mips.com>
1846 David Ung <davidu@mips.com>
1848 * mips.h: Add INSN_SMARTMIPS define.
1850 2006-04-30 Thiemo Seufer <ths@mips.com>
1851 David Ung <davidu@mips.com>
1853 * mips.h: Defines udi bits and masks. Add description of
1854 characters which may appear in the args field of udi
1857 2006-04-26 Thiemo Seufer <ths@networkno.de>
1859 * mips.h: Improve comments describing the bitfield instruction
1862 2006-04-26 Julian Brown <julian@codesourcery.com>
1864 * arm.h (FPU_VFP_EXT_V3): Define constant.
1865 (FPU_NEON_EXT_V1): Likewise.
1866 (FPU_VFP_HARD): Update.
1867 (FPU_VFP_V3): Define macro.
1868 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1870 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1872 * avr.h (AVR_ISA_PWMx): New.
1874 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1876 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1877 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1878 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1879 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1880 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1882 2006-03-10 Paul Brook <paul@codesourcery.com>
1884 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1886 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1888 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1889 first. Correct mask of bb "B" opcode.
1891 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1893 * i386.h (i386_optab): Support Intel Merom New Instructions.
1895 2006-02-24 Paul Brook <paul@codesourcery.com>
1897 * arm.h: Add V7 feature bits.
1899 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1901 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1903 2006-01-31 Paul Brook <paul@codesourcery.com>
1904 Richard Earnshaw <rearnsha@arm.com>
1906 * arm.h: Use ARM_CPU_FEATURE.
1907 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1908 (arm_feature_set): Change to a structure.
1909 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1910 ARM_FEATURE): New macros.
1912 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1914 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1915 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1916 (ADD_PC_INCR_OPCODE): Don't define.
1918 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1921 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1923 2005-11-14 David Ung <davidu@mips.com>
1925 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1926 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1927 save/restore encoding of the args field.
1929 2005-10-28 Dave Brolley <brolley@redhat.com>
1931 Contribute the following changes:
1932 2005-02-16 Dave Brolley <brolley@redhat.com>
1934 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1935 cgen_isa_mask_* to cgen_bitset_*.
1938 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1940 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1941 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1942 (CGEN_CPU_TABLE): Make isas a ponter.
1944 2003-09-29 Dave Brolley <brolley@redhat.com>
1946 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1947 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1948 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1950 2002-12-13 Dave Brolley <brolley@redhat.com>
1952 * cgen.h (symcat.h): #include it.
1953 (cgen-bitset.h): #include it.
1954 (CGEN_ATTR_VALUE_TYPE): Now a union.
1955 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1956 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1957 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1958 * cgen-bitset.h: New file.
1960 2005-09-30 Catherine Moore <clm@cm00re.com>
1964 2005-10-24 Jan Beulich <jbeulich@novell.com>
1966 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1969 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1971 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1972 Add FLAG_STRICT to pa10 ftest opcode.
1974 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1976 * hppa.h (pa_opcodes): Remove lha entries.
1978 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1980 * hppa.h (FLAG_STRICT): Revise comment.
1981 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1982 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1985 2005-09-30 Catherine Moore <clm@cm00re.com>
1989 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1991 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1993 2005-09-06 Chao-ying Fu <fu@mips.com>
1995 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1996 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1998 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1999 (INSN_ASE_MASK): Update to include INSN_MT.
2000 (INSN_MT): New define for MT ASE.
2002 2005-08-25 Chao-ying Fu <fu@mips.com>
2004 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2005 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2006 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2007 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2008 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2009 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2011 (INSN_DSP): New define for DSP ASE.
2013 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2017 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2019 * ppc.h (PPC_OPCODE_E300): Define.
2021 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2023 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2025 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2028 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2031 2005-07-27 Jan Beulich <jbeulich@novell.com>
2033 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2034 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2035 Add movq-s as 64-bit variants of movd-s.
2037 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2039 * hppa.h: Fix punctuation in comment.
2041 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2042 implicit space-register addressing. Set space-register bits on opcodes
2043 using implicit space-register addressing. Add various missing pa20
2044 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2045 space-register addressing. Use "fE" instead of "fe" in various
2048 2005-07-18 Jan Beulich <jbeulich@novell.com>
2050 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2052 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2054 * i386.h (i386_optab): Support Intel VMX Instructions.
2056 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2058 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2060 2005-07-05 Jan Beulich <jbeulich@novell.com>
2062 * i386.h (i386_optab): Add new insns.
2064 2005-07-01 Nick Clifton <nickc@redhat.com>
2066 * sparc.h: Add typedefs to structure declarations.
2068 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2071 * i386.h (i386_optab): Update comments for 64bit addressing on
2072 mov. Allow 64bit addressing for mov and movq.
2074 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2076 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2077 respectively, in various floating-point load and store patterns.
2079 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2081 * hppa.h (FLAG_STRICT): Correct comment.
2082 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2083 PA 2.0 mneumonics when equivalent. Entries with cache control
2084 completers now require PA 1.1. Adjust whitespace.
2086 2005-05-19 Anton Blanchard <anton@samba.org>
2088 * ppc.h (PPC_OPCODE_POWER5): Define.
2090 2005-05-10 Nick Clifton <nickc@redhat.com>
2092 * Update the address and phone number of the FSF organization in
2093 the GPL notices in the following files:
2094 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2095 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2096 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2097 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2098 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2099 tic54x.h, tic80.h, v850.h, vax.h
2101 2005-05-09 Jan Beulich <jbeulich@novell.com>
2103 * i386.h (i386_optab): Add ht and hnt.
2105 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2107 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2108 Add xcrypt-ctr. Provide aliases without hyphens.
2110 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2112 Moved from ../ChangeLog
2114 2005-04-12 Paul Brook <paul@codesourcery.com>
2115 * m88k.h: Rename psr macros to avoid conflicts.
2117 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2118 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2119 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2120 and ARM_ARCH_V6ZKT2.
2122 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2123 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2124 Remove redundant instruction types.
2125 (struct argument): X_op - new field.
2126 (struct cst4_entry): Remove.
2127 (no_op_insn): Declare.
2129 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2130 * crx.h (enum argtype): Rename types, remove unused types.
2132 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2133 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2134 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2135 (enum operand_type): Rearrange operands, edit comments.
2136 replace us<N> with ui<N> for unsigned immediate.
2137 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2138 displacements (respectively).
2139 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2140 (instruction type): Add NO_TYPE_INS.
2141 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2142 (operand_entry): New field - 'flags'.
2143 (operand flags): New.
2145 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2146 * crx.h (operand_type): Remove redundant types i3, i4,
2148 Add new unsigned immediate types us3, us4, us5, us16.
2150 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2152 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2153 adjust them accordingly.
2155 2005-04-01 Jan Beulich <jbeulich@novell.com>
2157 * i386.h (i386_optab): Add rdtscp.
2159 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2161 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2162 between memory and segment register. Allow movq for moving between
2163 general-purpose register and segment register.
2165 2005-02-09 Jan Beulich <jbeulich@novell.com>
2168 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2169 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2172 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2174 * m68k.h (m68008, m68ec030, m68882): Remove.
2176 (cpu_m68k, cpu_cf): New.
2177 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2178 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2180 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2182 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2183 * cgen.h (enum cgen_parse_operand_type): Add
2184 CGEN_PARSE_OPERAND_SYMBOLIC.
2186 2005-01-21 Fred Fish <fnf@specifixinc.com>
2188 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2189 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2190 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2192 2005-01-19 Fred Fish <fnf@specifixinc.com>
2194 * mips.h (struct mips_opcode): Add new pinfo2 member.
2195 (INSN_ALIAS): New define for opcode table entries that are
2196 specific instances of another entry, such as 'move' for an 'or'
2197 with a zero operand.
2198 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2199 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2201 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2203 * mips.h (CPU_RM9000): Define.
2204 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2206 2004-11-25 Jan Beulich <jbeulich@novell.com>
2208 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2209 to/from test registers are illegal in 64-bit mode. Add missing
2210 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2211 (previously one had to explicitly encode a rex64 prefix). Re-enable
2212 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2213 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2215 2004-11-23 Jan Beulich <jbeulich@novell.com>
2217 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2218 available only with SSE2. Change the MMX additions introduced by SSE
2219 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2220 instructions by their now designated identifier (since combining i686
2221 and 3DNow! does not really imply 3DNow!A).
2223 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2225 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2226 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2228 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2229 Vineet Sharma <vineets@noida.hcltech.com>
2231 * maxq.h: New file: Disassembly information for the maxq port.
2233 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2235 * i386.h (i386_optab): Put back "movzb".
2237 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2239 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2240 comments. Remove member cris_ver_sim. Add members
2241 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2242 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2243 (struct cris_support_reg, struct cris_cond15): New types.
2244 (cris_conds15): Declare.
2245 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2246 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2247 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2248 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2249 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2250 SIZE_FIELD_UNSIGNED.
2252 2004-11-04 Jan Beulich <jbeulich@novell.com>
2254 * i386.h (sldx_Suf): Remove.
2255 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2256 (q_FP): Define, implying no REX64.
2257 (x_FP, sl_FP): Imply FloatMF.
2258 (i386_optab): Split reg and mem forms of moving from segment registers
2259 so that the memory forms can ignore the 16-/32-bit operand size
2260 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2261 all non-floating-point instructions. Unite 32- and 64-bit forms of
2262 movsx, movzx, and movd. Adjust floating point operations for the above
2263 changes to the *FP macros. Add DefaultSize to floating point control
2264 insns operating on larger memory ranges. Remove left over comments
2265 hinting at certain insns being Intel-syntax ones where the ones
2266 actually meant are already gone.
2268 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2270 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2273 2004-09-30 Paul Brook <paul@codesourcery.com>
2275 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2276 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2278 2004-09-11 Theodore A. Roth <troth@openavr.org>
2280 * avr.h: Add support for
2281 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2283 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2285 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2287 2004-08-24 Dmitry Diky <diwil@spec.ru>
2289 * msp430.h (msp430_opc): Add new instructions.
2290 (msp430_rcodes): Declare new instructions.
2291 (msp430_hcodes): Likewise..
2293 2004-08-13 Nick Clifton <nickc@redhat.com>
2296 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2299 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2301 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2303 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2305 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2307 2004-07-21 Jan Beulich <jbeulich@novell.com>
2309 * i386.h: Adjust instruction descriptions to better match the
2312 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2314 * arm.h: Remove all old content. Replace with architecture defines
2315 from gas/config/tc-arm.c.
2317 2004-07-09 Andreas Schwab <schwab@suse.de>
2319 * m68k.h: Fix comment.
2321 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2325 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2327 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2329 2004-05-24 Peter Barada <peter@the-baradas.com>
2331 * m68k.h: Add 'size' to m68k_opcode.
2333 2004-05-05 Peter Barada <peter@the-baradas.com>
2335 * m68k.h: Switch from ColdFire chip name to core variant.
2337 2004-04-22 Peter Barada <peter@the-baradas.com>
2339 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2340 descriptions for new EMAC cases.
2341 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2342 handle Motorola MAC syntax.
2343 Allow disassembly of ColdFire V4e object files.
2345 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2347 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2349 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2351 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2353 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2355 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2357 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2359 * i386.h (i386_optab): Added xstore/xcrypt insns.
2361 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2363 * h8300.h (32bit ldc/stc): Add relaxing support.
2365 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2367 * h8300.h (BITOP): Pass MEMRELAX flag.
2369 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2371 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2374 For older changes see ChangeLog-9103
2376 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2378 Copying and distribution of this file, with or without modification,
2379 are permitted in any medium without royalty provided the copyright
2380 notice and this notice are preserved.
2386 version-control: never
projects / deliverable / binutils-gdb.git / blob