1 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
3 * ia64.h (ia64_opnd): Add new operand types.
5 2012-08-21 David S. Miller <davem@davemloft.net>
7 * sparc.h (F3F4): New macro.
9 2012-08-13 Ian Bolton <ian.bolton@arm.com>
10 Laurent Desnogues <laurent.desnogues@arm.com>
11 Jim MacArthur <jim.macarthur@arm.com>
12 Marcus Shawcroft <marcus.shawcroft@arm.com>
13 Nigel Stephens <nigel.stephens@arm.com>
14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
15 Richard Earnshaw <rearnsha@arm.com>
16 Sofiane Naci <sofiane.naci@arm.com>
17 Tejas Belagod <tejas.belagod@arm.com>
18 Yufeng Zhang <yufeng.zhang@arm.com>
20 * aarch64.h: New file.
22 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
23 Maciej W. Rozycki <macro@codesourcery.com>
25 * mips.h (mips_opcode): Add the exclusions field.
26 (OPCODE_IS_MEMBER): Remove macro.
27 (cpu_is_member): New inline function.
28 (opcode_is_member): Likewise.
30 2012-07-31 Chao-Ying Fu <fu@mips.com>
31 Catherine Moore <clm@codesourcery.com>
32 Maciej W. Rozycki <macro@codesourcery.com>
34 * mips.h: Document microMIPS DSP ASE usage.
35 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
36 microMIPS DSP ASE support.
37 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
38 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
39 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
40 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
41 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
42 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
43 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
45 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
47 * mips.h: Fix a typo in description.
49 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
51 * avr.h: (AVR_ISA_XCH): New define.
52 (AVR_ISA_XMEGA): Use it.
53 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
55 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
57 * m68hc11.h: Add XGate definitions.
58 (struct m68hc11_opcode): Add xg_mask field.
60 2012-05-14 Catherine Moore <clm@codesourcery.com>
61 Maciej W. Rozycki <macro@codesourcery.com>
62 Rhonda Wittels <rhonda@codesourcery.com>
64 * ppc.h (PPC_OPCODE_VLE): New definition.
65 (PPC_OP_SA): New macro.
66 (PPC_OP_SE_VLE): New macro.
67 (PPC_OP): Use a variable shift amount.
68 (powerpc_operand): Update comments.
69 (PPC_OPSHIFT_INV): New macro.
70 (PPC_OPERAND_CR): Replace with...
71 (PPC_OPERAND_CR_BIT): ...this and
72 (PPC_OPERAND_CR_REG): ...this.
75 2012-05-03 Sean Keys <skeys@ipdatasys.com>
77 * xgate.h: Header file for XGATE assembler.
79 2012-04-27 David S. Miller <davem@davemloft.net>
81 * sparc.h: Document new arg code' )' for crypto RS3
84 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
85 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
86 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
87 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
88 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
89 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
90 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
91 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
92 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
93 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
94 HWCAP_CBCOND, HWCAP_CRC32): New defines.
96 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
98 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
100 2012-02-27 Alan Modra <amodra@gmail.com>
102 * crx.h (cst4_map): Update declaration.
104 2012-02-25 Walter Lee <walt@tilera.com>
106 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
108 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
109 TILEPRO_OPC_LW_TLS_SN.
111 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
113 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
114 (XRELEASE_PREFIX_OPCODE): Likewise.
116 2011-12-08 Andrew Pinski <apinski@cavium.com>
117 Adam Nemet <anemet@caviumnetworks.com>
119 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
120 (INSN_OCTEON2): New macro.
121 (CPU_OCTEON2): New macro.
122 (OPCODE_IS_MEMBER): Add Octeon2.
124 2011-11-29 Andrew Pinski <apinski@cavium.com>
126 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
127 (INSN_OCTEONP): New macro.
128 (CPU_OCTEONP): New macro.
129 (OPCODE_IS_MEMBER): Add Octeon+.
130 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
132 2011-11-01 DJ Delorie <dj@redhat.com>
136 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
138 * mips.h: Fix a typo in description.
140 2011-09-21 David S. Miller <davem@davemloft.net>
142 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
143 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
144 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
145 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
147 2011-08-09 Chao-ying Fu <fu@mips.com>
148 Maciej W. Rozycki <macro@codesourcery.com>
150 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
151 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
152 (INSN_ASE_MASK): Add the MCU bit.
153 (INSN_MCU): New macro.
154 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
155 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
157 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
159 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
160 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
161 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
162 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
163 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
164 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
165 (INSN2_READ_GPR_MMN): Likewise.
166 (INSN2_READ_FPR_D): Change the bit used.
167 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
168 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
169 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
170 (INSN2_COND_BRANCH): Likewise.
171 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
172 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
173 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
174 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
175 (INSN2_MOD_GPR_MN): Likewise.
177 2011-08-05 David S. Miller <davem@davemloft.net>
179 * sparc.h: Document new format codes '4', '5', and '('.
180 (OPF_LOW4, RS3): New macros.
182 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
184 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
185 order of flags documented.
187 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
189 * mips.h: Clarify the description of microMIPS instruction
191 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
193 2011-07-24 Chao-ying Fu <fu@mips.com>
194 Maciej W. Rozycki <macro@codesourcery.com>
196 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
197 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
198 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
199 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
200 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
201 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
202 (OP_MASK_RS3, OP_SH_RS3): Likewise.
203 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
204 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
205 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
206 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
207 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
208 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
209 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
210 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
211 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
212 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
213 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
214 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
215 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
216 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
217 (INSN_WRITE_GPR_S): New macro.
218 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
219 (INSN2_READ_FPR_D): Likewise.
220 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
221 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
222 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
223 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
224 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
225 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
226 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
227 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
228 (CPU_MICROMIPS): New macro.
229 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
230 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
231 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
232 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
233 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
234 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
235 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
236 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
237 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
238 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
239 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
240 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
241 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
242 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
243 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
244 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
245 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
246 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
247 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
248 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
249 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
250 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
251 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
252 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
253 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
254 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
255 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
256 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
257 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
258 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
259 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
260 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
261 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
262 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
263 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
264 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
265 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
266 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
267 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
268 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
269 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
270 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
271 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
272 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
273 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
274 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
275 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
276 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
277 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
278 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
279 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
280 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
281 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
282 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
283 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
284 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
285 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
286 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
287 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
288 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
289 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
290 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
291 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
292 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
293 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
294 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
295 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
296 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
297 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
298 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
299 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
300 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
301 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
302 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
303 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
304 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
305 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
306 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
307 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
308 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
309 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
310 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
311 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
312 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
313 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
314 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
315 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
316 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
317 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
318 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
319 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
320 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
321 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
322 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
323 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
324 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
325 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
326 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
327 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
328 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
329 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
330 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
331 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
332 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
333 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
334 (micromips_opcodes): New declaration.
335 (bfd_micromips_num_opcodes): Likewise.
337 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
339 * mips.h (INSN_TRAP): Rename to...
340 (INSN_NO_DELAY_SLOT): ... this.
341 (INSN_SYNC): Remove macro.
343 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
345 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
346 a duplicate of AVR_ISA_SPM.
348 2011-07-01 Nick Clifton <nickc@redhat.com>
350 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
352 2011-06-18 Robin Getz <robin.getz@analog.com>
354 * bfin.h (is_macmod_signed): New func
356 2011-06-18 Mike Frysinger <vapier@gentoo.org>
358 * bfin.h (is_macmod_pmove): Add missing space before func args.
359 (is_macmod_hmove): Likewise.
361 2011-06-13 Walter Lee <walt@tilera.com>
363 * tilegx.h: New file.
364 * tilepro.h: New file.
366 2011-05-31 Paul Brook <paul@codesourcery.com>
368 * arm.h (ARM_ARCH_V7R_IDIV): Define.
370 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
372 * s390.h: Replace S390_OPERAND_REG_EVEN with
373 S390_OPERAND_REG_PAIR.
375 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
377 * s390.h: Add S390_OPCODE_REG_EVEN flag.
379 2011-04-18 Julian Brown <julian@codesourcery.com>
381 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
383 2011-04-11 Dan McDonald <dan@wellkeeper.com>
386 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
388 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
390 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
391 New instruction set flags.
392 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
394 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
396 * mips.h (M_PREF_AB): New enum value.
398 2011-02-12 Mike Frysinger <vapier@gentoo.org>
400 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
402 (is_macmod_pmove, is_macmod_hmove): New functions.
404 2011-02-11 Mike Frysinger <vapier@gentoo.org>
406 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
408 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
410 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
411 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
413 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
416 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
419 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
422 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
424 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
426 * mips.h: Update commentary after last commit.
428 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
430 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
431 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
432 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
434 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
436 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
438 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
440 * mips.h: Fix previous commit.
442 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
444 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
445 (INSN_LOONGSON_3A): Clear bit 31.
447 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
450 * arm.h (ARM_AEXT_V6M_ONLY): New define.
451 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
452 (ARM_ARCH_V6M_ONLY): New define.
454 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
456 * mips.h (INSN_LOONGSON_3A): Defined.
457 (CPU_LOONGSON_3A): Defined.
458 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
460 2010-10-09 Matt Rice <ratmice@gmail.com>
462 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
463 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
465 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
467 * arm.h (ARM_EXT_VIRT): New define.
468 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
469 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
472 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
474 * arm.h (ARM_AEXT_ADIV): New define.
475 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
477 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
479 * arm.h (ARM_EXT_OS): New define.
480 (ARM_AEXT_V6SM): Likewise.
481 (ARM_ARCH_V6SM): Likewise.
483 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
485 * arm.h (ARM_EXT_MP): Add.
486 (ARM_ARCH_V7A_MP): Likewise.
488 2010-09-22 Mike Frysinger <vapier@gentoo.org>
490 * bfin.h: Declare pseudoChr structs/defines.
492 2010-09-21 Mike Frysinger <vapier@gentoo.org>
494 * bfin.h: Strip trailing whitespace.
496 2010-07-29 DJ Delorie <dj@redhat.com>
498 * rx.h (RX_Operand_Type): Add TwoReg.
499 (RX_Opcode_ID): Remove ediv and ediv2.
501 2010-07-27 DJ Delorie <dj@redhat.com>
503 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
505 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
506 Ina Pandit <ina.pandit@kpitcummins.com>
508 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
509 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
510 PROCESSOR_V850E2_ALL.
511 Remove PROCESSOR_V850EA support.
512 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
513 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
514 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
515 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
516 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
517 V850_OPERAND_PERCENT.
518 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
520 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
523 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
525 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
526 (MIPS16_INSN_BRANCH): Rename to...
527 (MIPS16_INSN_COND_BRANCH): ... this.
529 2010-07-03 Alan Modra <amodra@gmail.com>
531 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
532 Renumber other PPC_OPCODE defines.
534 2010-07-03 Alan Modra <amodra@gmail.com>
536 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
538 2010-06-29 Alan Modra <amodra@gmail.com>
540 * maxq.h: Delete file.
542 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
544 * ppc.h (PPC_OPCODE_E500): Define.
546 2010-05-26 Catherine Moore <clm@codesourcery.com>
548 * opcode/mips.h (INSN_MIPS16): Remove.
550 2010-04-21 Joseph Myers <joseph@codesourcery.com>
552 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
554 2010-04-15 Nick Clifton <nickc@redhat.com>
556 * alpha.h: Update copyright notice to use GPLv3.
562 * convex.h: Likewise.
576 * m68hc11.h: Likewise.
582 * mn10200.h: Likewise.
583 * mn10300.h: Likewise.
584 * msp430.h: Likewise.
595 * score-datadep.h: Likewise.
596 * score-inst.h: Likewise.
598 * spu-insns.h: Likewise.
602 * tic54x.h: Likewise.
607 2010-03-25 Joseph Myers <joseph@codesourcery.com>
609 * tic6x-control-registers.h, tic6x-insn-formats.h,
610 tic6x-opcode-table.h, tic6x.h: New.
612 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
614 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
616 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
618 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
620 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
622 * ia64.h (ia64_find_opcode): Remove argument name.
623 (ia64_find_next_opcode): Likewise.
624 (ia64_dis_opcode): Likewise.
625 (ia64_free_opcode): Likewise.
626 (ia64_find_dependency): Likewise.
628 2009-11-22 Doug Evans <dje@sebabeach.org>
630 * cgen.h: Include bfd_stdint.h.
631 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
633 2009-11-18 Paul Brook <paul@codesourcery.com>
635 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
637 2009-11-17 Paul Brook <paul@codesourcery.com>
638 Daniel Jacobowitz <dan@codesourcery.com>
640 * arm.h (ARM_EXT_V6_DSP): Define.
641 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
642 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
644 2009-11-04 DJ Delorie <dj@redhat.com>
646 * rx.h (rx_decode_opcode) (mvtipl): Add.
647 (mvtcp, mvfcp, opecp): Remove.
649 2009-11-02 Paul Brook <paul@codesourcery.com>
651 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
652 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
653 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
654 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
655 FPU_ARCH_NEON_VFP_V4): Define.
657 2009-10-23 Doug Evans <dje@sebabeach.org>
659 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
660 * cgen.h: Update. Improve multi-inclusion macro name.
662 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
664 * ppc.h (PPC_OPCODE_476): Define.
666 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
668 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
670 2009-09-29 DJ Delorie <dj@redhat.com>
674 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
676 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
678 2009-09-21 Ben Elliston <bje@au.ibm.com>
680 * ppc.h (PPC_OPCODE_PPCA2): New.
682 2009-09-05 Martin Thuresson <martin@mtme.org>
684 * ia64.h (struct ia64_operand): Renamed member class to op_class.
686 2009-08-29 Martin Thuresson <martin@mtme.org>
688 * tic30.h (template): Rename type template to
689 insn_template. Updated code to use new name.
690 * tic54x.h (template): Rename type template to
693 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
695 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
697 2009-06-11 Anthony Green <green@moxielogic.com>
699 * moxie.h (MOXIE_F3_PCREL): Define.
700 (moxie_form3_opc_info): Grow.
702 2009-06-06 Anthony Green <green@moxielogic.com>
704 * moxie.h (MOXIE_F1_M): Define.
706 2009-04-15 Anthony Green <green@moxielogic.com>
710 2009-04-06 DJ Delorie <dj@redhat.com>
712 * h8300.h: Add relaxation attributes to MOVA opcodes.
714 2009-03-10 Alan Modra <amodra@bigpond.net.au>
716 * ppc.h (ppc_parse_cpu): Declare.
718 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
720 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
721 and _IMM11 for mbitclr and mbitset.
722 * score-datadep.h: Update dependency information.
724 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
726 * ppc.h (PPC_OPCODE_POWER7): New.
728 2009-02-06 Doug Evans <dje@google.com>
730 * i386.h: Add comment regarding sse* insns and prefixes.
732 2009-02-03 Sandip Matte <sandip@rmicorp.com>
734 * mips.h (INSN_XLR): Define.
735 (INSN_CHIP_MASK): Update.
737 (OPCODE_IS_MEMBER): Update.
738 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
740 2009-01-28 Doug Evans <dje@google.com>
742 * opcode/i386.h: Add multiple inclusion protection.
743 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
744 (EDI_REG_NUM): New macros.
745 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
746 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
747 (REX_PREFIX_P): New macro.
749 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
751 * ppc.h (struct powerpc_opcode): New field "deprecated".
752 (PPC_OPCODE_NOPOWER4): Delete.
754 2008-11-28 Joshua Kinard <kumba@gentoo.org>
756 * mips.h: Define CPU_R14000, CPU_R16000.
757 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
759 2008-11-18 Catherine Moore <clm@codesourcery.com>
761 * arm.h (FPU_NEON_FP16): New.
762 (FPU_ARCH_NEON_FP16): New.
764 2008-11-06 Chao-ying Fu <fu@mips.com>
766 * mips.h: Doucument '1' for 5-bit sync type.
768 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
770 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
773 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
775 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
777 2008-07-30 Michael J. Eager <eager@eagercon.com>
779 * ppc.h (PPC_OPCODE_405): Define.
780 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
782 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
784 * ppc.h (ppc_cpu_t): New typedef.
785 (struct powerpc_opcode <flags>): Use it.
786 (struct powerpc_operand <insert, extract>): Likewise.
787 (struct powerpc_macro <flags>): Likewise.
789 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
791 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
792 Update comment before MIPS16 field descriptors to mention MIPS16.
793 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
795 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
796 New bit masks and shift counts for cins and exts.
798 * mips.h: Document new field descriptors +Q.
799 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
801 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
803 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
804 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
806 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
808 * ppc.h: (PPC_OPCODE_E500MC): New.
810 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
812 * i386.h (MAX_OPERANDS): Set to 5.
813 (MAX_MNEM_SIZE): Changed to 20.
815 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
817 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
819 2008-03-09 Paul Brook <paul@codesourcery.com>
821 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
823 2008-03-04 Paul Brook <paul@codesourcery.com>
825 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
826 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
827 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
829 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
830 Nick Clifton <nickc@redhat.com>
833 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
834 with a 32-bit displacement but without the top bit of the 4th byte
837 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
839 * cr16.h (cr16_num_optab): Declared.
841 2008-02-14 Hakan Ardo <hakan@debian.org>
844 * avr.h (AVR_ISA_2xxe): Define.
846 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
848 * mips.h: Update copyright.
849 (INSN_CHIP_MASK): New macro.
850 (INSN_OCTEON): New macro.
851 (CPU_OCTEON): New macro.
852 (OPCODE_IS_MEMBER): Handle Octeon instructions.
854 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
856 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
858 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
860 * avr.h (AVR_ISA_USB162): Add new opcode set.
861 (AVR_ISA_AVR3): Likewise.
863 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
865 * mips.h (INSN_LOONGSON_2E): New.
866 (INSN_LOONGSON_2F): New.
867 (CPU_LOONGSON_2E): New.
868 (CPU_LOONGSON_2F): New.
869 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
871 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
873 * mips.h (INSN_ISA*): Redefine certain values as an
874 enumeration. Update comments.
875 (mips_isa_table): New.
876 (ISA_MIPS*): Redefine to match enumeration.
877 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
880 2007-08-08 Ben Elliston <bje@au.ibm.com>
882 * ppc.h (PPC_OPCODE_PPCPS): New.
884 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
886 * m68k.h: Document j K & E.
888 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
890 * cr16.h: New file for CR16 target.
892 2007-05-02 Alan Modra <amodra@bigpond.net.au>
894 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
896 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
898 * m68k.h (mcfisa_c): New.
899 (mcfusp, mcf_mask): Adjust.
901 2007-04-20 Alan Modra <amodra@bigpond.net.au>
903 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
904 (num_powerpc_operands): Declare.
905 (PPC_OPERAND_SIGNED et al): Redefine as hex.
906 (PPC_OPERAND_PLUS1): Define.
908 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
910 * i386.h (REX_MODE64): Renamed to ...
912 (REX_EXTX): Renamed to ...
914 (REX_EXTY): Renamed to ...
916 (REX_EXTZ): Renamed to ...
919 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
921 * i386.h: Add entries from config/tc-i386.h and move tables
922 to opcodes/i386-opc.h.
924 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
926 * i386.h (FloatDR): Removed.
927 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
929 2007-03-01 Alan Modra <amodra@bigpond.net.au>
931 * spu-insns.h: Add soma double-float insns.
933 2007-02-20 Thiemo Seufer <ths@mips.com>
934 Chao-Ying Fu <fu@mips.com>
936 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
937 (INSN_DSPR2): Add flag for DSP R2 instructions.
938 (M_BALIGN): New macro.
940 2007-02-14 Alan Modra <amodra@bigpond.net.au>
942 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
943 and Seg3ShortFrom with Shortform.
945 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
948 * i386.h (i386_optab): Put the real "test" before the pseudo
951 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
953 * m68k.h (m68010up): OR fido_a.
955 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
957 * m68k.h (fido_a): New.
959 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
961 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
962 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
965 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
967 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
969 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
971 * score-inst.h (enum score_insn_type): Add Insn_internal.
973 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
974 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
975 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
976 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
977 Alan Modra <amodra@bigpond.net.au>
979 * spu-insns.h: New file.
982 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
984 * ppc.h (PPC_OPCODE_CELL): Define.
986 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
988 * i386.h : Modify opcode to support for the change in POPCNT opcode
989 in amdfam10 architecture.
991 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
993 * i386.h: Replace CpuMNI with CpuSSSE3.
995 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
996 Joseph Myers <joseph@codesourcery.com>
997 Ian Lance Taylor <ian@wasabisystems.com>
998 Ben Elliston <bje@wasabisystems.com>
1000 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1002 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1004 * score-datadep.h: New file.
1005 * score-inst.h: New file.
1007 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1009 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1010 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1011 movdq2q and movq2dq.
1013 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1014 Michael Meissner <michael.meissner@amd.com>
1016 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1018 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1020 * i386.h (i386_optab): Add "nop" with memory reference.
1022 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1024 * i386.h (i386_optab): Update comment for 64bit NOP.
1026 2006-06-06 Ben Elliston <bje@au.ibm.com>
1027 Anton Blanchard <anton@samba.org>
1029 * ppc.h (PPC_OPCODE_POWER6): Define.
1032 2006-06-05 Thiemo Seufer <ths@mips.com>
1034 * mips.h: Improve description of MT flags.
1036 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1038 * m68k.h (mcf_mask): Define.
1040 2006-05-05 Thiemo Seufer <ths@mips.com>
1041 David Ung <davidu@mips.com>
1043 * mips.h (enum): Add macro M_CACHE_AB.
1045 2006-05-04 Thiemo Seufer <ths@mips.com>
1046 Nigel Stephens <nigel@mips.com>
1047 David Ung <davidu@mips.com>
1049 * mips.h: Add INSN_SMARTMIPS define.
1051 2006-04-30 Thiemo Seufer <ths@mips.com>
1052 David Ung <davidu@mips.com>
1054 * mips.h: Defines udi bits and masks. Add description of
1055 characters which may appear in the args field of udi
1058 2006-04-26 Thiemo Seufer <ths@networkno.de>
1060 * mips.h: Improve comments describing the bitfield instruction
1063 2006-04-26 Julian Brown <julian@codesourcery.com>
1065 * arm.h (FPU_VFP_EXT_V3): Define constant.
1066 (FPU_NEON_EXT_V1): Likewise.
1067 (FPU_VFP_HARD): Update.
1068 (FPU_VFP_V3): Define macro.
1069 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1071 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1073 * avr.h (AVR_ISA_PWMx): New.
1075 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1077 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1078 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1079 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1080 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1081 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1083 2006-03-10 Paul Brook <paul@codesourcery.com>
1085 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1087 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1089 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1090 first. Correct mask of bb "B" opcode.
1092 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1094 * i386.h (i386_optab): Support Intel Merom New Instructions.
1096 2006-02-24 Paul Brook <paul@codesourcery.com>
1098 * arm.h: Add V7 feature bits.
1100 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1102 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1104 2006-01-31 Paul Brook <paul@codesourcery.com>
1105 Richard Earnshaw <rearnsha@arm.com>
1107 * arm.h: Use ARM_CPU_FEATURE.
1108 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1109 (arm_feature_set): Change to a structure.
1110 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1111 ARM_FEATURE): New macros.
1113 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1115 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1116 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1117 (ADD_PC_INCR_OPCODE): Don't define.
1119 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1122 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1124 2005-11-14 David Ung <davidu@mips.com>
1126 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1127 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1128 save/restore encoding of the args field.
1130 2005-10-28 Dave Brolley <brolley@redhat.com>
1132 Contribute the following changes:
1133 2005-02-16 Dave Brolley <brolley@redhat.com>
1135 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1136 cgen_isa_mask_* to cgen_bitset_*.
1139 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1141 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1142 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1143 (CGEN_CPU_TABLE): Make isas a ponter.
1145 2003-09-29 Dave Brolley <brolley@redhat.com>
1147 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1148 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1149 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1151 2002-12-13 Dave Brolley <brolley@redhat.com>
1153 * cgen.h (symcat.h): #include it.
1154 (cgen-bitset.h): #include it.
1155 (CGEN_ATTR_VALUE_TYPE): Now a union.
1156 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1157 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1158 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1159 * cgen-bitset.h: New file.
1161 2005-09-30 Catherine Moore <clm@cm00re.com>
1165 2005-10-24 Jan Beulich <jbeulich@novell.com>
1167 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1170 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1172 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1173 Add FLAG_STRICT to pa10 ftest opcode.
1175 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1177 * hppa.h (pa_opcodes): Remove lha entries.
1179 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1181 * hppa.h (FLAG_STRICT): Revise comment.
1182 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1183 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1186 2005-09-30 Catherine Moore <clm@cm00re.com>
1190 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1192 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1194 2005-09-06 Chao-ying Fu <fu@mips.com>
1196 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1197 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1199 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1200 (INSN_ASE_MASK): Update to include INSN_MT.
1201 (INSN_MT): New define for MT ASE.
1203 2005-08-25 Chao-ying Fu <fu@mips.com>
1205 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1206 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1207 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1208 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1209 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1210 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1212 (INSN_DSP): New define for DSP ASE.
1214 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1218 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1220 * ppc.h (PPC_OPCODE_E300): Define.
1222 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1224 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1226 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1229 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1232 2005-07-27 Jan Beulich <jbeulich@novell.com>
1234 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1235 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1236 Add movq-s as 64-bit variants of movd-s.
1238 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1240 * hppa.h: Fix punctuation in comment.
1242 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1243 implicit space-register addressing. Set space-register bits on opcodes
1244 using implicit space-register addressing. Add various missing pa20
1245 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1246 space-register addressing. Use "fE" instead of "fe" in various
1249 2005-07-18 Jan Beulich <jbeulich@novell.com>
1251 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1253 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1255 * i386.h (i386_optab): Support Intel VMX Instructions.
1257 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1259 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1261 2005-07-05 Jan Beulich <jbeulich@novell.com>
1263 * i386.h (i386_optab): Add new insns.
1265 2005-07-01 Nick Clifton <nickc@redhat.com>
1267 * sparc.h: Add typedefs to structure declarations.
1269 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1272 * i386.h (i386_optab): Update comments for 64bit addressing on
1273 mov. Allow 64bit addressing for mov and movq.
1275 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1277 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1278 respectively, in various floating-point load and store patterns.
1280 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1282 * hppa.h (FLAG_STRICT): Correct comment.
1283 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1284 PA 2.0 mneumonics when equivalent. Entries with cache control
1285 completers now require PA 1.1. Adjust whitespace.
1287 2005-05-19 Anton Blanchard <anton@samba.org>
1289 * ppc.h (PPC_OPCODE_POWER5): Define.
1291 2005-05-10 Nick Clifton <nickc@redhat.com>
1293 * Update the address and phone number of the FSF organization in
1294 the GPL notices in the following files:
1295 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1296 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1297 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1298 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1299 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1300 tic54x.h, tic80.h, v850.h, vax.h
1302 2005-05-09 Jan Beulich <jbeulich@novell.com>
1304 * i386.h (i386_optab): Add ht and hnt.
1306 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1308 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1309 Add xcrypt-ctr. Provide aliases without hyphens.
1311 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1313 Moved from ../ChangeLog
1315 2005-04-12 Paul Brook <paul@codesourcery.com>
1316 * m88k.h: Rename psr macros to avoid conflicts.
1318 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1319 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1320 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1321 and ARM_ARCH_V6ZKT2.
1323 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1324 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1325 Remove redundant instruction types.
1326 (struct argument): X_op - new field.
1327 (struct cst4_entry): Remove.
1328 (no_op_insn): Declare.
1330 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1331 * crx.h (enum argtype): Rename types, remove unused types.
1333 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1334 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1335 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1336 (enum operand_type): Rearrange operands, edit comments.
1337 replace us<N> with ui<N> for unsigned immediate.
1338 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1339 displacements (respectively).
1340 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1341 (instruction type): Add NO_TYPE_INS.
1342 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1343 (operand_entry): New field - 'flags'.
1344 (operand flags): New.
1346 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1347 * crx.h (operand_type): Remove redundant types i3, i4,
1349 Add new unsigned immediate types us3, us4, us5, us16.
1351 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1353 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1354 adjust them accordingly.
1356 2005-04-01 Jan Beulich <jbeulich@novell.com>
1358 * i386.h (i386_optab): Add rdtscp.
1360 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1362 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1363 between memory and segment register. Allow movq for moving between
1364 general-purpose register and segment register.
1366 2005-02-09 Jan Beulich <jbeulich@novell.com>
1369 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1370 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1373 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1375 * m68k.h (m68008, m68ec030, m68882): Remove.
1377 (cpu_m68k, cpu_cf): New.
1378 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1379 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1381 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1383 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1384 * cgen.h (enum cgen_parse_operand_type): Add
1385 CGEN_PARSE_OPERAND_SYMBOLIC.
1387 2005-01-21 Fred Fish <fnf@specifixinc.com>
1389 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1390 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1391 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1393 2005-01-19 Fred Fish <fnf@specifixinc.com>
1395 * mips.h (struct mips_opcode): Add new pinfo2 member.
1396 (INSN_ALIAS): New define for opcode table entries that are
1397 specific instances of another entry, such as 'move' for an 'or'
1398 with a zero operand.
1399 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1400 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1402 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1404 * mips.h (CPU_RM9000): Define.
1405 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1407 2004-11-25 Jan Beulich <jbeulich@novell.com>
1409 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1410 to/from test registers are illegal in 64-bit mode. Add missing
1411 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1412 (previously one had to explicitly encode a rex64 prefix). Re-enable
1413 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1414 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1416 2004-11-23 Jan Beulich <jbeulich@novell.com>
1418 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1419 available only with SSE2. Change the MMX additions introduced by SSE
1420 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1421 instructions by their now designated identifier (since combining i686
1422 and 3DNow! does not really imply 3DNow!A).
1424 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1426 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1427 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1429 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1430 Vineet Sharma <vineets@noida.hcltech.com>
1432 * maxq.h: New file: Disassembly information for the maxq port.
1434 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1436 * i386.h (i386_optab): Put back "movzb".
1438 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1440 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1441 comments. Remove member cris_ver_sim. Add members
1442 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1443 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1444 (struct cris_support_reg, struct cris_cond15): New types.
1445 (cris_conds15): Declare.
1446 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1447 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1448 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1449 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1450 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1451 SIZE_FIELD_UNSIGNED.
1453 2004-11-04 Jan Beulich <jbeulich@novell.com>
1455 * i386.h (sldx_Suf): Remove.
1456 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1457 (q_FP): Define, implying no REX64.
1458 (x_FP, sl_FP): Imply FloatMF.
1459 (i386_optab): Split reg and mem forms of moving from segment registers
1460 so that the memory forms can ignore the 16-/32-bit operand size
1461 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1462 all non-floating-point instructions. Unite 32- and 64-bit forms of
1463 movsx, movzx, and movd. Adjust floating point operations for the above
1464 changes to the *FP macros. Add DefaultSize to floating point control
1465 insns operating on larger memory ranges. Remove left over comments
1466 hinting at certain insns being Intel-syntax ones where the ones
1467 actually meant are already gone.
1469 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1471 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1474 2004-09-30 Paul Brook <paul@codesourcery.com>
1476 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1477 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1479 2004-09-11 Theodore A. Roth <troth@openavr.org>
1481 * avr.h: Add support for
1482 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1484 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1486 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1488 2004-08-24 Dmitry Diky <diwil@spec.ru>
1490 * msp430.h (msp430_opc): Add new instructions.
1491 (msp430_rcodes): Declare new instructions.
1492 (msp430_hcodes): Likewise..
1494 2004-08-13 Nick Clifton <nickc@redhat.com>
1497 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1500 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1502 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1504 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1506 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1508 2004-07-21 Jan Beulich <jbeulich@novell.com>
1510 * i386.h: Adjust instruction descriptions to better match the
1513 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1515 * arm.h: Remove all old content. Replace with architecture defines
1516 from gas/config/tc-arm.c.
1518 2004-07-09 Andreas Schwab <schwab@suse.de>
1520 * m68k.h: Fix comment.
1522 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1526 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1528 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1530 2004-05-24 Peter Barada <peter@the-baradas.com>
1532 * m68k.h: Add 'size' to m68k_opcode.
1534 2004-05-05 Peter Barada <peter@the-baradas.com>
1536 * m68k.h: Switch from ColdFire chip name to core variant.
1538 2004-04-22 Peter Barada <peter@the-baradas.com>
1540 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1541 descriptions for new EMAC cases.
1542 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1543 handle Motorola MAC syntax.
1544 Allow disassembly of ColdFire V4e object files.
1546 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1548 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1550 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1552 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1554 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1556 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1558 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1560 * i386.h (i386_optab): Added xstore/xcrypt insns.
1562 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1564 * h8300.h (32bit ldc/stc): Add relaxing support.
1566 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1568 * h8300.h (BITOP): Pass MEMRELAX flag.
1570 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1572 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1575 For older changes see ChangeLog-9103
1581 version-control: never
projects / deliverable / binutils-gdb.git / blob