include/opcode/ChangeLog

   1 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
   2             Andrew Jenner <andrew@codesourcery.com>
   3
   4         Based on patches from Altera Corporation.
   5
   6         * nios2.h: New file.
   7
   8 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
   9
  10         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
  11
  12 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
  13
  14         PR gas/15069
  15         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
  16
  17 2013-01-24  Nick Clifton  <nickc@redhat.com>
  18
  19         * v850.h: Add e3v5 support.
  20
  21 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  22
  23         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
  24
  25 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  26
  27         * ppc.h (PPC_OPCODE_POWER8): New define.
  28         (PPC_OPCODE_HTM): Likewise.
  29
  30 2013-01-10  Will Newton <will.newton@imgtec.com>
  31
  32         * metag.h: New file.
  33
  34 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  35
  36         * cr16.h (make_instruction): Rename to cr16_make_instruction.
  37         (match_opcode): Rename to cr16_match_opcode.
  38
  39 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
  40
  41         * mips.h: Add support for r5900 instructions including lq and sq.
  42
  43 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  44
  45         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
  46         (make_instruction,match_opcode): Added function prototypes.
  47         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
  48
  49 2012-11-23  Alan Modra  <amodra@gmail.com>
  50
  51         * ppc.h (ppc_parse_cpu): Update prototype.
  52
  53 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  54
  55         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
  56         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
  57
  58 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  59
  60         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
  61
  62 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
  63
  64         * ia64.h (ia64_opnd): Add new operand types.
  65
  66 2012-08-21  David S. Miller  <davem@davemloft.net>
  67
  68         * sparc.h (F3F4): New macro.
  69
  70 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
  71             Laurent Desnogues  <laurent.desnogues@arm.com>
  72             Jim MacArthur  <jim.macarthur@arm.com>
  73             Marcus Shawcroft  <marcus.shawcroft@arm.com>
  74             Nigel Stephens  <nigel.stephens@arm.com>
  75             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  76             Richard Earnshaw  <rearnsha@arm.com>
  77             Sofiane Naci  <sofiane.naci@arm.com>
  78             Tejas Belagod  <tejas.belagod@arm.com>
  79             Yufeng Zhang  <yufeng.zhang@arm.com>
  80
  81         * aarch64.h: New file.
  82
  83 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
  84             Maciej W. Rozycki  <macro@codesourcery.com>
  85
  86         * mips.h (mips_opcode): Add the exclusions field.
  87         (OPCODE_IS_MEMBER): Remove macro.
  88         (cpu_is_member): New inline function.
  89         (opcode_is_member): Likewise.
  90
  91 2012-07-31  Chao-Ying Fu  <fu@mips.com>
  92             Catherine Moore  <clm@codesourcery.com>
  93             Maciej W. Rozycki  <macro@codesourcery.com>
  94
  95         * mips.h: Document microMIPS DSP ASE usage.
  96         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
  97         microMIPS DSP ASE support.
  98         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
  99         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 100         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 101         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 102         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 103         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 104         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 105
 106 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 107
 108         * mips.h: Fix a typo in description.
 109
 110 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 111
 112         * avr.h: (AVR_ISA_XCH): New define.
 113         (AVR_ISA_XMEGA): Use it.
 114         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 115
 116 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 117
 118         * m68hc11.h: Add XGate definitions.
 119         (struct m68hc11_opcode): Add xg_mask field.
 120
 121 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 122             Maciej W. Rozycki  <macro@codesourcery.com>
 123             Rhonda Wittels  <rhonda@codesourcery.com>
 124
 125         * ppc.h (PPC_OPCODE_VLE): New definition.
 126         (PPC_OP_SA): New macro.
 127         (PPC_OP_SE_VLE): New macro.
 128         (PPC_OP): Use a variable shift amount.
 129         (powerpc_operand): Update comments.
 130         (PPC_OPSHIFT_INV): New macro.
 131         (PPC_OPERAND_CR): Replace with...
 132         (PPC_OPERAND_CR_BIT): ...this and
 133         (PPC_OPERAND_CR_REG): ...this.
 134
 135
 136 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 137
 138         * xgate.h: Header file for XGATE assembler.
 139
 140 2012-04-27  David S. Miller  <davem@davemloft.net>
 141
 142         * sparc.h: Document new arg code' )' for crypto RS3
 143         immediates.
 144
 145         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 146         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 147         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 148         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 149         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 150         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 151         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 152         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 153         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 154         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 155         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 156
 157 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 158
 159         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 160
 161 2012-02-27  Alan Modra  <amodra@gmail.com>
 162
 163         * crx.h (cst4_map): Update declaration.
 164
 165 2012-02-25  Walter Lee  <walt@tilera.com>
 166
 167         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 168         TILEGX_OPC_LD_TLS.
 169         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 170         TILEPRO_OPC_LW_TLS_SN.
 171
 172 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 173
 174         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 175         (XRELEASE_PREFIX_OPCODE): Likewise.
 176
 177 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 178             Adam Nemet  <anemet@caviumnetworks.com>
 179
 180         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 181         (INSN_OCTEON2): New macro.
 182         (CPU_OCTEON2): New macro.
 183         (OPCODE_IS_MEMBER): Add Octeon2.
 184
 185 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 186
 187         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 188         (INSN_OCTEONP): New macro.
 189         (CPU_OCTEONP): New macro.
 190         (OPCODE_IS_MEMBER): Add Octeon+.
 191         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 192
 193 2011-11-01  DJ Delorie  <dj@redhat.com>
 194
 195         * rl78.h: New file.
 196
 197 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 198
 199         * mips.h: Fix a typo in description.
 200
 201 2011-09-21  David S. Miller  <davem@davemloft.net>
 202
 203         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 204         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 205         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 206         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 207
 208 2011-08-09  Chao-ying Fu  <fu@mips.com>
 209             Maciej W. Rozycki  <macro@codesourcery.com>
 210
 211         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 212         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 213         (INSN_ASE_MASK): Add the MCU bit.
 214         (INSN_MCU): New macro.
 215         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 216         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 217
 218 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 219
 220         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 221         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 222         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 223         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 224         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 225         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 226         (INSN2_READ_GPR_MMN): Likewise.
 227         (INSN2_READ_FPR_D): Change the bit used.
 228         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 229         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 230         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 231         (INSN2_COND_BRANCH): Likewise.
 232         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 233         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 234         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 235         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 236         (INSN2_MOD_GPR_MN): Likewise.
 237
 238 2011-08-05  David S. Miller  <davem@davemloft.net>
 239
 240         * sparc.h: Document new format codes '4', '5', and '('.
 241         (OPF_LOW4, RS3): New macros.
 242
 243 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 244
 245         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 246         order of flags documented.
 247
 248 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 249
 250         * mips.h: Clarify the description of microMIPS instruction
 251         manipulation macros.
 252         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 253
 254 2011-07-24  Chao-ying Fu  <fu@mips.com>
 255             Maciej W. Rozycki  <macro@codesourcery.com>
 256
 257         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 258         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 259         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 260         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 261         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 262         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 263         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 264         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 265         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 266         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 267         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 268         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 269         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 270         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 271         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 272         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 273         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 274         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 275         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 276         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 277         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 278         (INSN_WRITE_GPR_S): New macro.
 279         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 280         (INSN2_READ_FPR_D): Likewise.
 281         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 282         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 283         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 284         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 285         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 286         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 287         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 288         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 289         (CPU_MICROMIPS): New macro.
 290         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 291         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 292         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 293         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 294         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 295         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 296         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 297         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 298         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 299         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 300         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 301         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 302         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 303         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 304         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 305         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 306         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 307         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 308         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 309         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 310         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 311         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 312         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 313         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 314         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 315         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 316         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 317         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 318         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 319         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 320         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 321         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 322         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 323         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 324         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 325         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 326         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 327         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 328         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 329         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 330         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 331         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 332         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 333         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 334         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 335         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 336         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 337         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 338         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 339         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 340         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 341         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 342         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 343         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 344         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 345         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 346         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 347         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 348         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 349         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 350         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 351         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 352         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 353         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 354         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 355         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 356         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 357         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 358         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 359         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 360         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 361         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 362         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 363         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 364         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 365         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 366         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 367         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 368         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 369         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 370         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 371         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 372         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 373         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 374         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 375         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 376         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 377         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 378         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 379         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 380         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 381         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 382         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 383         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 384         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 385         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 386         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 387         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 388         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 389         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 390         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 391         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 392         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 393         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 394         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 395         (micromips_opcodes): New declaration.
 396         (bfd_micromips_num_opcodes): Likewise.
 397
 398 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 399
 400         * mips.h (INSN_TRAP): Rename to...
 401         (INSN_NO_DELAY_SLOT): ... this.
 402         (INSN_SYNC): Remove macro.
 403
 404 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 405
 406         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 407         a duplicate of AVR_ISA_SPM.
 408
 409 2011-07-01  Nick Clifton  <nickc@redhat.com>
 410
 411         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 412
 413 2011-06-18  Robin Getz  <robin.getz@analog.com>
 414
 415         * bfin.h (is_macmod_signed): New func
 416
 417 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 418
 419         * bfin.h (is_macmod_pmove): Add missing space before func args.
 420         (is_macmod_hmove): Likewise.
 421
 422 2011-06-13  Walter Lee  <walt@tilera.com>
 423
 424         * tilegx.h: New file.
 425         * tilepro.h: New file.
 426
 427 2011-05-31  Paul Brook  <paul@codesourcery.com>
 428
 429         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 430
 431 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 432
 433         * s390.h: Replace S390_OPERAND_REG_EVEN with
 434         S390_OPERAND_REG_PAIR.
 435
 436 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 437
 438         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 439
 440 2011-04-18  Julian Brown  <julian@codesourcery.com>
 441
 442         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 443
 444 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 445
 446         PR gas/12296
 447         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 448
 449 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 450
 451         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 452         New instruction set flags.
 453         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 454
 455 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 456
 457         * mips.h (M_PREF_AB): New enum value.
 458
 459 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 460
 461         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 462         M_IU): Define.
 463         (is_macmod_pmove, is_macmod_hmove): New functions.
 464
 465 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 466
 467         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 468
 469 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 470
 471         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 472         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 473
 474 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 475
 476         PR gas/11395
 477         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 478         "bb" entries.
 479
 480 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 481
 482         PR gas/11395
 483         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 484
 485 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 486
 487         * mips.h: Update commentary after last commit.
 488
 489 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 490
 491         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 492         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 493         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 494
 495 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 496
 497         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 498
 499 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 500
 501         * mips.h: Fix previous commit.
 502
 503 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 504
 505         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 506         (INSN_LOONGSON_3A): Clear bit 31.
 507
 508 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 509
 510         PR gas/12198
 511         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 512         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 513         (ARM_ARCH_V6M_ONLY): New define.
 514
 515 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 516
 517         * mips.h (INSN_LOONGSON_3A): Defined.
 518         (CPU_LOONGSON_3A): Defined.
 519         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 520
 521 2010-10-09  Matt Rice  <ratmice@gmail.com>
 522
 523         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 524         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 525
 526 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 527
 528         * arm.h (ARM_EXT_VIRT): New define.
 529         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 530         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 531         Extensions.
 532
 533 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 534
 535         * arm.h (ARM_AEXT_ADIV): New define.
 536         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 537
 538 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 539
 540         * arm.h (ARM_EXT_OS): New define.
 541         (ARM_AEXT_V6SM): Likewise.
 542         (ARM_ARCH_V6SM): Likewise.
 543
 544 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 545
 546         * arm.h (ARM_EXT_MP): Add.
 547         (ARM_ARCH_V7A_MP): Likewise.
 548
 549 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 550
 551         * bfin.h: Declare pseudoChr structs/defines.
 552
 553 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 554
 555         * bfin.h: Strip trailing whitespace.
 556
 557 2010-07-29  DJ Delorie  <dj@redhat.com>
 558
 559         * rx.h (RX_Operand_Type): Add TwoReg.
 560         (RX_Opcode_ID): Remove ediv and ediv2.
 561
 562 2010-07-27  DJ Delorie  <dj@redhat.com>
 563
 564         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 565
 566 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 567             Ina Pandit  <ina.pandit@kpitcummins.com>
 568
 569         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 570         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 571         PROCESSOR_V850E2_ALL.
 572         Remove PROCESSOR_V850EA support.
 573         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 574         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 575         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 576         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 577         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 578         V850_OPERAND_PERCENT.
 579         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 580         V850_NOT_R0.
 581         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 582         and V850E_PUSH_POP
 583
 584 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 585
 586         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 587         (MIPS16_INSN_BRANCH): Rename to...
 588         (MIPS16_INSN_COND_BRANCH): ... this.
 589
 590 2010-07-03  Alan Modra  <amodra@gmail.com>
 591
 592         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 593         Renumber other PPC_OPCODE defines.
 594
 595 2010-07-03  Alan Modra  <amodra@gmail.com>
 596
 597         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 598
 599 2010-06-29  Alan Modra  <amodra@gmail.com>
 600
 601         * maxq.h: Delete file.
 602
 603 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 604
 605         * ppc.h (PPC_OPCODE_E500): Define.
 606
 607 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 608
 609         * opcode/mips.h (INSN_MIPS16): Remove.
 610
 611 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 612
 613         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 614
 615 2010-04-15  Nick Clifton  <nickc@redhat.com>
 616
 617         * alpha.h: Update copyright notice to use GPLv3.
 618         * arc.h: Likewise.
 619         * arm.h: Likewise.
 620         * avr.h: Likewise.
 621         * bfin.h: Likewise.
 622         * cgen.h: Likewise.
 623         * convex.h: Likewise.
 624         * cr16.h: Likewise.
 625         * cris.h: Likewise.
 626         * crx.h: Likewise.
 627         * d10v.h: Likewise.
 628         * d30v.h: Likewise.
 629         * dlx.h: Likewise.
 630         * h8300.h: Likewise.
 631         * hppa.h: Likewise.
 632         * i370.h: Likewise.
 633         * i386.h: Likewise.
 634         * i860.h: Likewise.
 635         * i960.h: Likewise.
 636         * ia64.h: Likewise.
 637         * m68hc11.h: Likewise.
 638         * m68k.h: Likewise.
 639         * m88k.h: Likewise.
 640         * maxq.h: Likewise.
 641         * mips.h: Likewise.
 642         * mmix.h: Likewise.
 643         * mn10200.h: Likewise.
 644         * mn10300.h: Likewise.
 645         * msp430.h: Likewise.
 646         * np1.h: Likewise.
 647         * ns32k.h: Likewise.
 648         * or32.h: Likewise.
 649         * pdp11.h: Likewise.
 650         * pj.h: Likewise.
 651         * pn.h: Likewise.
 652         * ppc.h: Likewise.
 653         * pyr.h: Likewise.
 654         * rx.h: Likewise.
 655         * s390.h: Likewise.
 656         * score-datadep.h: Likewise.
 657         * score-inst.h: Likewise.
 658         * sparc.h: Likewise.
 659         * spu-insns.h: Likewise.
 660         * spu.h: Likewise.
 661         * tic30.h: Likewise.
 662         * tic4x.h: Likewise.
 663         * tic54x.h: Likewise.
 664         * tic80.h: Likewise.
 665         * v850.h: Likewise.
 666         * vax.h: Likewise.
 667
 668 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 669
 670         * tic6x-control-registers.h, tic6x-insn-formats.h,
 671         tic6x-opcode-table.h, tic6x.h: New.
 672
 673 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 674
 675         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 676
 677 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 678
 679         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 680
 681 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * ia64.h (ia64_find_opcode): Remove argument name.
 684         (ia64_find_next_opcode): Likewise.
 685         (ia64_dis_opcode): Likewise.
 686         (ia64_free_opcode): Likewise.
 687         (ia64_find_dependency): Likewise.
 688
 689 2009-11-22  Doug Evans  <dje@sebabeach.org>
 690
 691         * cgen.h: Include bfd_stdint.h.
 692         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 693
 694 2009-11-18  Paul Brook  <paul@codesourcery.com>
 695
 696         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 697
 698 2009-11-17  Paul Brook  <paul@codesourcery.com>
 699         Daniel Jacobowitz  <dan@codesourcery.com>
 700
 701         * arm.h (ARM_EXT_V6_DSP): Define.
 702         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 703         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 704
 705 2009-11-04  DJ Delorie  <dj@redhat.com>
 706
 707         * rx.h (rx_decode_opcode) (mvtipl): Add.
 708         (mvtcp, mvfcp, opecp): Remove.
 709
 710 2009-11-02  Paul Brook  <paul@codesourcery.com>
 711
 712         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 713         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 714         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 715         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 716         FPU_ARCH_NEON_VFP_V4): Define.
 717
 718 2009-10-23  Doug Evans  <dje@sebabeach.org>
 719
 720         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 721         * cgen.h: Update.  Improve multi-inclusion macro name.
 722
 723 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 724
 725         * ppc.h (PPC_OPCODE_476): Define.
 726
 727 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 728
 729         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 730
 731 2009-09-29  DJ Delorie  <dj@redhat.com>
 732
 733         * rx.h: New file.
 734
 735 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 736
 737         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 738
 739 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 740
 741         * ppc.h (PPC_OPCODE_PPCA2): New.
 742
 743 2009-09-05  Martin Thuresson  <martin@mtme.org>
 744
 745         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 746
 747 2009-08-29  Martin Thuresson  <martin@mtme.org>
 748
 749         * tic30.h (template): Rename type template to
 750         insn_template. Updated code to use new name.
 751         * tic54x.h (template): Rename type template to
 752         insn_template.
 753
 754 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 755
 756         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 757
 758 2009-06-11  Anthony Green  <green@moxielogic.com>
 759
 760         * moxie.h (MOXIE_F3_PCREL): Define.
 761         (moxie_form3_opc_info): Grow.
 762
 763 2009-06-06  Anthony Green  <green@moxielogic.com>
 764
 765         * moxie.h (MOXIE_F1_M): Define.
 766
 767 2009-04-15  Anthony Green  <green@moxielogic.com>
 768
 769         * moxie.h: Created.
 770
 771 2009-04-06  DJ Delorie  <dj@redhat.com>
 772
 773         * h8300.h: Add relaxation attributes to MOVA opcodes.
 774
 775 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 776
 777         * ppc.h (ppc_parse_cpu): Declare.
 778
 779 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 780
 781         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 782         and _IMM11 for mbitclr and mbitset.
 783         * score-datadep.h: Update dependency information.
 784
 785 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 786
 787         * ppc.h (PPC_OPCODE_POWER7): New.
 788
 789 2009-02-06  Doug Evans  <dje@google.com>
 790
 791         * i386.h: Add comment regarding sse* insns and prefixes.
 792
 793 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 794
 795         * mips.h (INSN_XLR): Define.
 796         (INSN_CHIP_MASK): Update.
 797         (CPU_XLR): Define.
 798         (OPCODE_IS_MEMBER): Update.
 799         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 800
 801 2009-01-28  Doug Evans  <dje@google.com>
 802
 803         * opcode/i386.h: Add multiple inclusion protection.
 804         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 805         (EDI_REG_NUM): New macros.
 806         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 807         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 808         (REX_PREFIX_P): New macro.
 809
 810 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 811
 812         * ppc.h (struct powerpc_opcode): New field "deprecated".
 813         (PPC_OPCODE_NOPOWER4): Delete.
 814
 815 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 816
 817         * mips.h: Define CPU_R14000, CPU_R16000.
 818         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 819
 820 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 821
 822         * arm.h (FPU_NEON_FP16): New.
 823         (FPU_ARCH_NEON_FP16): New.
 824
 825 2008-11-06  Chao-ying Fu  <fu@mips.com>
 826
 827         * mips.h: Doucument '1' for 5-bit sync type.
 828
 829 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 832         IA64_RS_CR.
 833
 834 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 835
 836         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 837
 838 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 839
 840         * ppc.h (PPC_OPCODE_405): Define.
 841         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 842
 843 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 844
 845         * ppc.h (ppc_cpu_t): New typedef.
 846         (struct powerpc_opcode <flags>): Use it.
 847         (struct powerpc_operand <insert, extract>): Likewise.
 848         (struct powerpc_macro <flags>): Likewise.
 849
 850 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 851
 852         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 853         Update comment before MIPS16 field descriptors to mention MIPS16.
 854         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 855         BBIT.
 856         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 857         New bit masks and shift counts for cins and exts.
 858
 859         * mips.h: Document new field descriptors +Q.
 860         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 861
 862 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 863
 864         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 865         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 866
 867 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 868
 869         * ppc.h: (PPC_OPCODE_E500MC): New.
 870
 871 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 872
 873         * i386.h (MAX_OPERANDS): Set to 5.
 874         (MAX_MNEM_SIZE): Changed to 20.
 875
 876 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 877
 878         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 879
 880 2008-03-09  Paul Brook  <paul@codesourcery.com>
 881
 882         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 883
 884 2008-03-04  Paul Brook  <paul@codesourcery.com>
 885
 886         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 887         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 888         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 889
 890 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 891             Nick Clifton  <nickc@redhat.com>
 892
 893         PR 3134
 894         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 895         with a 32-bit displacement but without the top bit of the 4th byte
 896         set.
 897
 898 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 899
 900         * cr16.h (cr16_num_optab): Declared.
 901
 902 2008-02-14  Hakan Ardo  <hakan@debian.org>
 903
 904         PR gas/2626
 905         * avr.h (AVR_ISA_2xxe): Define.
 906
 907 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 908
 909         * mips.h: Update copyright.
 910         (INSN_CHIP_MASK): New macro.
 911         (INSN_OCTEON): New macro.
 912         (CPU_OCTEON): New macro.
 913         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 914
 915 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 916
 917         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 918
 919 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 920
 921         * avr.h (AVR_ISA_USB162): Add new opcode set.
 922         (AVR_ISA_AVR3): Likewise.
 923
 924 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 925
 926         * mips.h (INSN_LOONGSON_2E): New.
 927         (INSN_LOONGSON_2F): New.
 928         (CPU_LOONGSON_2E): New.
 929         (CPU_LOONGSON_2F): New.
 930         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 931
 932 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 933
 934         * mips.h (INSN_ISA*): Redefine certain values as an
 935         enumeration.  Update comments.
 936         (mips_isa_table): New.
 937         (ISA_MIPS*): Redefine to match enumeration.
 938         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 939         values.
 940
 941 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 942
 943         * ppc.h (PPC_OPCODE_PPCPS): New.
 944
 945 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 946
 947         * m68k.h: Document j K & E.
 948
 949 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 950
 951         * cr16.h: New file for CR16 target.
 952
 953 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 954
 955         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 956
 957 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 958
 959         * m68k.h (mcfisa_c): New.
 960         (mcfusp, mcf_mask): Adjust.
 961
 962 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 963
 964         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 965         (num_powerpc_operands): Declare.
 966         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 967         (PPC_OPERAND_PLUS1): Define.
 968
 969 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 970
 971         * i386.h (REX_MODE64): Renamed to ...
 972         (REX_W): This.
 973         (REX_EXTX): Renamed to ...
 974         (REX_R): This.
 975         (REX_EXTY): Renamed to ...
 976         (REX_X): This.
 977         (REX_EXTZ): Renamed to ...
 978         (REX_B): This.
 979
 980 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         * i386.h: Add entries from config/tc-i386.h and move tables
 983         to opcodes/i386-opc.h.
 984
 985 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 986
 987         * i386.h (FloatDR): Removed.
 988         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 989
 990 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 991
 992         * spu-insns.h: Add soma double-float insns.
 993
 994 2007-02-20  Thiemo Seufer  <ths@mips.com>
 995             Chao-Ying Fu  <fu@mips.com>
 996
 997         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 998         (INSN_DSPR2): Add flag for DSP R2 instructions.
 999         (M_BALIGN): New macro.
1000
1001 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1002
1003         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1004         and Seg3ShortFrom with Shortform.
1005
1006 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1007
1008         PR gas/4027
1009         * i386.h (i386_optab): Put the real "test" before the pseudo
1010         one.
1011
1012 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1013
1014         * m68k.h (m68010up): OR fido_a.
1015
1016 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1017
1018         * m68k.h (fido_a): New.
1019
1020 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1021
1022         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1023         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1024         values.
1025
1026 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1027
1028         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1029
1030 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1031
1032         * score-inst.h (enum score_insn_type): Add Insn_internal.
1033
1034 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1035             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1036             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1037             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1038             Alan Modra  <amodra@bigpond.net.au>
1039
1040         * spu-insns.h: New file.
1041         * spu.h: New file.
1042
1043 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1044
1045         * ppc.h (PPC_OPCODE_CELL): Define.
1046
1047 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1048
1049         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1050         in amdfam10 architecture.
1051
1052 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1053
1054         * i386.h: Replace CpuMNI with CpuSSSE3.
1055
1056 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1057             Joseph Myers  <joseph@codesourcery.com>
1058             Ian Lance Taylor  <ian@wasabisystems.com>
1059             Ben Elliston  <bje@wasabisystems.com>
1060
1061         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1062
1063 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1064
1065         * score-datadep.h: New file.
1066         * score-inst.h: New file.
1067
1068 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1069
1070         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1071         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1072         movdq2q and movq2dq.
1073
1074 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1075            Michael Meissner             <michael.meissner@amd.com>
1076
1077         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1078
1079 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1080
1081         * i386.h (i386_optab): Add "nop" with memory reference.
1082
1083 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         * i386.h (i386_optab): Update comment for 64bit NOP.
1086
1087 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1088             Anton Blanchard  <anton@samba.org>
1089
1090         * ppc.h (PPC_OPCODE_POWER6): Define.
1091         Adjust whitespace.
1092
1093 2006-06-05  Thiemo Seufer  <ths@mips.com>
1094
1095         * mips.h: Improve description of MT flags.
1096
1097 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1098
1099         * m68k.h (mcf_mask): Define.
1100
1101 2006-05-05  Thiemo Seufer  <ths@mips.com>
1102             David Ung  <davidu@mips.com>
1103
1104         * mips.h (enum): Add macro M_CACHE_AB.
1105
1106 2006-05-04  Thiemo Seufer  <ths@mips.com>
1107             Nigel Stephens  <nigel@mips.com>
1108             David Ung  <davidu@mips.com>
1109
1110         * mips.h: Add INSN_SMARTMIPS define.
1111
1112 2006-04-30  Thiemo Seufer  <ths@mips.com>
1113             David Ung  <davidu@mips.com>
1114
1115         * mips.h: Defines udi bits and masks.  Add description of
1116         characters which may appear in the args field of udi
1117         instructions.
1118
1119 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1120
1121         * mips.h: Improve comments describing the bitfield instruction
1122         fields.
1123
1124 2006-04-26  Julian Brown  <julian@codesourcery.com>
1125
1126         * arm.h (FPU_VFP_EXT_V3): Define constant.
1127         (FPU_NEON_EXT_V1): Likewise.
1128         (FPU_VFP_HARD): Update.
1129         (FPU_VFP_V3): Define macro.
1130         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1131
1132 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1133
1134         * avr.h (AVR_ISA_PWMx): New.
1135
1136 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1137
1138         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1139         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1140         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1141         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1142         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1143
1144 2006-03-10  Paul Brook  <paul@codesourcery.com>
1145
1146         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1147
1148 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1149
1150         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1151         first.  Correct mask of bb "B" opcode.
1152
1153 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1154
1155         * i386.h (i386_optab): Support Intel Merom New Instructions.
1156
1157 2006-02-24  Paul Brook  <paul@codesourcery.com>
1158
1159         * arm.h: Add V7 feature bits.
1160
1161 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1162
1163         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1164
1165 2006-01-31  Paul Brook  <paul@codesourcery.com>
1166         Richard Earnshaw <rearnsha@arm.com>
1167
1168         * arm.h: Use ARM_CPU_FEATURE.
1169         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1170         (arm_feature_set): Change to a structure.
1171         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1172         ARM_FEATURE): New macros.
1173
1174 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1175
1176         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1177         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1178         (ADD_PC_INCR_OPCODE): Don't define.
1179
1180 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         PR gas/1874
1183         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1184
1185 2005-11-14  David Ung  <davidu@mips.com>
1186
1187         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1188         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1189         save/restore encoding of the args field.
1190
1191 2005-10-28  Dave Brolley  <brolley@redhat.com>
1192
1193         Contribute the following changes:
1194         2005-02-16  Dave Brolley  <brolley@redhat.com>
1195
1196         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1197         cgen_isa_mask_* to cgen_bitset_*.
1198         * cgen.h: Likewise.
1199
1200         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1201
1202         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1203         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1204         (CGEN_CPU_TABLE): Make isas a ponter.
1205
1206         2003-09-29  Dave Brolley  <brolley@redhat.com>
1207
1208         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1209         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1210         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1211
1212         2002-12-13  Dave Brolley  <brolley@redhat.com>
1213
1214         * cgen.h (symcat.h): #include it.
1215         (cgen-bitset.h): #include it.
1216         (CGEN_ATTR_VALUE_TYPE): Now a union.
1217         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1218         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1219         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1220         * cgen-bitset.h: New file.
1221
1222 2005-09-30  Catherine Moore  <clm@cm00re.com>
1223
1224         * bfin.h: New file.
1225
1226 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1227
1228         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1229         indirect operands.
1230
1231 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1232
1233         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1234         Add FLAG_STRICT to pa10 ftest opcode.
1235
1236 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1237
1238         * hppa.h (pa_opcodes): Remove lha entries.
1239
1240 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1241
1242         * hppa.h (FLAG_STRICT): Revise comment.
1243         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1244         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1245         entries for "fdc".
1246
1247 2005-09-30  Catherine Moore  <clm@cm00re.com>
1248
1249         * bfin.h: New file.
1250
1251 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1252
1253         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1254
1255 2005-09-06  Chao-ying Fu  <fu@mips.com>
1256
1257         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1258         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1259         define.
1260         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1261         (INSN_ASE_MASK): Update to include INSN_MT.
1262         (INSN_MT): New define for MT ASE.
1263
1264 2005-08-25  Chao-ying Fu  <fu@mips.com>
1265
1266         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1267         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1268         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1269         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1270         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1271         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1272         instructions.
1273         (INSN_DSP): New define for DSP ASE.
1274
1275 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1276
1277         * a29k.h: Delete.
1278
1279 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1280
1281         * ppc.h (PPC_OPCODE_E300): Define.
1282
1283 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1284
1285         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1286
1287 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1288
1289         PR gas/336
1290         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1291         and pitlb.
1292
1293 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1294
1295         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1296         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1297         Add movq-s as 64-bit variants of movd-s.
1298
1299 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1300
1301         * hppa.h: Fix punctuation in comment.
1302
1303         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1304         implicit space-register addressing.  Set space-register bits on opcodes
1305         using implicit space-register addressing.  Add various missing pa20
1306         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1307         space-register addressing.  Use "fE" instead of "fe" in various
1308         fstw opcodes.
1309
1310 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1311
1312         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1313
1314 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1315
1316         * i386.h (i386_optab): Support Intel VMX Instructions.
1317
1318 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1319
1320         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1321
1322 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1323
1324         * i386.h (i386_optab): Add new insns.
1325
1326 2005-07-01  Nick Clifton  <nickc@redhat.com>
1327
1328         * sparc.h: Add typedefs to structure declarations.
1329
1330 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1331
1332         PR 1013
1333         * i386.h (i386_optab): Update comments for 64bit addressing on
1334         mov. Allow 64bit addressing for mov and movq.
1335
1336 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1337
1338         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1339         respectively, in various floating-point load and store patterns.
1340
1341 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1342
1343         * hppa.h (FLAG_STRICT): Correct comment.
1344         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1345         PA 2.0 mneumonics when equivalent.  Entries with cache control
1346         completers now require PA 1.1.  Adjust whitespace.
1347
1348 2005-05-19  Anton Blanchard  <anton@samba.org>
1349
1350         * ppc.h (PPC_OPCODE_POWER5): Define.
1351
1352 2005-05-10  Nick Clifton  <nickc@redhat.com>
1353
1354         * Update the address and phone number of the FSF organization in
1355         the GPL notices in the following files:
1356         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1357         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1358         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1359         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1360         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1361         tic54x.h, tic80.h, v850.h, vax.h
1362
1363 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1364
1365         * i386.h (i386_optab): Add ht and hnt.
1366
1367 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1368
1369         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1370         Add xcrypt-ctr.  Provide aliases without hyphens.
1371
1372 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1373
1374         Moved from ../ChangeLog
1375
1376         2005-04-12  Paul Brook  <paul@codesourcery.com>
1377         * m88k.h: Rename psr macros to avoid conflicts.
1378
1379         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1380         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1381         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1382         and ARM_ARCH_V6ZKT2.
1383
1384         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1385         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1386         Remove redundant instruction types.
1387         (struct argument): X_op - new field.
1388         (struct cst4_entry): Remove.
1389         (no_op_insn): Declare.
1390
1391         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1392         * crx.h (enum argtype): Rename types, remove unused types.
1393
1394         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1395         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1396         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1397         (enum operand_type): Rearrange operands, edit comments.
1398         replace us<N> with ui<N> for unsigned immediate.
1399         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1400         displacements (respectively).
1401         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1402         (instruction type): Add NO_TYPE_INS.
1403         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1404         (operand_entry): New field - 'flags'.
1405         (operand flags): New.
1406
1407         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1408         * crx.h (operand_type): Remove redundant types i3, i4,
1409         i5, i8, i12.
1410         Add new unsigned immediate types us3, us4, us5, us16.
1411
1412 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1413
1414         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1415         adjust them accordingly.
1416
1417 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1418
1419         * i386.h (i386_optab): Add rdtscp.
1420
1421 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1422
1423         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1424         between memory and segment register. Allow movq for moving between
1425         general-purpose register and segment register.
1426
1427 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1428
1429         PR gas/707
1430         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1431         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1432         fnstsw.
1433
1434 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1435
1436         * m68k.h (m68008, m68ec030, m68882): Remove.
1437         (m68k_mask): New.
1438         (cpu_m68k, cpu_cf): New.
1439         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1440         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1441
1442 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1443
1444         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1445         * cgen.h (enum cgen_parse_operand_type): Add
1446         CGEN_PARSE_OPERAND_SYMBOLIC.
1447
1448 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1449
1450         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1451         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1452         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1453
1454 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1455
1456         * mips.h (struct mips_opcode): Add new pinfo2 member.
1457         (INSN_ALIAS): New define for opcode table entries that are
1458         specific instances of another entry, such as 'move' for an 'or'
1459         with a zero operand.
1460         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1461         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1462
1463 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1464
1465         * mips.h (CPU_RM9000): Define.
1466         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1467
1468 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1469
1470         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1471         to/from test registers are illegal in 64-bit mode. Add missing
1472         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1473         (previously one had to explicitly encode a rex64 prefix). Re-enable
1474         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1475         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1476
1477 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1478
1479         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1480         available only with SSE2. Change the MMX additions introduced by SSE
1481         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1482         instructions by their now designated identifier (since combining i686
1483         and 3DNow! does not really imply 3DNow!A).
1484
1485 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1486
1487         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1488         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1489
1490 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1491             Vineet Sharma      <vineets@noida.hcltech.com>
1492
1493         * maxq.h: New file: Disassembly information for the maxq port.
1494
1495 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1496
1497         * i386.h (i386_optab): Put back "movzb".
1498
1499 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1500
1501         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1502         comments.  Remove member cris_ver_sim.  Add members
1503         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1504         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1505         (struct cris_support_reg, struct cris_cond15): New types.
1506         (cris_conds15): Declare.
1507         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1508         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1509         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1510         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1511         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1512         SIZE_FIELD_UNSIGNED.
1513
1514 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1515
1516         * i386.h (sldx_Suf): Remove.
1517         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1518         (q_FP): Define, implying no REX64.
1519         (x_FP, sl_FP): Imply FloatMF.
1520         (i386_optab): Split reg and mem forms of moving from segment registers
1521         so that the memory forms can ignore the 16-/32-bit operand size
1522         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1523         all non-floating-point instructions. Unite 32- and 64-bit forms of
1524         movsx, movzx, and movd. Adjust floating point operations for the above
1525         changes to the *FP macros. Add DefaultSize to floating point control
1526         insns operating on larger memory ranges. Remove left over comments
1527         hinting at certain insns being Intel-syntax ones where the ones
1528         actually meant are already gone.
1529
1530 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1531
1532         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1533         instruction type.
1534
1535 2004-09-30  Paul Brook  <paul@codesourcery.com>
1536
1537         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1538         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1539
1540 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1541
1542         * avr.h: Add support for
1543         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1544
1545 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1546
1547         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1548
1549 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1550
1551         * msp430.h (msp430_opc): Add new instructions.
1552         (msp430_rcodes): Declare new instructions.
1553         (msp430_hcodes): Likewise..
1554
1555 2004-08-13  Nick Clifton  <nickc@redhat.com>
1556
1557         PR/301
1558         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1559         processors.
1560
1561 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1562
1563         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1564
1565 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1566
1567         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1568
1569 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1570
1571         * i386.h: Adjust instruction descriptions to better match the
1572         specification.
1573
1574 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1575
1576         * arm.h: Remove all old content.  Replace with architecture defines
1577         from gas/config/tc-arm.c.
1578
1579 2004-07-09  Andreas Schwab  <schwab@suse.de>
1580
1581         * m68k.h: Fix comment.
1582
1583 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1584
1585         * crx.h: New file.
1586
1587 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1588
1589         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1590
1591 2004-05-24  Peter Barada  <peter@the-baradas.com>
1592
1593         * m68k.h: Add 'size' to m68k_opcode.
1594
1595 2004-05-05  Peter Barada  <peter@the-baradas.com>
1596
1597         * m68k.h: Switch from ColdFire chip name to core variant.
1598
1599 2004-04-22  Peter Barada  <peter@the-baradas.com>
1600
1601         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1602         descriptions for new EMAC cases.
1603         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1604         handle Motorola MAC syntax.
1605         Allow disassembly of ColdFire V4e object files.
1606
1607 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1608
1609         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1610
1611 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1612
1613         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1614
1615 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1616
1617         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1618
1619 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1620
1621         * i386.h (i386_optab): Added xstore/xcrypt insns.
1622
1623 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1624
1625         * h8300.h (32bit ldc/stc): Add relaxing support.
1626
1627 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1628
1629         * h8300.h (BITOP): Pass MEMRELAX flag.
1630
1631 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1632
1633         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1634         except for the H8S.
1635
1636 For older changes see ChangeLog-9103
1637 \f
1638 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1639
1640 Copying and distribution of this file, with or without modification,
1641 are permitted in any medium without royalty provided the copyright
1642 notice and this notice are preserved.
1643
1644 Local Variables:
1645 mode: change-log
1646 left-margin: 8
1647 fill-column: 74
1648 version-control: never
1649 End: