include/opcode/ChangeLog

   1 2013-04-03  Nick Clifton  <nickc@redhat.com>
   2
   3         * v850.h (V850_INVERSE_PCREL): Define.
   4
   5 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
   6
   7         PR binutils/15068
   8         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
   9
  10 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  11
  12         PR binutils/15068
  13         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
  14         Add 16-bit opcodes.
  15         * tic6xc-opcode-table.h: Add 16-bit insns.
  16         * tic6x.h: Add support for 16-bit insns.
  17
  18 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
  19
  20         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
  21         and mov.b/w/l Rs,@(d:32,ERd).
  22
  23 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  24
  25         PR gas/15082
  26         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
  27         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
  28         tic6x_operand_xregpair operand coding type.
  29         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
  30         opcode field, usu ORXREGD1324 for the src2 operand and remove the
  31         TIC6X_FLAG_NO_CROSS.
  32
  33 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  34
  35         PR gas/15095
  36         * tic6x.h (enum tic6x_coding_method): Add
  37         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
  38         separately the msb and lsb of a register pair.  This is needed to
  39         encode the opcodes in the same way as TI assembler does.
  40         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
  41         and rsqrdp opcodes to use the new field coding types.
  42
  43 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  44
  45         * arm.h (CRC_EXT_ARMV8): New constant.
  46         (ARCH_CRC_ARMV8): New macro.
  47
  48 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
  49
  50         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
  51
  52 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  53             Andrew Jenner <andrew@codesourcery.com>
  54
  55         Based on patches from Altera Corporation.
  56
  57         * nios2.h: New file.
  58
  59 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  60
  61         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
  62
  63 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
  64
  65         PR gas/15069
  66         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
  67
  68 2013-01-24  Nick Clifton  <nickc@redhat.com>
  69
  70         * v850.h: Add e3v5 support.
  71
  72 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  73
  74         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
  75
  76 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  77
  78         * ppc.h (PPC_OPCODE_POWER8): New define.
  79         (PPC_OPCODE_HTM): Likewise.
  80
  81 2013-01-10  Will Newton <will.newton@imgtec.com>
  82
  83         * metag.h: New file.
  84
  85 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  86
  87         * cr16.h (make_instruction): Rename to cr16_make_instruction.
  88         (match_opcode): Rename to cr16_match_opcode.
  89
  90 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
  91
  92         * mips.h: Add support for r5900 instructions including lq and sq.
  93
  94 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  95
  96         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
  97         (make_instruction,match_opcode): Added function prototypes.
  98         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
  99
 100 2012-11-23  Alan Modra  <amodra@gmail.com>
 101
 102         * ppc.h (ppc_parse_cpu): Update prototype.
 103
 104 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 105
 106         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 107         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 108
 109 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 110
 111         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 112
 113 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 114
 115         * ia64.h (ia64_opnd): Add new operand types.
 116
 117 2012-08-21  David S. Miller  <davem@davemloft.net>
 118
 119         * sparc.h (F3F4): New macro.
 120
 121 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 122             Laurent Desnogues  <laurent.desnogues@arm.com>
 123             Jim MacArthur  <jim.macarthur@arm.com>
 124             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 125             Nigel Stephens  <nigel.stephens@arm.com>
 126             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 127             Richard Earnshaw  <rearnsha@arm.com>
 128             Sofiane Naci  <sofiane.naci@arm.com>
 129             Tejas Belagod  <tejas.belagod@arm.com>
 130             Yufeng Zhang  <yufeng.zhang@arm.com>
 131
 132         * aarch64.h: New file.
 133
 134 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 135             Maciej W. Rozycki  <macro@codesourcery.com>
 136
 137         * mips.h (mips_opcode): Add the exclusions field.
 138         (OPCODE_IS_MEMBER): Remove macro.
 139         (cpu_is_member): New inline function.
 140         (opcode_is_member): Likewise.
 141
 142 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 143             Catherine Moore  <clm@codesourcery.com>
 144             Maciej W. Rozycki  <macro@codesourcery.com>
 145
 146         * mips.h: Document microMIPS DSP ASE usage.
 147         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 148         microMIPS DSP ASE support.
 149         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 150         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 151         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 152         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 153         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 154         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 155         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 156
 157 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 158
 159         * mips.h: Fix a typo in description.
 160
 161 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 162
 163         * avr.h: (AVR_ISA_XCH): New define.
 164         (AVR_ISA_XMEGA): Use it.
 165         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 166
 167 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 168
 169         * m68hc11.h: Add XGate definitions.
 170         (struct m68hc11_opcode): Add xg_mask field.
 171
 172 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 173             Maciej W. Rozycki  <macro@codesourcery.com>
 174             Rhonda Wittels  <rhonda@codesourcery.com>
 175
 176         * ppc.h (PPC_OPCODE_VLE): New definition.
 177         (PPC_OP_SA): New macro.
 178         (PPC_OP_SE_VLE): New macro.
 179         (PPC_OP): Use a variable shift amount.
 180         (powerpc_operand): Update comments.
 181         (PPC_OPSHIFT_INV): New macro.
 182         (PPC_OPERAND_CR): Replace with...
 183         (PPC_OPERAND_CR_BIT): ...this and
 184         (PPC_OPERAND_CR_REG): ...this.
 185
 186
 187 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 188
 189         * xgate.h: Header file for XGATE assembler.
 190
 191 2012-04-27  David S. Miller  <davem@davemloft.net>
 192
 193         * sparc.h: Document new arg code' )' for crypto RS3
 194         immediates.
 195
 196         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 197         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 198         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 199         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 200         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 201         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 202         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 203         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 204         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 205         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 206         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 207
 208 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 209
 210         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 211
 212 2012-02-27  Alan Modra  <amodra@gmail.com>
 213
 214         * crx.h (cst4_map): Update declaration.
 215
 216 2012-02-25  Walter Lee  <walt@tilera.com>
 217
 218         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 219         TILEGX_OPC_LD_TLS.
 220         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 221         TILEPRO_OPC_LW_TLS_SN.
 222
 223 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 226         (XRELEASE_PREFIX_OPCODE): Likewise.
 227
 228 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 229             Adam Nemet  <anemet@caviumnetworks.com>
 230
 231         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 232         (INSN_OCTEON2): New macro.
 233         (CPU_OCTEON2): New macro.
 234         (OPCODE_IS_MEMBER): Add Octeon2.
 235
 236 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 237
 238         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 239         (INSN_OCTEONP): New macro.
 240         (CPU_OCTEONP): New macro.
 241         (OPCODE_IS_MEMBER): Add Octeon+.
 242         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 243
 244 2011-11-01  DJ Delorie  <dj@redhat.com>
 245
 246         * rl78.h: New file.
 247
 248 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 249
 250         * mips.h: Fix a typo in description.
 251
 252 2011-09-21  David S. Miller  <davem@davemloft.net>
 253
 254         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 255         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 256         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 257         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 258
 259 2011-08-09  Chao-ying Fu  <fu@mips.com>
 260             Maciej W. Rozycki  <macro@codesourcery.com>
 261
 262         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 263         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 264         (INSN_ASE_MASK): Add the MCU bit.
 265         (INSN_MCU): New macro.
 266         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 267         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 268
 269 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 270
 271         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 272         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 273         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 274         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 275         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 276         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 277         (INSN2_READ_GPR_MMN): Likewise.
 278         (INSN2_READ_FPR_D): Change the bit used.
 279         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 280         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 281         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 282         (INSN2_COND_BRANCH): Likewise.
 283         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 284         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 285         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 286         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 287         (INSN2_MOD_GPR_MN): Likewise.
 288
 289 2011-08-05  David S. Miller  <davem@davemloft.net>
 290
 291         * sparc.h: Document new format codes '4', '5', and '('.
 292         (OPF_LOW4, RS3): New macros.
 293
 294 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 295
 296         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 297         order of flags documented.
 298
 299 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 300
 301         * mips.h: Clarify the description of microMIPS instruction
 302         manipulation macros.
 303         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 304
 305 2011-07-24  Chao-ying Fu  <fu@mips.com>
 306             Maciej W. Rozycki  <macro@codesourcery.com>
 307
 308         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 309         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 310         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 311         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 312         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 313         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 314         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 315         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 316         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 317         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 318         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 319         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 320         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 321         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 322         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 323         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 324         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 325         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 326         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 327         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 328         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 329         (INSN_WRITE_GPR_S): New macro.
 330         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 331         (INSN2_READ_FPR_D): Likewise.
 332         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 333         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 334         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 335         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 336         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 337         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 338         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 339         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 340         (CPU_MICROMIPS): New macro.
 341         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 342         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 343         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 344         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 345         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 346         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 347         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 348         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 349         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 350         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 351         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 352         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 353         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 354         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 355         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 356         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 357         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 358         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 359         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 360         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 361         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 362         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 363         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 364         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 365         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 366         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 367         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 368         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 369         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 370         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 371         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 372         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 373         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 374         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 375         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 376         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 377         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 378         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 379         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 380         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 381         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 382         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 383         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 384         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 385         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 386         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 387         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 388         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 389         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 390         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 391         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 392         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 393         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 394         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 395         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 396         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 397         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 398         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 399         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 400         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 401         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 402         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 403         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 404         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 405         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 406         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 407         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 408         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 409         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 410         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 411         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 412         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 413         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 414         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 415         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 416         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 417         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 418         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 419         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 420         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 421         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 422         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 423         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 424         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 425         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 426         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 427         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 428         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 429         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 430         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 431         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 432         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 433         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 434         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 435         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 436         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 437         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 438         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 439         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 440         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 441         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 442         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 443         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 444         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 445         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 446         (micromips_opcodes): New declaration.
 447         (bfd_micromips_num_opcodes): Likewise.
 448
 449 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 450
 451         * mips.h (INSN_TRAP): Rename to...
 452         (INSN_NO_DELAY_SLOT): ... this.
 453         (INSN_SYNC): Remove macro.
 454
 455 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 456
 457         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 458         a duplicate of AVR_ISA_SPM.
 459
 460 2011-07-01  Nick Clifton  <nickc@redhat.com>
 461
 462         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 463
 464 2011-06-18  Robin Getz  <robin.getz@analog.com>
 465
 466         * bfin.h (is_macmod_signed): New func
 467
 468 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 469
 470         * bfin.h (is_macmod_pmove): Add missing space before func args.
 471         (is_macmod_hmove): Likewise.
 472
 473 2011-06-13  Walter Lee  <walt@tilera.com>
 474
 475         * tilegx.h: New file.
 476         * tilepro.h: New file.
 477
 478 2011-05-31  Paul Brook  <paul@codesourcery.com>
 479
 480         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 481
 482 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 483
 484         * s390.h: Replace S390_OPERAND_REG_EVEN with
 485         S390_OPERAND_REG_PAIR.
 486
 487 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 488
 489         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 490
 491 2011-04-18  Julian Brown  <julian@codesourcery.com>
 492
 493         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 494
 495 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 496
 497         PR gas/12296
 498         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 499
 500 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 501
 502         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 503         New instruction set flags.
 504         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 505
 506 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 507
 508         * mips.h (M_PREF_AB): New enum value.
 509
 510 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 511
 512         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 513         M_IU): Define.
 514         (is_macmod_pmove, is_macmod_hmove): New functions.
 515
 516 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 517
 518         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 519
 520 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 521
 522         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 523         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 524
 525 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 526
 527         PR gas/11395
 528         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 529         "bb" entries.
 530
 531 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 532
 533         PR gas/11395
 534         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 535
 536 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 537
 538         * mips.h: Update commentary after last commit.
 539
 540 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 541
 542         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 543         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 544         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 545
 546 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 547
 548         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 549
 550 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 551
 552         * mips.h: Fix previous commit.
 553
 554 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 555
 556         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 557         (INSN_LOONGSON_3A): Clear bit 31.
 558
 559 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 560
 561         PR gas/12198
 562         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 563         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 564         (ARM_ARCH_V6M_ONLY): New define.
 565
 566 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 567
 568         * mips.h (INSN_LOONGSON_3A): Defined.
 569         (CPU_LOONGSON_3A): Defined.
 570         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 571
 572 2010-10-09  Matt Rice  <ratmice@gmail.com>
 573
 574         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 575         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 576
 577 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 578
 579         * arm.h (ARM_EXT_VIRT): New define.
 580         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 581         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 582         Extensions.
 583
 584 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 585
 586         * arm.h (ARM_AEXT_ADIV): New define.
 587         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 588
 589 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 590
 591         * arm.h (ARM_EXT_OS): New define.
 592         (ARM_AEXT_V6SM): Likewise.
 593         (ARM_ARCH_V6SM): Likewise.
 594
 595 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 596
 597         * arm.h (ARM_EXT_MP): Add.
 598         (ARM_ARCH_V7A_MP): Likewise.
 599
 600 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 601
 602         * bfin.h: Declare pseudoChr structs/defines.
 603
 604 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 605
 606         * bfin.h: Strip trailing whitespace.
 607
 608 2010-07-29  DJ Delorie  <dj@redhat.com>
 609
 610         * rx.h (RX_Operand_Type): Add TwoReg.
 611         (RX_Opcode_ID): Remove ediv and ediv2.
 612
 613 2010-07-27  DJ Delorie  <dj@redhat.com>
 614
 615         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 616
 617 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 618             Ina Pandit  <ina.pandit@kpitcummins.com>
 619
 620         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 621         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 622         PROCESSOR_V850E2_ALL.
 623         Remove PROCESSOR_V850EA support.
 624         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 625         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 626         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 627         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 628         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 629         V850_OPERAND_PERCENT.
 630         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 631         V850_NOT_R0.
 632         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 633         and V850E_PUSH_POP
 634
 635 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 636
 637         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 638         (MIPS16_INSN_BRANCH): Rename to...
 639         (MIPS16_INSN_COND_BRANCH): ... this.
 640
 641 2010-07-03  Alan Modra  <amodra@gmail.com>
 642
 643         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 644         Renumber other PPC_OPCODE defines.
 645
 646 2010-07-03  Alan Modra  <amodra@gmail.com>
 647
 648         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 649
 650 2010-06-29  Alan Modra  <amodra@gmail.com>
 651
 652         * maxq.h: Delete file.
 653
 654 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 655
 656         * ppc.h (PPC_OPCODE_E500): Define.
 657
 658 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 659
 660         * opcode/mips.h (INSN_MIPS16): Remove.
 661
 662 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 663
 664         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 665
 666 2010-04-15  Nick Clifton  <nickc@redhat.com>
 667
 668         * alpha.h: Update copyright notice to use GPLv3.
 669         * arc.h: Likewise.
 670         * arm.h: Likewise.
 671         * avr.h: Likewise.
 672         * bfin.h: Likewise.
 673         * cgen.h: Likewise.
 674         * convex.h: Likewise.
 675         * cr16.h: Likewise.
 676         * cris.h: Likewise.
 677         * crx.h: Likewise.
 678         * d10v.h: Likewise.
 679         * d30v.h: Likewise.
 680         * dlx.h: Likewise.
 681         * h8300.h: Likewise.
 682         * hppa.h: Likewise.
 683         * i370.h: Likewise.
 684         * i386.h: Likewise.
 685         * i860.h: Likewise.
 686         * i960.h: Likewise.
 687         * ia64.h: Likewise.
 688         * m68hc11.h: Likewise.
 689         * m68k.h: Likewise.
 690         * m88k.h: Likewise.
 691         * maxq.h: Likewise.
 692         * mips.h: Likewise.
 693         * mmix.h: Likewise.
 694         * mn10200.h: Likewise.
 695         * mn10300.h: Likewise.
 696         * msp430.h: Likewise.
 697         * np1.h: Likewise.
 698         * ns32k.h: Likewise.
 699         * or32.h: Likewise.
 700         * pdp11.h: Likewise.
 701         * pj.h: Likewise.
 702         * pn.h: Likewise.
 703         * ppc.h: Likewise.
 704         * pyr.h: Likewise.
 705         * rx.h: Likewise.
 706         * s390.h: Likewise.
 707         * score-datadep.h: Likewise.
 708         * score-inst.h: Likewise.
 709         * sparc.h: Likewise.
 710         * spu-insns.h: Likewise.
 711         * spu.h: Likewise.
 712         * tic30.h: Likewise.
 713         * tic4x.h: Likewise.
 714         * tic54x.h: Likewise.
 715         * tic80.h: Likewise.
 716         * v850.h: Likewise.
 717         * vax.h: Likewise.
 718
 719 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 720
 721         * tic6x-control-registers.h, tic6x-insn-formats.h,
 722         tic6x-opcode-table.h, tic6x.h: New.
 723
 724 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 725
 726         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 727
 728 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 729
 730         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 731
 732 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 733
 734         * ia64.h (ia64_find_opcode): Remove argument name.
 735         (ia64_find_next_opcode): Likewise.
 736         (ia64_dis_opcode): Likewise.
 737         (ia64_free_opcode): Likewise.
 738         (ia64_find_dependency): Likewise.
 739
 740 2009-11-22  Doug Evans  <dje@sebabeach.org>
 741
 742         * cgen.h: Include bfd_stdint.h.
 743         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 744
 745 2009-11-18  Paul Brook  <paul@codesourcery.com>
 746
 747         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 748
 749 2009-11-17  Paul Brook  <paul@codesourcery.com>
 750         Daniel Jacobowitz  <dan@codesourcery.com>
 751
 752         * arm.h (ARM_EXT_V6_DSP): Define.
 753         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 754         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 755
 756 2009-11-04  DJ Delorie  <dj@redhat.com>
 757
 758         * rx.h (rx_decode_opcode) (mvtipl): Add.
 759         (mvtcp, mvfcp, opecp): Remove.
 760
 761 2009-11-02  Paul Brook  <paul@codesourcery.com>
 762
 763         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 764         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 765         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 766         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 767         FPU_ARCH_NEON_VFP_V4): Define.
 768
 769 2009-10-23  Doug Evans  <dje@sebabeach.org>
 770
 771         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 772         * cgen.h: Update.  Improve multi-inclusion macro name.
 773
 774 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 775
 776         * ppc.h (PPC_OPCODE_476): Define.
 777
 778 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 779
 780         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 781
 782 2009-09-29  DJ Delorie  <dj@redhat.com>
 783
 784         * rx.h: New file.
 785
 786 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 787
 788         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 789
 790 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 791
 792         * ppc.h (PPC_OPCODE_PPCA2): New.
 793
 794 2009-09-05  Martin Thuresson  <martin@mtme.org>
 795
 796         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 797
 798 2009-08-29  Martin Thuresson  <martin@mtme.org>
 799
 800         * tic30.h (template): Rename type template to
 801         insn_template. Updated code to use new name.
 802         * tic54x.h (template): Rename type template to
 803         insn_template.
 804
 805 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 806
 807         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 808
 809 2009-06-11  Anthony Green  <green@moxielogic.com>
 810
 811         * moxie.h (MOXIE_F3_PCREL): Define.
 812         (moxie_form3_opc_info): Grow.
 813
 814 2009-06-06  Anthony Green  <green@moxielogic.com>
 815
 816         * moxie.h (MOXIE_F1_M): Define.
 817
 818 2009-04-15  Anthony Green  <green@moxielogic.com>
 819
 820         * moxie.h: Created.
 821
 822 2009-04-06  DJ Delorie  <dj@redhat.com>
 823
 824         * h8300.h: Add relaxation attributes to MOVA opcodes.
 825
 826 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 827
 828         * ppc.h (ppc_parse_cpu): Declare.
 829
 830 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 831
 832         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 833         and _IMM11 for mbitclr and mbitset.
 834         * score-datadep.h: Update dependency information.
 835
 836 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 837
 838         * ppc.h (PPC_OPCODE_POWER7): New.
 839
 840 2009-02-06  Doug Evans  <dje@google.com>
 841
 842         * i386.h: Add comment regarding sse* insns and prefixes.
 843
 844 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 845
 846         * mips.h (INSN_XLR): Define.
 847         (INSN_CHIP_MASK): Update.
 848         (CPU_XLR): Define.
 849         (OPCODE_IS_MEMBER): Update.
 850         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 851
 852 2009-01-28  Doug Evans  <dje@google.com>
 853
 854         * opcode/i386.h: Add multiple inclusion protection.
 855         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 856         (EDI_REG_NUM): New macros.
 857         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 858         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 859         (REX_PREFIX_P): New macro.
 860
 861 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 862
 863         * ppc.h (struct powerpc_opcode): New field "deprecated".
 864         (PPC_OPCODE_NOPOWER4): Delete.
 865
 866 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 867
 868         * mips.h: Define CPU_R14000, CPU_R16000.
 869         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 870
 871 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 872
 873         * arm.h (FPU_NEON_FP16): New.
 874         (FPU_ARCH_NEON_FP16): New.
 875
 876 2008-11-06  Chao-ying Fu  <fu@mips.com>
 877
 878         * mips.h: Doucument '1' for 5-bit sync type.
 879
 880 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 883         IA64_RS_CR.
 884
 885 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 886
 887         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 888
 889 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 890
 891         * ppc.h (PPC_OPCODE_405): Define.
 892         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 893
 894 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 895
 896         * ppc.h (ppc_cpu_t): New typedef.
 897         (struct powerpc_opcode <flags>): Use it.
 898         (struct powerpc_operand <insert, extract>): Likewise.
 899         (struct powerpc_macro <flags>): Likewise.
 900
 901 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 902
 903         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 904         Update comment before MIPS16 field descriptors to mention MIPS16.
 905         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 906         BBIT.
 907         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 908         New bit masks and shift counts for cins and exts.
 909
 910         * mips.h: Document new field descriptors +Q.
 911         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 912
 913 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 914
 915         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 916         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 917
 918 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 919
 920         * ppc.h: (PPC_OPCODE_E500MC): New.
 921
 922 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         * i386.h (MAX_OPERANDS): Set to 5.
 925         (MAX_MNEM_SIZE): Changed to 20.
 926
 927 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 928
 929         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 930
 931 2008-03-09  Paul Brook  <paul@codesourcery.com>
 932
 933         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 934
 935 2008-03-04  Paul Brook  <paul@codesourcery.com>
 936
 937         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 938         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 939         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 940
 941 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 942             Nick Clifton  <nickc@redhat.com>
 943
 944         PR 3134
 945         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 946         with a 32-bit displacement but without the top bit of the 4th byte
 947         set.
 948
 949 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 950
 951         * cr16.h (cr16_num_optab): Declared.
 952
 953 2008-02-14  Hakan Ardo  <hakan@debian.org>
 954
 955         PR gas/2626
 956         * avr.h (AVR_ISA_2xxe): Define.
 957
 958 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 959
 960         * mips.h: Update copyright.
 961         (INSN_CHIP_MASK): New macro.
 962         (INSN_OCTEON): New macro.
 963         (CPU_OCTEON): New macro.
 964         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 965
 966 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 967
 968         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 969
 970 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 971
 972         * avr.h (AVR_ISA_USB162): Add new opcode set.
 973         (AVR_ISA_AVR3): Likewise.
 974
 975 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 976
 977         * mips.h (INSN_LOONGSON_2E): New.
 978         (INSN_LOONGSON_2F): New.
 979         (CPU_LOONGSON_2E): New.
 980         (CPU_LOONGSON_2F): New.
 981         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 982
 983 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 984
 985         * mips.h (INSN_ISA*): Redefine certain values as an
 986         enumeration.  Update comments.
 987         (mips_isa_table): New.
 988         (ISA_MIPS*): Redefine to match enumeration.
 989         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 990         values.
 991
 992 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 993
 994         * ppc.h (PPC_OPCODE_PPCPS): New.
 995
 996 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 997
 998         * m68k.h: Document j K & E.
 999
1000 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1001
1002         * cr16.h: New file for CR16 target.
1003
1004 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1005
1006         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1007
1008 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1009
1010         * m68k.h (mcfisa_c): New.
1011         (mcfusp, mcf_mask): Adjust.
1012
1013 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1014
1015         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1016         (num_powerpc_operands): Declare.
1017         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1018         (PPC_OPERAND_PLUS1): Define.
1019
1020 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1021
1022         * i386.h (REX_MODE64): Renamed to ...
1023         (REX_W): This.
1024         (REX_EXTX): Renamed to ...
1025         (REX_R): This.
1026         (REX_EXTY): Renamed to ...
1027         (REX_X): This.
1028         (REX_EXTZ): Renamed to ...
1029         (REX_B): This.
1030
1031 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1032
1033         * i386.h: Add entries from config/tc-i386.h and move tables
1034         to opcodes/i386-opc.h.
1035
1036 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1037
1038         * i386.h (FloatDR): Removed.
1039         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1040
1041 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1042
1043         * spu-insns.h: Add soma double-float insns.
1044
1045 2007-02-20  Thiemo Seufer  <ths@mips.com>
1046             Chao-Ying Fu  <fu@mips.com>
1047
1048         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1049         (INSN_DSPR2): Add flag for DSP R2 instructions.
1050         (M_BALIGN): New macro.
1051
1052 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1053
1054         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1055         and Seg3ShortFrom with Shortform.
1056
1057 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         PR gas/4027
1060         * i386.h (i386_optab): Put the real "test" before the pseudo
1061         one.
1062
1063 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1064
1065         * m68k.h (m68010up): OR fido_a.
1066
1067 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1068
1069         * m68k.h (fido_a): New.
1070
1071 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1072
1073         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1074         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1075         values.
1076
1077 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1078
1079         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1080
1081 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1082
1083         * score-inst.h (enum score_insn_type): Add Insn_internal.
1084
1085 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1086             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1087             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1088             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1089             Alan Modra  <amodra@bigpond.net.au>
1090
1091         * spu-insns.h: New file.
1092         * spu.h: New file.
1093
1094 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1095
1096         * ppc.h (PPC_OPCODE_CELL): Define.
1097
1098 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1099
1100         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1101         in amdfam10 architecture.
1102
1103 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * i386.h: Replace CpuMNI with CpuSSSE3.
1106
1107 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1108             Joseph Myers  <joseph@codesourcery.com>
1109             Ian Lance Taylor  <ian@wasabisystems.com>
1110             Ben Elliston  <bje@wasabisystems.com>
1111
1112         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1113
1114 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1115
1116         * score-datadep.h: New file.
1117         * score-inst.h: New file.
1118
1119 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1120
1121         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1122         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1123         movdq2q and movq2dq.
1124
1125 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1126            Michael Meissner             <michael.meissner@amd.com>
1127
1128         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1129
1130 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         * i386.h (i386_optab): Add "nop" with memory reference.
1133
1134 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1135
1136         * i386.h (i386_optab): Update comment for 64bit NOP.
1137
1138 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1139             Anton Blanchard  <anton@samba.org>
1140
1141         * ppc.h (PPC_OPCODE_POWER6): Define.
1142         Adjust whitespace.
1143
1144 2006-06-05  Thiemo Seufer  <ths@mips.com>
1145
1146         * mips.h: Improve description of MT flags.
1147
1148 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1149
1150         * m68k.h (mcf_mask): Define.
1151
1152 2006-05-05  Thiemo Seufer  <ths@mips.com>
1153             David Ung  <davidu@mips.com>
1154
1155         * mips.h (enum): Add macro M_CACHE_AB.
1156
1157 2006-05-04  Thiemo Seufer  <ths@mips.com>
1158             Nigel Stephens  <nigel@mips.com>
1159             David Ung  <davidu@mips.com>
1160
1161         * mips.h: Add INSN_SMARTMIPS define.
1162
1163 2006-04-30  Thiemo Seufer  <ths@mips.com>
1164             David Ung  <davidu@mips.com>
1165
1166         * mips.h: Defines udi bits and masks.  Add description of
1167         characters which may appear in the args field of udi
1168         instructions.
1169
1170 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1171
1172         * mips.h: Improve comments describing the bitfield instruction
1173         fields.
1174
1175 2006-04-26  Julian Brown  <julian@codesourcery.com>
1176
1177         * arm.h (FPU_VFP_EXT_V3): Define constant.
1178         (FPU_NEON_EXT_V1): Likewise.
1179         (FPU_VFP_HARD): Update.
1180         (FPU_VFP_V3): Define macro.
1181         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1182
1183 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1184
1185         * avr.h (AVR_ISA_PWMx): New.
1186
1187 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1188
1189         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1190         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1191         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1192         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1193         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1194
1195 2006-03-10  Paul Brook  <paul@codesourcery.com>
1196
1197         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1198
1199 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1200
1201         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1202         first.  Correct mask of bb "B" opcode.
1203
1204 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1205
1206         * i386.h (i386_optab): Support Intel Merom New Instructions.
1207
1208 2006-02-24  Paul Brook  <paul@codesourcery.com>
1209
1210         * arm.h: Add V7 feature bits.
1211
1212 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1213
1214         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1215
1216 2006-01-31  Paul Brook  <paul@codesourcery.com>
1217         Richard Earnshaw <rearnsha@arm.com>
1218
1219         * arm.h: Use ARM_CPU_FEATURE.
1220         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1221         (arm_feature_set): Change to a structure.
1222         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1223         ARM_FEATURE): New macros.
1224
1225 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1226
1227         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1228         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1229         (ADD_PC_INCR_OPCODE): Don't define.
1230
1231 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1232
1233         PR gas/1874
1234         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1235
1236 2005-11-14  David Ung  <davidu@mips.com>
1237
1238         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1239         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1240         save/restore encoding of the args field.
1241
1242 2005-10-28  Dave Brolley  <brolley@redhat.com>
1243
1244         Contribute the following changes:
1245         2005-02-16  Dave Brolley  <brolley@redhat.com>
1246
1247         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1248         cgen_isa_mask_* to cgen_bitset_*.
1249         * cgen.h: Likewise.
1250
1251         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1252
1253         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1254         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1255         (CGEN_CPU_TABLE): Make isas a ponter.
1256
1257         2003-09-29  Dave Brolley  <brolley@redhat.com>
1258
1259         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1260         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1261         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1262
1263         2002-12-13  Dave Brolley  <brolley@redhat.com>
1264
1265         * cgen.h (symcat.h): #include it.
1266         (cgen-bitset.h): #include it.
1267         (CGEN_ATTR_VALUE_TYPE): Now a union.
1268         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1269         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1270         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1271         * cgen-bitset.h: New file.
1272
1273 2005-09-30  Catherine Moore  <clm@cm00re.com>
1274
1275         * bfin.h: New file.
1276
1277 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1278
1279         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1280         indirect operands.
1281
1282 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1283
1284         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1285         Add FLAG_STRICT to pa10 ftest opcode.
1286
1287 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1288
1289         * hppa.h (pa_opcodes): Remove lha entries.
1290
1291 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1292
1293         * hppa.h (FLAG_STRICT): Revise comment.
1294         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1295         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1296         entries for "fdc".
1297
1298 2005-09-30  Catherine Moore  <clm@cm00re.com>
1299
1300         * bfin.h: New file.
1301
1302 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1303
1304         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1305
1306 2005-09-06  Chao-ying Fu  <fu@mips.com>
1307
1308         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1309         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1310         define.
1311         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1312         (INSN_ASE_MASK): Update to include INSN_MT.
1313         (INSN_MT): New define for MT ASE.
1314
1315 2005-08-25  Chao-ying Fu  <fu@mips.com>
1316
1317         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1318         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1319         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1320         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1321         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1322         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1323         instructions.
1324         (INSN_DSP): New define for DSP ASE.
1325
1326 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1327
1328         * a29k.h: Delete.
1329
1330 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1331
1332         * ppc.h (PPC_OPCODE_E300): Define.
1333
1334 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1335
1336         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1337
1338 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1339
1340         PR gas/336
1341         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1342         and pitlb.
1343
1344 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1345
1346         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1347         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1348         Add movq-s as 64-bit variants of movd-s.
1349
1350 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1351
1352         * hppa.h: Fix punctuation in comment.
1353
1354         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1355         implicit space-register addressing.  Set space-register bits on opcodes
1356         using implicit space-register addressing.  Add various missing pa20
1357         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1358         space-register addressing.  Use "fE" instead of "fe" in various
1359         fstw opcodes.
1360
1361 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1362
1363         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1364
1365 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1366
1367         * i386.h (i386_optab): Support Intel VMX Instructions.
1368
1369 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1370
1371         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1372
1373 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1374
1375         * i386.h (i386_optab): Add new insns.
1376
1377 2005-07-01  Nick Clifton  <nickc@redhat.com>
1378
1379         * sparc.h: Add typedefs to structure declarations.
1380
1381 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         PR 1013
1384         * i386.h (i386_optab): Update comments for 64bit addressing on
1385         mov. Allow 64bit addressing for mov and movq.
1386
1387 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1388
1389         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1390         respectively, in various floating-point load and store patterns.
1391
1392 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1393
1394         * hppa.h (FLAG_STRICT): Correct comment.
1395         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1396         PA 2.0 mneumonics when equivalent.  Entries with cache control
1397         completers now require PA 1.1.  Adjust whitespace.
1398
1399 2005-05-19  Anton Blanchard  <anton@samba.org>
1400
1401         * ppc.h (PPC_OPCODE_POWER5): Define.
1402
1403 2005-05-10  Nick Clifton  <nickc@redhat.com>
1404
1405         * Update the address and phone number of the FSF organization in
1406         the GPL notices in the following files:
1407         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1408         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1409         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1410         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1411         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1412         tic54x.h, tic80.h, v850.h, vax.h
1413
1414 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1415
1416         * i386.h (i386_optab): Add ht and hnt.
1417
1418 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1419
1420         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1421         Add xcrypt-ctr.  Provide aliases without hyphens.
1422
1423 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1424
1425         Moved from ../ChangeLog
1426
1427         2005-04-12  Paul Brook  <paul@codesourcery.com>
1428         * m88k.h: Rename psr macros to avoid conflicts.
1429
1430         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1431         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1432         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1433         and ARM_ARCH_V6ZKT2.
1434
1435         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1436         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1437         Remove redundant instruction types.
1438         (struct argument): X_op - new field.
1439         (struct cst4_entry): Remove.
1440         (no_op_insn): Declare.
1441
1442         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1443         * crx.h (enum argtype): Rename types, remove unused types.
1444
1445         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1446         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1447         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1448         (enum operand_type): Rearrange operands, edit comments.
1449         replace us<N> with ui<N> for unsigned immediate.
1450         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1451         displacements (respectively).
1452         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1453         (instruction type): Add NO_TYPE_INS.
1454         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1455         (operand_entry): New field - 'flags'.
1456         (operand flags): New.
1457
1458         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1459         * crx.h (operand_type): Remove redundant types i3, i4,
1460         i5, i8, i12.
1461         Add new unsigned immediate types us3, us4, us5, us16.
1462
1463 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1464
1465         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1466         adjust them accordingly.
1467
1468 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1469
1470         * i386.h (i386_optab): Add rdtscp.
1471
1472 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1473
1474         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1475         between memory and segment register. Allow movq for moving between
1476         general-purpose register and segment register.
1477
1478 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1479
1480         PR gas/707
1481         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1482         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1483         fnstsw.
1484
1485 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1486
1487         * m68k.h (m68008, m68ec030, m68882): Remove.
1488         (m68k_mask): New.
1489         (cpu_m68k, cpu_cf): New.
1490         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1491         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1492
1493 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1494
1495         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1496         * cgen.h (enum cgen_parse_operand_type): Add
1497         CGEN_PARSE_OPERAND_SYMBOLIC.
1498
1499 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1500
1501         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1502         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1503         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1504
1505 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1506
1507         * mips.h (struct mips_opcode): Add new pinfo2 member.
1508         (INSN_ALIAS): New define for opcode table entries that are
1509         specific instances of another entry, such as 'move' for an 'or'
1510         with a zero operand.
1511         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1512         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1513
1514 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1515
1516         * mips.h (CPU_RM9000): Define.
1517         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1518
1519 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1520
1521         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1522         to/from test registers are illegal in 64-bit mode. Add missing
1523         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1524         (previously one had to explicitly encode a rex64 prefix). Re-enable
1525         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1526         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1527
1528 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1529
1530         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1531         available only with SSE2. Change the MMX additions introduced by SSE
1532         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1533         instructions by their now designated identifier (since combining i686
1534         and 3DNow! does not really imply 3DNow!A).
1535
1536 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1537
1538         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1539         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1540
1541 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1542             Vineet Sharma      <vineets@noida.hcltech.com>
1543
1544         * maxq.h: New file: Disassembly information for the maxq port.
1545
1546 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1547
1548         * i386.h (i386_optab): Put back "movzb".
1549
1550 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1551
1552         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1553         comments.  Remove member cris_ver_sim.  Add members
1554         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1555         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1556         (struct cris_support_reg, struct cris_cond15): New types.
1557         (cris_conds15): Declare.
1558         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1559         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1560         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1561         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1562         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1563         SIZE_FIELD_UNSIGNED.
1564
1565 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1566
1567         * i386.h (sldx_Suf): Remove.
1568         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1569         (q_FP): Define, implying no REX64.
1570         (x_FP, sl_FP): Imply FloatMF.
1571         (i386_optab): Split reg and mem forms of moving from segment registers
1572         so that the memory forms can ignore the 16-/32-bit operand size
1573         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1574         all non-floating-point instructions. Unite 32- and 64-bit forms of
1575         movsx, movzx, and movd. Adjust floating point operations for the above
1576         changes to the *FP macros. Add DefaultSize to floating point control
1577         insns operating on larger memory ranges. Remove left over comments
1578         hinting at certain insns being Intel-syntax ones where the ones
1579         actually meant are already gone.
1580
1581 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1582
1583         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1584         instruction type.
1585
1586 2004-09-30  Paul Brook  <paul@codesourcery.com>
1587
1588         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1589         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1590
1591 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1592
1593         * avr.h: Add support for
1594         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1595
1596 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1597
1598         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1599
1600 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1601
1602         * msp430.h (msp430_opc): Add new instructions.
1603         (msp430_rcodes): Declare new instructions.
1604         (msp430_hcodes): Likewise..
1605
1606 2004-08-13  Nick Clifton  <nickc@redhat.com>
1607
1608         PR/301
1609         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1610         processors.
1611
1612 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1613
1614         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1615
1616 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1617
1618         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1619
1620 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1621
1622         * i386.h: Adjust instruction descriptions to better match the
1623         specification.
1624
1625 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1626
1627         * arm.h: Remove all old content.  Replace with architecture defines
1628         from gas/config/tc-arm.c.
1629
1630 2004-07-09  Andreas Schwab  <schwab@suse.de>
1631
1632         * m68k.h: Fix comment.
1633
1634 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1635
1636         * crx.h: New file.
1637
1638 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1639
1640         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1641
1642 2004-05-24  Peter Barada  <peter@the-baradas.com>
1643
1644         * m68k.h: Add 'size' to m68k_opcode.
1645
1646 2004-05-05  Peter Barada  <peter@the-baradas.com>
1647
1648         * m68k.h: Switch from ColdFire chip name to core variant.
1649
1650 2004-04-22  Peter Barada  <peter@the-baradas.com>
1651
1652         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1653         descriptions for new EMAC cases.
1654         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1655         handle Motorola MAC syntax.
1656         Allow disassembly of ColdFire V4e object files.
1657
1658 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1659
1660         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1661
1662 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1663
1664         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1665
1666 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1667
1668         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1669
1670 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1671
1672         * i386.h (i386_optab): Added xstore/xcrypt insns.
1673
1674 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1675
1676         * h8300.h (32bit ldc/stc): Add relaxing support.
1677
1678 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1679
1680         * h8300.h (BITOP): Pass MEMRELAX flag.
1681
1682 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1683
1684         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1685         except for the H8S.
1686
1687 For older changes see ChangeLog-9103
1688 \f
1689 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1690
1691 Copying and distribution of this file, with or without modification,
1692 are permitted in any medium without royalty provided the copyright
1693 notice and this notice are preserved.
1694
1695 Local Variables:
1696 mode: change-log
1697 left-margin: 8
1698 fill-column: 74
1699 version-control: never
1700 End: