include/opcode/ChangeLog

   1 2010-10-09  Matt Rice  <ratmice@gmail.com>
   2
   3         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
   4         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
   5
   6 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   7
   8         * arm.h (ARM_EXT_VIRT): New define.
   9         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
  10         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
  11         Extensions.
  12
  13 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  14
  15         * arm.h (ARM_AEXT_ADIV): New define.
  16         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
  17
  18 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  19
  20         * arm.h (ARM_EXT_OS): New define.
  21         (ARM_AEXT_V6SM): Likewise.
  22         (ARM_ARCH_V6SM): Likewise.
  23
  24 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  25
  26         * arm.h (ARM_EXT_MP): Add.
  27         (ARM_ARCH_V7A_MP): Likewise.
  28
  29 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  30
  31         * bfin.h: Declare pseudoChr structs/defines.
  32
  33 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
  34
  35         * bfin.h: Strip trailing whitespace.
  36
  37 2010-07-29  DJ Delorie  <dj@redhat.com>
  38
  39         * rx.h (RX_Operand_Type): Add TwoReg.
  40         (RX_Opcode_ID): Remove ediv and ediv2.
  41
  42 2010-07-27  DJ Delorie  <dj@redhat.com>
  43
  44         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
  45
  46 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
  47             Ina Pandit  <ina.pandit@kpitcummins.com>
  48
  49         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
  50         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
  51         PROCESSOR_V850E2_ALL.
  52         Remove PROCESSOR_V850EA support.
  53         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
  54         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
  55         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
  56         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
  57         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
  58         V850_OPERAND_PERCENT.
  59         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
  60         V850_NOT_R0.
  61         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
  62         and V850E_PUSH_POP
  63
  64 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
  65
  66         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
  67         (MIPS16_INSN_BRANCH): Rename to...
  68         (MIPS16_INSN_COND_BRANCH): ... this.
  69
  70 2010-07-03  Alan Modra  <amodra@gmail.com>
  71
  72         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
  73         Renumber other PPC_OPCODE defines.
  74
  75 2010-07-03  Alan Modra  <amodra@gmail.com>
  76
  77         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
  78
  79 2010-06-29  Alan Modra  <amodra@gmail.com>
  80
  81         * maxq.h: Delete file.
  82
  83 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
  84
  85         * ppc.h (PPC_OPCODE_E500): Define.
  86
  87 2010-05-26  Catherine Moore  <clm@codesourcery.com>
  88
  89         * opcode/mips.h (INSN_MIPS16): Remove.
  90
  91 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
  92
  93         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
  94
  95 2010-04-15  Nick Clifton  <nickc@redhat.com>
  96
  97         * alpha.h: Update copyright notice to use GPLv3.
  98         * arc.h: Likewise.
  99         * arm.h: Likewise.
 100         * avr.h: Likewise.
 101         * bfin.h: Likewise.
 102         * cgen.h: Likewise.
 103         * convex.h: Likewise.
 104         * cr16.h: Likewise.
 105         * cris.h: Likewise.
 106         * crx.h: Likewise.
 107         * d10v.h: Likewise.
 108         * d30v.h: Likewise.
 109         * dlx.h: Likewise.
 110         * h8300.h: Likewise.
 111         * hppa.h: Likewise.
 112         * i370.h: Likewise.
 113         * i386.h: Likewise.
 114         * i860.h: Likewise.
 115         * i960.h: Likewise.
 116         * ia64.h: Likewise.
 117         * m68hc11.h: Likewise.
 118         * m68k.h: Likewise.
 119         * m88k.h: Likewise.
 120         * maxq.h: Likewise.
 121         * mips.h: Likewise.
 122         * mmix.h: Likewise.
 123         * mn10200.h: Likewise.
 124         * mn10300.h: Likewise.
 125         * msp430.h: Likewise.
 126         * np1.h: Likewise.
 127         * ns32k.h: Likewise.
 128         * or32.h: Likewise.
 129         * pdp11.h: Likewise.
 130         * pj.h: Likewise.
 131         * pn.h: Likewise.
 132         * ppc.h: Likewise.
 133         * pyr.h: Likewise.
 134         * rx.h: Likewise.
 135         * s390.h: Likewise.
 136         * score-datadep.h: Likewise.
 137         * score-inst.h: Likewise.
 138         * sparc.h: Likewise.
 139         * spu-insns.h: Likewise.
 140         * spu.h: Likewise.
 141         * tic30.h: Likewise.
 142         * tic4x.h: Likewise.
 143         * tic54x.h: Likewise.
 144         * tic80.h: Likewise.
 145         * v850.h: Likewise.
 146         * vax.h: Likewise.
 147
 148 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 149
 150         * tic6x-control-registers.h, tic6x-insn-formats.h,
 151         tic6x-opcode-table.h, tic6x.h: New.
 152
 153 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 154
 155         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 156
 157 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 158
 159         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 160
 161 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         * ia64.h (ia64_find_opcode): Remove argument name.
 164         (ia64_find_next_opcode): Likewise.
 165         (ia64_dis_opcode): Likewise.
 166         (ia64_free_opcode): Likewise.
 167         (ia64_find_dependency): Likewise.
 168
 169 2009-11-22  Doug Evans  <dje@sebabeach.org>
 170
 171         * cgen.h: Include bfd_stdint.h.
 172         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 173
 174 2009-11-18  Paul Brook  <paul@codesourcery.com>
 175
 176         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 177
 178 2009-11-17  Paul Brook  <paul@codesourcery.com>
 179         Daniel Jacobowitz  <dan@codesourcery.com>
 180
 181         * arm.h (ARM_EXT_V6_DSP): Define.
 182         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 183         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 184
 185 2009-11-04  DJ Delorie  <dj@redhat.com>
 186
 187         * rx.h (rx_decode_opcode) (mvtipl): Add.
 188         (mvtcp, mvfcp, opecp): Remove.
 189
 190 2009-11-02  Paul Brook  <paul@codesourcery.com>
 191
 192         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 193         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 194         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 195         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 196         FPU_ARCH_NEON_VFP_V4): Define.
 197
 198 2009-10-23  Doug Evans  <dje@sebabeach.org>
 199
 200         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 201         * cgen.h: Update.  Improve multi-inclusion macro name.
 202
 203 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 204
 205         * ppc.h (PPC_OPCODE_476): Define.
 206
 207 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 208
 209         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 210
 211 2009-09-29  DJ Delorie  <dj@redhat.com>
 212
 213         * rx.h: New file.
 214
 215 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 216
 217         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 218
 219 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 220
 221         * ppc.h (PPC_OPCODE_PPCA2): New.
 222
 223 2009-09-05  Martin Thuresson  <martin@mtme.org>
 224
 225         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 226
 227 2009-08-29  Martin Thuresson  <martin@mtme.org>
 228
 229         * tic30.h (template): Rename type template to
 230         insn_template. Updated code to use new name.
 231         * tic54x.h (template): Rename type template to
 232         insn_template.
 233
 234 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 235
 236         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 237
 238 2009-06-11  Anthony Green  <green@moxielogic.com>
 239
 240         * moxie.h (MOXIE_F3_PCREL): Define.
 241         (moxie_form3_opc_info): Grow.
 242
 243 2009-06-06  Anthony Green  <green@moxielogic.com>
 244
 245         * moxie.h (MOXIE_F1_M): Define.
 246
 247 2009-04-15  Anthony Green  <green@moxielogic.com>
 248
 249         * moxie.h: Created.
 250
 251 2009-04-06  DJ Delorie  <dj@redhat.com>
 252
 253         * h8300.h: Add relaxation attributes to MOVA opcodes.
 254
 255 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 256
 257         * ppc.h (ppc_parse_cpu): Declare.
 258
 259 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 260
 261         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 262         and _IMM11 for mbitclr and mbitset.
 263         * score-datadep.h: Update dependency information.
 264
 265 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 266
 267         * ppc.h (PPC_OPCODE_POWER7): New.
 268
 269 2009-02-06  Doug Evans  <dje@google.com>
 270
 271         * i386.h: Add comment regarding sse* insns and prefixes.
 272
 273 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 274
 275         * mips.h (INSN_XLR): Define.
 276         (INSN_CHIP_MASK): Update.
 277         (CPU_XLR): Define.
 278         (OPCODE_IS_MEMBER): Update.
 279         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 280
 281 2009-01-28  Doug Evans  <dje@google.com>
 282
 283         * opcode/i386.h: Add multiple inclusion protection.
 284         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 285         (EDI_REG_NUM): New macros.
 286         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 287         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 288         (REX_PREFIX_P): New macro.
 289
 290 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 291
 292         * ppc.h (struct powerpc_opcode): New field "deprecated".
 293         (PPC_OPCODE_NOPOWER4): Delete.
 294
 295 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 296
 297         * mips.h: Define CPU_R14000, CPU_R16000.
 298         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 299
 300 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 301
 302         * arm.h (FPU_NEON_FP16): New.
 303         (FPU_ARCH_NEON_FP16): New.
 304
 305 2008-11-06  Chao-ying Fu  <fu@mips.com>
 306
 307         * mips.h: Doucument '1' for 5-bit sync type.
 308
 309 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 312         IA64_RS_CR.
 313
 314 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 315
 316         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 317
 318 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 319
 320         * ppc.h (PPC_OPCODE_405): Define.
 321         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 322
 323 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 324
 325         * ppc.h (ppc_cpu_t): New typedef.
 326         (struct powerpc_opcode <flags>): Use it.
 327         (struct powerpc_operand <insert, extract>): Likewise.
 328         (struct powerpc_macro <flags>): Likewise.
 329
 330 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 331
 332         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 333         Update comment before MIPS16 field descriptors to mention MIPS16.
 334         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 335         BBIT.
 336         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 337         New bit masks and shift counts for cins and exts.
 338
 339         * mips.h: Document new field descriptors +Q.
 340         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 341
 342 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 343
 344         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 345         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 346
 347 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 348
 349         * ppc.h: (PPC_OPCODE_E500MC): New.
 350
 351 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386.h (MAX_OPERANDS): Set to 5.
 354         (MAX_MNEM_SIZE): Changed to 20.
 355
 356 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 357
 358         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 359
 360 2008-03-09  Paul Brook  <paul@codesourcery.com>
 361
 362         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 363
 364 2008-03-04  Paul Brook  <paul@codesourcery.com>
 365
 366         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 367         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 368         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 369
 370 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 371             Nick Clifton  <nickc@redhat.com>
 372
 373         PR 3134
 374         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 375         with a 32-bit displacement but without the top bit of the 4th byte
 376         set.
 377
 378 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 379
 380         * cr16.h (cr16_num_optab): Declared.
 381
 382 2008-02-14  Hakan Ardo  <hakan@debian.org>
 383
 384         PR gas/2626
 385         * avr.h (AVR_ISA_2xxe): Define.
 386
 387 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 388
 389         * mips.h: Update copyright.
 390         (INSN_CHIP_MASK): New macro.
 391         (INSN_OCTEON): New macro.
 392         (CPU_OCTEON): New macro.
 393         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 394
 395 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 396
 397         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 398
 399 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 400
 401         * avr.h (AVR_ISA_USB162): Add new opcode set.
 402         (AVR_ISA_AVR3): Likewise.
 403
 404 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 405
 406         * mips.h (INSN_LOONGSON_2E): New.
 407         (INSN_LOONGSON_2F): New.
 408         (CPU_LOONGSON_2E): New.
 409         (CPU_LOONGSON_2F): New.
 410         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 411
 412 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 413
 414         * mips.h (INSN_ISA*): Redefine certain values as an
 415         enumeration.  Update comments.
 416         (mips_isa_table): New.
 417         (ISA_MIPS*): Redefine to match enumeration.
 418         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 419         values.
 420
 421 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 422
 423         * ppc.h (PPC_OPCODE_PPCPS): New.
 424
 425 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 426
 427         * m68k.h: Document j K & E.
 428
 429 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 430
 431         * cr16.h: New file for CR16 target.
 432
 433 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 434
 435         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 436
 437 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 438
 439         * m68k.h (mcfisa_c): New.
 440         (mcfusp, mcf_mask): Adjust.
 441
 442 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 443
 444         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 445         (num_powerpc_operands): Declare.
 446         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 447         (PPC_OPERAND_PLUS1): Define.
 448
 449 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 450
 451         * i386.h (REX_MODE64): Renamed to ...
 452         (REX_W): This.
 453         (REX_EXTX): Renamed to ...
 454         (REX_R): This.
 455         (REX_EXTY): Renamed to ...
 456         (REX_X): This.
 457         (REX_EXTZ): Renamed to ...
 458         (REX_B): This.
 459
 460 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         * i386.h: Add entries from config/tc-i386.h and move tables
 463         to opcodes/i386-opc.h.
 464
 465 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         * i386.h (FloatDR): Removed.
 468         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 469
 470 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 471
 472         * spu-insns.h: Add soma double-float insns.
 473
 474 2007-02-20  Thiemo Seufer  <ths@mips.com>
 475             Chao-Ying Fu  <fu@mips.com>
 476
 477         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 478         (INSN_DSPR2): Add flag for DSP R2 instructions.
 479         (M_BALIGN): New macro.
 480
 481 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 482
 483         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 484         and Seg3ShortFrom with Shortform.
 485
 486 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         PR gas/4027
 489         * i386.h (i386_optab): Put the real "test" before the pseudo
 490         one.
 491
 492 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 493
 494         * m68k.h (m68010up): OR fido_a.
 495
 496 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 497
 498         * m68k.h (fido_a): New.
 499
 500 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 501
 502         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 503         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 504         values.
 505
 506 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 509
 510 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 511
 512         * score-inst.h (enum score_insn_type): Add Insn_internal.
 513
 514 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 515             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 516             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 517             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 518             Alan Modra  <amodra@bigpond.net.au>
 519
 520         * spu-insns.h: New file.
 521         * spu.h: New file.
 522
 523 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 524
 525         * ppc.h (PPC_OPCODE_CELL): Define.
 526
 527 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 528
 529         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 530         in amdfam10 architecture.
 531
 532 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 533
 534         * i386.h: Replace CpuMNI with CpuSSSE3.
 535
 536 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 537             Joseph Myers  <joseph@codesourcery.com>
 538             Ian Lance Taylor  <ian@wasabisystems.com>
 539             Ben Elliston  <bje@wasabisystems.com>
 540
 541         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 542
 543 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 544
 545         * score-datadep.h: New file.
 546         * score-inst.h: New file.
 547
 548 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 551         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 552         movdq2q and movq2dq.
 553
 554 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 555            Michael Meissner             <michael.meissner@amd.com>
 556
 557         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 558
 559 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386.h (i386_optab): Add "nop" with memory reference.
 562
 563 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * i386.h (i386_optab): Update comment for 64bit NOP.
 566
 567 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 568             Anton Blanchard  <anton@samba.org>
 569
 570         * ppc.h (PPC_OPCODE_POWER6): Define.
 571         Adjust whitespace.
 572
 573 2006-06-05  Thiemo Seufer  <ths@mips.com>
 574
 575         * mips.h: Improve description of MT flags.
 576
 577 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 578
 579         * m68k.h (mcf_mask): Define.
 580
 581 2006-05-05  Thiemo Seufer  <ths@mips.com>
 582             David Ung  <davidu@mips.com>
 583
 584         * mips.h (enum): Add macro M_CACHE_AB.
 585
 586 2006-05-04  Thiemo Seufer  <ths@mips.com>
 587             Nigel Stephens  <nigel@mips.com>
 588             David Ung  <davidu@mips.com>
 589
 590         * mips.h: Add INSN_SMARTMIPS define.
 591
 592 2006-04-30  Thiemo Seufer  <ths@mips.com>
 593             David Ung  <davidu@mips.com>
 594
 595         * mips.h: Defines udi bits and masks.  Add description of
 596         characters which may appear in the args field of udi
 597         instructions.
 598
 599 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 600
 601         * mips.h: Improve comments describing the bitfield instruction
 602         fields.
 603
 604 2006-04-26  Julian Brown  <julian@codesourcery.com>
 605
 606         * arm.h (FPU_VFP_EXT_V3): Define constant.
 607         (FPU_NEON_EXT_V1): Likewise.
 608         (FPU_VFP_HARD): Update.
 609         (FPU_VFP_V3): Define macro.
 610         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 611
 612 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 613
 614         * avr.h (AVR_ISA_PWMx): New.
 615
 616 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 617
 618         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 619         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 620         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 621         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 622         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 623
 624 2006-03-10  Paul Brook  <paul@codesourcery.com>
 625
 626         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 627
 628 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 629
 630         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 631         first.  Correct mask of bb "B" opcode.
 632
 633 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 634
 635         * i386.h (i386_optab): Support Intel Merom New Instructions.
 636
 637 2006-02-24  Paul Brook  <paul@codesourcery.com>
 638
 639         * arm.h: Add V7 feature bits.
 640
 641 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 642
 643         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 644
 645 2006-01-31  Paul Brook  <paul@codesourcery.com>
 646         Richard Earnshaw <rearnsha@arm.com>
 647
 648         * arm.h: Use ARM_CPU_FEATURE.
 649         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 650         (arm_feature_set): Change to a structure.
 651         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 652         ARM_FEATURE): New macros.
 653
 654 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 655
 656         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 657         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 658         (ADD_PC_INCR_OPCODE): Don't define.
 659
 660 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 661
 662         PR gas/1874
 663         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 664
 665 2005-11-14  David Ung  <davidu@mips.com>
 666
 667         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 668         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 669         save/restore encoding of the args field.
 670
 671 2005-10-28  Dave Brolley  <brolley@redhat.com>
 672
 673         Contribute the following changes:
 674         2005-02-16  Dave Brolley  <brolley@redhat.com>
 675
 676         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 677         cgen_isa_mask_* to cgen_bitset_*.
 678         * cgen.h: Likewise.
 679
 680         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 681
 682         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 683         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 684         (CGEN_CPU_TABLE): Make isas a ponter.
 685
 686         2003-09-29  Dave Brolley  <brolley@redhat.com>
 687
 688         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 689         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 690         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 691
 692         2002-12-13  Dave Brolley  <brolley@redhat.com>
 693
 694         * cgen.h (symcat.h): #include it.
 695         (cgen-bitset.h): #include it.
 696         (CGEN_ATTR_VALUE_TYPE): Now a union.
 697         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 698         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 699         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 700         * cgen-bitset.h: New file.
 701
 702 2005-09-30  Catherine Moore  <clm@cm00re.com>
 703
 704         * bfin.h: New file.
 705
 706 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 707
 708         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 709         indirect operands.
 710
 711 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 712
 713         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 714         Add FLAG_STRICT to pa10 ftest opcode.
 715
 716 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 717
 718         * hppa.h (pa_opcodes): Remove lha entries.
 719
 720 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 721
 722         * hppa.h (FLAG_STRICT): Revise comment.
 723         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 724         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 725         entries for "fdc".
 726
 727 2005-09-30  Catherine Moore  <clm@cm00re.com>
 728
 729         * bfin.h: New file.
 730
 731 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 732
 733         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 734
 735 2005-09-06  Chao-ying Fu  <fu@mips.com>
 736
 737         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 738         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 739         define.
 740         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 741         (INSN_ASE_MASK): Update to include INSN_MT.
 742         (INSN_MT): New define for MT ASE.
 743
 744 2005-08-25  Chao-ying Fu  <fu@mips.com>
 745
 746         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 747         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 748         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 749         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 750         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 751         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 752         instructions.
 753         (INSN_DSP): New define for DSP ASE.
 754
 755 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 756
 757         * a29k.h: Delete.
 758
 759 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 760
 761         * ppc.h (PPC_OPCODE_E300): Define.
 762
 763 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 764
 765         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 766
 767 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 768
 769         PR gas/336
 770         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 771         and pitlb.
 772
 773 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 774
 775         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 776         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 777         Add movq-s as 64-bit variants of movd-s.
 778
 779 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 780
 781         * hppa.h: Fix punctuation in comment.
 782
 783         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 784         implicit space-register addressing.  Set space-register bits on opcodes
 785         using implicit space-register addressing.  Add various missing pa20
 786         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 787         space-register addressing.  Use "fE" instead of "fe" in various
 788         fstw opcodes.
 789
 790 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 791
 792         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 793
 794 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 795
 796         * i386.h (i386_optab): Support Intel VMX Instructions.
 797
 798 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 799
 800         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 801
 802 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 803
 804         * i386.h (i386_optab): Add new insns.
 805
 806 2005-07-01  Nick Clifton  <nickc@redhat.com>
 807
 808         * sparc.h: Add typedefs to structure declarations.
 809
 810 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 811
 812         PR 1013
 813         * i386.h (i386_optab): Update comments for 64bit addressing on
 814         mov. Allow 64bit addressing for mov and movq.
 815
 816 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 817
 818         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 819         respectively, in various floating-point load and store patterns.
 820
 821 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 822
 823         * hppa.h (FLAG_STRICT): Correct comment.
 824         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 825         PA 2.0 mneumonics when equivalent.  Entries with cache control
 826         completers now require PA 1.1.  Adjust whitespace.
 827
 828 2005-05-19  Anton Blanchard  <anton@samba.org>
 829
 830         * ppc.h (PPC_OPCODE_POWER5): Define.
 831
 832 2005-05-10  Nick Clifton  <nickc@redhat.com>
 833
 834         * Update the address and phone number of the FSF organization in
 835         the GPL notices in the following files:
 836         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 837         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 838         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 839         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 840         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 841         tic54x.h, tic80.h, v850.h, vax.h
 842
 843 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 844
 845         * i386.h (i386_optab): Add ht and hnt.
 846
 847 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 848
 849         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 850         Add xcrypt-ctr.  Provide aliases without hyphens.
 851
 852 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 853
 854         Moved from ../ChangeLog
 855
 856         2005-04-12  Paul Brook  <paul@codesourcery.com>
 857         * m88k.h: Rename psr macros to avoid conflicts.
 858
 859         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 860         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 861         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 862         and ARM_ARCH_V6ZKT2.
 863
 864         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 865         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 866         Remove redundant instruction types.
 867         (struct argument): X_op - new field.
 868         (struct cst4_entry): Remove.
 869         (no_op_insn): Declare.
 870
 871         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 872         * crx.h (enum argtype): Rename types, remove unused types.
 873
 874         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 875         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 876         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 877         (enum operand_type): Rearrange operands, edit comments.
 878         replace us<N> with ui<N> for unsigned immediate.
 879         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 880         displacements (respectively).
 881         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 882         (instruction type): Add NO_TYPE_INS.
 883         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 884         (operand_entry): New field - 'flags'.
 885         (operand flags): New.
 886
 887         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 888         * crx.h (operand_type): Remove redundant types i3, i4,
 889         i5, i8, i12.
 890         Add new unsigned immediate types us3, us4, us5, us16.
 891
 892 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 893
 894         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 895         adjust them accordingly.
 896
 897 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 898
 899         * i386.h (i386_optab): Add rdtscp.
 900
 901 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 904         between memory and segment register. Allow movq for moving between
 905         general-purpose register and segment register.
 906
 907 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 908
 909         PR gas/707
 910         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 911         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 912         fnstsw.
 913
 914 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 915
 916         * m68k.h (m68008, m68ec030, m68882): Remove.
 917         (m68k_mask): New.
 918         (cpu_m68k, cpu_cf): New.
 919         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 920         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 921
 922 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 923
 924         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 925         * cgen.h (enum cgen_parse_operand_type): Add
 926         CGEN_PARSE_OPERAND_SYMBOLIC.
 927
 928 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 929
 930         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 931         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 932         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 933
 934 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 935
 936         * mips.h (struct mips_opcode): Add new pinfo2 member.
 937         (INSN_ALIAS): New define for opcode table entries that are
 938         specific instances of another entry, such as 'move' for an 'or'
 939         with a zero operand.
 940         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 941         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 942
 943 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 944
 945         * mips.h (CPU_RM9000): Define.
 946         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 947
 948 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 949
 950         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 951         to/from test registers are illegal in 64-bit mode. Add missing
 952         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 953         (previously one had to explicitly encode a rex64 prefix). Re-enable
 954         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 955         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 956
 957 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 958
 959         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 960         available only with SSE2. Change the MMX additions introduced by SSE
 961         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 962         instructions by their now designated identifier (since combining i686
 963         and 3DNow! does not really imply 3DNow!A).
 964
 965 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 966
 967         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 968         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 969
 970 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 971             Vineet Sharma      <vineets@noida.hcltech.com>
 972
 973         * maxq.h: New file: Disassembly information for the maxq port.
 974
 975 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 976
 977         * i386.h (i386_optab): Put back "movzb".
 978
 979 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 980
 981         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 982         comments.  Remove member cris_ver_sim.  Add members
 983         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 984         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 985         (struct cris_support_reg, struct cris_cond15): New types.
 986         (cris_conds15): Declare.
 987         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 988         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 989         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 990         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 991         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 992         SIZE_FIELD_UNSIGNED.
 993
 994 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 995
 996         * i386.h (sldx_Suf): Remove.
 997         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 998         (q_FP): Define, implying no REX64.
 999         (x_FP, sl_FP): Imply FloatMF.
1000         (i386_optab): Split reg and mem forms of moving from segment registers
1001         so that the memory forms can ignore the 16-/32-bit operand size
1002         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1003         all non-floating-point instructions. Unite 32- and 64-bit forms of
1004         movsx, movzx, and movd. Adjust floating point operations for the above
1005         changes to the *FP macros. Add DefaultSize to floating point control
1006         insns operating on larger memory ranges. Remove left over comments
1007         hinting at certain insns being Intel-syntax ones where the ones
1008         actually meant are already gone.
1009
1010 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1011
1012         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1013         instruction type.
1014
1015 2004-09-30  Paul Brook  <paul@codesourcery.com>
1016
1017         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1018         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1019
1020 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1021
1022         * avr.h: Add support for
1023         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1024
1025 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1026
1027         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1028
1029 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1030
1031         * msp430.h (msp430_opc): Add new instructions.
1032         (msp430_rcodes): Declare new instructions.
1033         (msp430_hcodes): Likewise..
1034
1035 2004-08-13  Nick Clifton  <nickc@redhat.com>
1036
1037         PR/301
1038         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1039         processors.
1040
1041 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1042
1043         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1044
1045 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1048
1049 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1050
1051         * i386.h: Adjust instruction descriptions to better match the
1052         specification.
1053
1054 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1055
1056         * arm.h: Remove all old content.  Replace with architecture defines
1057         from gas/config/tc-arm.c.
1058
1059 2004-07-09  Andreas Schwab  <schwab@suse.de>
1060
1061         * m68k.h: Fix comment.
1062
1063 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1064
1065         * crx.h: New file.
1066
1067 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1068
1069         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1070
1071 2004-05-24  Peter Barada  <peter@the-baradas.com>
1072
1073         * m68k.h: Add 'size' to m68k_opcode.
1074
1075 2004-05-05  Peter Barada  <peter@the-baradas.com>
1076
1077         * m68k.h: Switch from ColdFire chip name to core variant.
1078
1079 2004-04-22  Peter Barada  <peter@the-baradas.com>
1080
1081         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1082         descriptions for new EMAC cases.
1083         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1084         handle Motorola MAC syntax.
1085         Allow disassembly of ColdFire V4e object files.
1086
1087 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1088
1089         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1090
1091 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1092
1093         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1094
1095 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1096
1097         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1098
1099 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1100
1101         * i386.h (i386_optab): Added xstore/xcrypt insns.
1102
1103 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1104
1105         * h8300.h (32bit ldc/stc): Add relaxing support.
1106
1107 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1108
1109         * h8300.h (BITOP): Pass MEMRELAX flag.
1110
1111 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1112
1113         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1114         except for the H8S.
1115
1116 For older changes see ChangeLog-9103
1117 \f
1118 Local Variables:
1119 mode: change-log
1120 left-margin: 8
1121 fill-column: 74
1122 version-control: never
1123 End: