1 2009-11-02 Paul Brook <paul@codesourcery.com>
3 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
4 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
5 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
6 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
7 FPU_ARCH_NEON_VFP_V4): Define.
9 2009-10-23 Doug Evans <dje@sebabeach.org>
11 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
12 * cgen.h: Update. Improve multi-inclusion macro name.
14 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
16 * ppc.h (PPC_OPCODE_476): Define.
18 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
20 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
22 2009-09-29 DJ Delorie <dj@redhat.com>
26 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
28 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
30 2009-09-21 Ben Elliston <bje@au.ibm.com>
32 * ppc.h (PPC_OPCODE_PPCA2): New.
34 2009-09-05 Martin Thuresson <martin@mtme.org>
36 * ia64.h (struct ia64_operand): Renamed member class to op_class.
38 2009-08-29 Martin Thuresson <martin@mtme.org>
40 * tic30.h (template): Rename type template to
41 insn_template. Updated code to use new name.
42 * tic54x.h (template): Rename type template to
45 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
47 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
49 2009-06-11 Anthony Green <green@moxielogic.com>
51 * moxie.h (MOXIE_F3_PCREL): Define.
52 (moxie_form3_opc_info): Grow.
54 2009-06-06 Anthony Green <green@moxielogic.com>
56 * moxie.h (MOXIE_F1_M): Define.
58 2009-04-15 Anthony Green <green@moxielogic.com>
62 2009-04-06 DJ Delorie <dj@redhat.com>
64 * h8300.h: Add relaxation attributes to MOVA opcodes.
66 2009-03-10 Alan Modra <amodra@bigpond.net.au>
68 * ppc.h (ppc_parse_cpu): Declare.
70 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
72 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
73 and _IMM11 for mbitclr and mbitset.
74 * score-datadep.h: Update dependency information.
76 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
78 * ppc.h (PPC_OPCODE_POWER7): New.
80 2009-02-06 Doug Evans <dje@google.com>
82 * i386.h: Add comment regarding sse* insns and prefixes.
84 2009-02-03 Sandip Matte <sandip@rmicorp.com>
86 * mips.h (INSN_XLR): Define.
87 (INSN_CHIP_MASK): Update.
89 (OPCODE_IS_MEMBER): Update.
90 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
92 2009-01-28 Doug Evans <dje@google.com>
94 * opcode/i386.h: Add multiple inclusion protection.
95 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
96 (EDI_REG_NUM): New macros.
97 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
98 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
99 (REX_PREFIX_P): New macro.
101 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
103 * ppc.h (struct powerpc_opcode): New field "deprecated".
104 (PPC_OPCODE_NOPOWER4): Delete.
106 2008-11-28 Joshua Kinard <kumba@gentoo.org>
108 * mips.h: Define CPU_R14000, CPU_R16000.
109 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
111 2008-11-18 Catherine Moore <clm@codesourcery.com>
113 * arm.h (FPU_NEON_FP16): New.
114 (FPU_ARCH_NEON_FP16): New.
116 2008-11-06 Chao-ying Fu <fu@mips.com>
118 * mips.h: Doucument '1' for 5-bit sync type.
120 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
122 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
125 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
127 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
129 2008-07-30 Michael J. Eager <eager@eagercon.com>
131 * ppc.h (PPC_OPCODE_405): Define.
132 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
134 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
136 * ppc.h (ppc_cpu_t): New typedef.
137 (struct powerpc_opcode <flags>): Use it.
138 (struct powerpc_operand <insert, extract>): Likewise.
139 (struct powerpc_macro <flags>): Likewise.
141 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
143 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
144 Update comment before MIPS16 field descriptors to mention MIPS16.
145 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
147 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
148 New bit masks and shift counts for cins and exts.
150 * mips.h: Document new field descriptors +Q.
151 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
153 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
155 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
156 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
158 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
160 * ppc.h: (PPC_OPCODE_E500MC): New.
162 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
164 * i386.h (MAX_OPERANDS): Set to 5.
165 (MAX_MNEM_SIZE): Changed to 20.
167 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
169 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
171 2008-03-09 Paul Brook <paul@codesourcery.com>
173 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
175 2008-03-04 Paul Brook <paul@codesourcery.com>
177 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
178 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
179 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
181 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
182 Nick Clifton <nickc@redhat.com>
185 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
186 with a 32-bit displacement but without the top bit of the 4th byte
189 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
191 * cr16.h (cr16_num_optab): Declared.
193 2008-02-14 Hakan Ardo <hakan@debian.org>
196 * avr.h (AVR_ISA_2xxe): Define.
198 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
200 * mips.h: Update copyright.
201 (INSN_CHIP_MASK): New macro.
202 (INSN_OCTEON): New macro.
203 (CPU_OCTEON): New macro.
204 (OPCODE_IS_MEMBER): Handle Octeon instructions.
206 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
208 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
210 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
212 * avr.h (AVR_ISA_USB162): Add new opcode set.
213 (AVR_ISA_AVR3): Likewise.
215 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
217 * mips.h (INSN_LOONGSON_2E): New.
218 (INSN_LOONGSON_2F): New.
219 (CPU_LOONGSON_2E): New.
220 (CPU_LOONGSON_2F): New.
221 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
223 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
225 * mips.h (INSN_ISA*): Redefine certain values as an
226 enumeration. Update comments.
227 (mips_isa_table): New.
228 (ISA_MIPS*): Redefine to match enumeration.
229 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
232 2007-08-08 Ben Elliston <bje@au.ibm.com>
234 * ppc.h (PPC_OPCODE_PPCPS): New.
236 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
238 * m68k.h: Document j K & E.
240 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
242 * cr16.h: New file for CR16 target.
244 2007-05-02 Alan Modra <amodra@bigpond.net.au>
246 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
248 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
250 * m68k.h (mcfisa_c): New.
251 (mcfusp, mcf_mask): Adjust.
253 2007-04-20 Alan Modra <amodra@bigpond.net.au>
255 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
256 (num_powerpc_operands): Declare.
257 (PPC_OPERAND_SIGNED et al): Redefine as hex.
258 (PPC_OPERAND_PLUS1): Define.
260 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
262 * i386.h (REX_MODE64): Renamed to ...
264 (REX_EXTX): Renamed to ...
266 (REX_EXTY): Renamed to ...
268 (REX_EXTZ): Renamed to ...
271 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
273 * i386.h: Add entries from config/tc-i386.h and move tables
274 to opcodes/i386-opc.h.
276 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
278 * i386.h (FloatDR): Removed.
279 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
281 2007-03-01 Alan Modra <amodra@bigpond.net.au>
283 * spu-insns.h: Add soma double-float insns.
285 2007-02-20 Thiemo Seufer <ths@mips.com>
286 Chao-Ying Fu <fu@mips.com>
288 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
289 (INSN_DSPR2): Add flag for DSP R2 instructions.
290 (M_BALIGN): New macro.
292 2007-02-14 Alan Modra <amodra@bigpond.net.au>
294 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
295 and Seg3ShortFrom with Shortform.
297 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
300 * i386.h (i386_optab): Put the real "test" before the pseudo
303 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
305 * m68k.h (m68010up): OR fido_a.
307 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
309 * m68k.h (fido_a): New.
311 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
313 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
314 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
317 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
319 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
321 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
323 * score-inst.h (enum score_insn_type): Add Insn_internal.
325 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
326 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
327 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
328 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
329 Alan Modra <amodra@bigpond.net.au>
331 * spu-insns.h: New file.
334 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
336 * ppc.h (PPC_OPCODE_CELL): Define.
338 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
340 * i386.h : Modify opcode to support for the change in POPCNT opcode
341 in amdfam10 architecture.
343 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
345 * i386.h: Replace CpuMNI with CpuSSSE3.
347 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
348 Joseph Myers <joseph@codesourcery.com>
349 Ian Lance Taylor <ian@wasabisystems.com>
350 Ben Elliston <bje@wasabisystems.com>
352 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
354 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
356 * score-datadep.h: New file.
357 * score-inst.h: New file.
359 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
361 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
362 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
365 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
366 Michael Meissner <michael.meissner@amd.com>
368 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
370 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
372 * i386.h (i386_optab): Add "nop" with memory reference.
374 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
376 * i386.h (i386_optab): Update comment for 64bit NOP.
378 2006-06-06 Ben Elliston <bje@au.ibm.com>
379 Anton Blanchard <anton@samba.org>
381 * ppc.h (PPC_OPCODE_POWER6): Define.
384 2006-06-05 Thiemo Seufer <ths@mips.com>
386 * mips.h: Improve description of MT flags.
388 2006-05-25 Richard Sandiford <richard@codesourcery.com>
390 * m68k.h (mcf_mask): Define.
392 2006-05-05 Thiemo Seufer <ths@mips.com>
393 David Ung <davidu@mips.com>
395 * mips.h (enum): Add macro M_CACHE_AB.
397 2006-05-04 Thiemo Seufer <ths@mips.com>
398 Nigel Stephens <nigel@mips.com>
399 David Ung <davidu@mips.com>
401 * mips.h: Add INSN_SMARTMIPS define.
403 2006-04-30 Thiemo Seufer <ths@mips.com>
404 David Ung <davidu@mips.com>
406 * mips.h: Defines udi bits and masks. Add description of
407 characters which may appear in the args field of udi
410 2006-04-26 Thiemo Seufer <ths@networkno.de>
412 * mips.h: Improve comments describing the bitfield instruction
415 2006-04-26 Julian Brown <julian@codesourcery.com>
417 * arm.h (FPU_VFP_EXT_V3): Define constant.
418 (FPU_NEON_EXT_V1): Likewise.
419 (FPU_VFP_HARD): Update.
420 (FPU_VFP_V3): Define macro.
421 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
423 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
425 * avr.h (AVR_ISA_PWMx): New.
427 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
429 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
430 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
431 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
432 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
433 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
435 2006-03-10 Paul Brook <paul@codesourcery.com>
437 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
439 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
441 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
442 first. Correct mask of bb "B" opcode.
444 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
446 * i386.h (i386_optab): Support Intel Merom New Instructions.
448 2006-02-24 Paul Brook <paul@codesourcery.com>
450 * arm.h: Add V7 feature bits.
452 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
454 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
456 2006-01-31 Paul Brook <paul@codesourcery.com>
457 Richard Earnshaw <rearnsha@arm.com>
459 * arm.h: Use ARM_CPU_FEATURE.
460 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
461 (arm_feature_set): Change to a structure.
462 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
463 ARM_FEATURE): New macros.
465 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
467 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
468 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
469 (ADD_PC_INCR_OPCODE): Don't define.
471 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
474 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
476 2005-11-14 David Ung <davidu@mips.com>
478 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
479 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
480 save/restore encoding of the args field.
482 2005-10-28 Dave Brolley <brolley@redhat.com>
484 Contribute the following changes:
485 2005-02-16 Dave Brolley <brolley@redhat.com>
487 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
488 cgen_isa_mask_* to cgen_bitset_*.
491 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
493 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
494 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
495 (CGEN_CPU_TABLE): Make isas a ponter.
497 2003-09-29 Dave Brolley <brolley@redhat.com>
499 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
500 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
501 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
503 2002-12-13 Dave Brolley <brolley@redhat.com>
505 * cgen.h (symcat.h): #include it.
506 (cgen-bitset.h): #include it.
507 (CGEN_ATTR_VALUE_TYPE): Now a union.
508 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
509 (CGEN_ATTR_ENTRY): 'value' now unsigned.
510 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
511 * cgen-bitset.h: New file.
513 2005-09-30 Catherine Moore <clm@cm00re.com>
517 2005-10-24 Jan Beulich <jbeulich@novell.com>
519 * ia64.h (enum ia64_opnd): Move memory operand out of set of
522 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
524 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
525 Add FLAG_STRICT to pa10 ftest opcode.
527 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
529 * hppa.h (pa_opcodes): Remove lha entries.
531 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
533 * hppa.h (FLAG_STRICT): Revise comment.
534 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
535 before corresponding pa11 opcodes. Add strict pa10 register-immediate
538 2005-09-30 Catherine Moore <clm@cm00re.com>
542 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
544 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
546 2005-09-06 Chao-ying Fu <fu@mips.com>
548 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
549 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
551 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
552 (INSN_ASE_MASK): Update to include INSN_MT.
553 (INSN_MT): New define for MT ASE.
555 2005-08-25 Chao-ying Fu <fu@mips.com>
557 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
558 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
559 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
560 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
561 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
562 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
564 (INSN_DSP): New define for DSP ASE.
566 2005-08-18 Alan Modra <amodra@bigpond.net.au>
570 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
572 * ppc.h (PPC_OPCODE_E300): Define.
574 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
576 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
578 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
581 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
584 2005-07-27 Jan Beulich <jbeulich@novell.com>
586 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
587 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
588 Add movq-s as 64-bit variants of movd-s.
590 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
592 * hppa.h: Fix punctuation in comment.
594 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
595 implicit space-register addressing. Set space-register bits on opcodes
596 using implicit space-register addressing. Add various missing pa20
597 long-immediate opcodes. Remove various opcodes using implicit 3-bit
598 space-register addressing. Use "fE" instead of "fe" in various
601 2005-07-18 Jan Beulich <jbeulich@novell.com>
603 * i386.h (i386_optab): Operands of aam and aad are unsigned.
605 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
607 * i386.h (i386_optab): Support Intel VMX Instructions.
609 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
611 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
613 2005-07-05 Jan Beulich <jbeulich@novell.com>
615 * i386.h (i386_optab): Add new insns.
617 2005-07-01 Nick Clifton <nickc@redhat.com>
619 * sparc.h: Add typedefs to structure declarations.
621 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
624 * i386.h (i386_optab): Update comments for 64bit addressing on
625 mov. Allow 64bit addressing for mov and movq.
627 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
629 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
630 respectively, in various floating-point load and store patterns.
632 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
634 * hppa.h (FLAG_STRICT): Correct comment.
635 (pa_opcodes): Update load and store entries to allow both PA 1.X and
636 PA 2.0 mneumonics when equivalent. Entries with cache control
637 completers now require PA 1.1. Adjust whitespace.
639 2005-05-19 Anton Blanchard <anton@samba.org>
641 * ppc.h (PPC_OPCODE_POWER5): Define.
643 2005-05-10 Nick Clifton <nickc@redhat.com>
645 * Update the address and phone number of the FSF organization in
646 the GPL notices in the following files:
647 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
648 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
649 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
650 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
651 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
652 tic54x.h, tic80.h, v850.h, vax.h
654 2005-05-09 Jan Beulich <jbeulich@novell.com>
656 * i386.h (i386_optab): Add ht and hnt.
658 2005-04-18 Mark Kettenis <kettenis@gnu.org>
660 * i386.h: Insert hyphens into selected VIA PadLock extensions.
661 Add xcrypt-ctr. Provide aliases without hyphens.
663 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
665 Moved from ../ChangeLog
667 2005-04-12 Paul Brook <paul@codesourcery.com>
668 * m88k.h: Rename psr macros to avoid conflicts.
670 2005-03-12 Zack Weinberg <zack@codesourcery.com>
671 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
672 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
675 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
676 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
677 Remove redundant instruction types.
678 (struct argument): X_op - new field.
679 (struct cst4_entry): Remove.
680 (no_op_insn): Declare.
682 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
683 * crx.h (enum argtype): Rename types, remove unused types.
685 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
686 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
687 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
688 (enum operand_type): Rearrange operands, edit comments.
689 replace us<N> with ui<N> for unsigned immediate.
690 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
691 displacements (respectively).
692 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
693 (instruction type): Add NO_TYPE_INS.
694 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
695 (operand_entry): New field - 'flags'.
696 (operand flags): New.
698 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
699 * crx.h (operand_type): Remove redundant types i3, i4,
701 Add new unsigned immediate types us3, us4, us5, us16.
703 2005-04-12 Mark Kettenis <kettenis@gnu.org>
705 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
706 adjust them accordingly.
708 2005-04-01 Jan Beulich <jbeulich@novell.com>
710 * i386.h (i386_optab): Add rdtscp.
712 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
714 * i386.h (i386_optab): Don't allow the `l' suffix for moving
715 between memory and segment register. Allow movq for moving between
716 general-purpose register and segment register.
718 2005-02-09 Jan Beulich <jbeulich@novell.com>
721 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
722 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
725 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
727 * m68k.h (m68008, m68ec030, m68882): Remove.
729 (cpu_m68k, cpu_cf): New.
730 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
731 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
733 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
735 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
736 * cgen.h (enum cgen_parse_operand_type): Add
737 CGEN_PARSE_OPERAND_SYMBOLIC.
739 2005-01-21 Fred Fish <fnf@specifixinc.com>
741 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
742 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
743 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
745 2005-01-19 Fred Fish <fnf@specifixinc.com>
747 * mips.h (struct mips_opcode): Add new pinfo2 member.
748 (INSN_ALIAS): New define for opcode table entries that are
749 specific instances of another entry, such as 'move' for an 'or'
751 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
752 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
754 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
756 * mips.h (CPU_RM9000): Define.
757 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
759 2004-11-25 Jan Beulich <jbeulich@novell.com>
761 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
762 to/from test registers are illegal in 64-bit mode. Add missing
763 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
764 (previously one had to explicitly encode a rex64 prefix). Re-enable
765 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
766 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
768 2004-11-23 Jan Beulich <jbeulich@novell.com>
770 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
771 available only with SSE2. Change the MMX additions introduced by SSE
772 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
773 instructions by their now designated identifier (since combining i686
774 and 3DNow! does not really imply 3DNow!A).
776 2004-11-19 Alan Modra <amodra@bigpond.net.au>
778 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
779 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
781 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
782 Vineet Sharma <vineets@noida.hcltech.com>
784 * maxq.h: New file: Disassembly information for the maxq port.
786 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
788 * i386.h (i386_optab): Put back "movzb".
790 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
792 * cris.h (enum cris_insn_version_usage): Tweak formatting and
793 comments. Remove member cris_ver_sim. Add members
794 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
795 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
796 (struct cris_support_reg, struct cris_cond15): New types.
797 (cris_conds15): Declare.
798 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
799 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
800 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
801 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
802 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
805 2004-11-04 Jan Beulich <jbeulich@novell.com>
807 * i386.h (sldx_Suf): Remove.
808 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
809 (q_FP): Define, implying no REX64.
810 (x_FP, sl_FP): Imply FloatMF.
811 (i386_optab): Split reg and mem forms of moving from segment registers
812 so that the memory forms can ignore the 16-/32-bit operand size
813 distinction. Adjust a few others for Intel mode. Remove *FP uses from
814 all non-floating-point instructions. Unite 32- and 64-bit forms of
815 movsx, movzx, and movd. Adjust floating point operations for the above
816 changes to the *FP macros. Add DefaultSize to floating point control
817 insns operating on larger memory ranges. Remove left over comments
818 hinting at certain insns being Intel-syntax ones where the ones
819 actually meant are already gone.
821 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
823 * crx.h: Add COPS_REG_INS - Coprocessor Special register
826 2004-09-30 Paul Brook <paul@codesourcery.com>
828 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
829 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
831 2004-09-11 Theodore A. Roth <troth@openavr.org>
833 * avr.h: Add support for
834 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
836 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
838 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
840 2004-08-24 Dmitry Diky <diwil@spec.ru>
842 * msp430.h (msp430_opc): Add new instructions.
843 (msp430_rcodes): Declare new instructions.
844 (msp430_hcodes): Likewise..
846 2004-08-13 Nick Clifton <nickc@redhat.com>
849 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
852 2004-08-30 Michal Ludvig <mludvig@suse.cz>
854 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
856 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
858 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
860 2004-07-21 Jan Beulich <jbeulich@novell.com>
862 * i386.h: Adjust instruction descriptions to better match the
865 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
867 * arm.h: Remove all old content. Replace with architecture defines
868 from gas/config/tc-arm.c.
870 2004-07-09 Andreas Schwab <schwab@suse.de>
872 * m68k.h: Fix comment.
874 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
878 2004-06-24 Alan Modra <amodra@bigpond.net.au>
880 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
882 2004-05-24 Peter Barada <peter@the-baradas.com>
884 * m68k.h: Add 'size' to m68k_opcode.
886 2004-05-05 Peter Barada <peter@the-baradas.com>
888 * m68k.h: Switch from ColdFire chip name to core variant.
890 2004-04-22 Peter Barada <peter@the-baradas.com>
892 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
893 descriptions for new EMAC cases.
894 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
895 handle Motorola MAC syntax.
896 Allow disassembly of ColdFire V4e object files.
898 2004-03-16 Alan Modra <amodra@bigpond.net.au>
900 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
902 2004-03-12 Jakub Jelinek <jakub@redhat.com>
904 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
906 2004-03-12 Michal Ludvig <mludvig@suse.cz>
908 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
910 2004-03-12 Michal Ludvig <mludvig@suse.cz>
912 * i386.h (i386_optab): Added xstore/xcrypt insns.
914 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
916 * h8300.h (32bit ldc/stc): Add relaxing support.
918 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
920 * h8300.h (BITOP): Pass MEMRELAX flag.
922 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
924 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
927 For older changes see ChangeLog-9103
933 version-control: never