1 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Remove references to "+I" and imm2_expr.
5 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips.h (M_DEXT, M_DINS): Delete.
9 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
11 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
12 (mips_optional_operand_p): New function.
14 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
15 Richard Sandiford <rdsandiford@googlemail.com>
17 * mips.h: Document new VU0 operand characters.
18 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
19 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
20 (OP_REG_R5900_ACC): New mips_reg_operand_types.
21 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
22 (mips_vu0_channel_mask): Declare.
24 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
26 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
27 (mips_int_operand_min, mips_int_operand_max): New functions.
28 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
30 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
32 * mips.h (mips_decode_reg_operand): New function.
33 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
34 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
35 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
37 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
38 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
39 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
40 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
41 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
42 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
43 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
44 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
45 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
46 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
47 macros to cover the gaps.
48 (INSN2_MOD_SP): Replace with...
49 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
50 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
51 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
52 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
53 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
56 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
58 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
59 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
60 (MIPS16_INSN_COND_BRANCH): Delete.
62 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
63 Kirill Yukhin <kirill.yukhin@intel.com>
64 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
66 * i386.h (BND_PREFIX_OPCODE): New.
68 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
70 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
72 (decode_mips16_operand): Declare.
74 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
76 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
77 (mips_operand, mips_int_operand, mips_mapped_int_operand)
78 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
79 (mips_pcrel_operand): New structures.
80 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
81 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
82 (decode_mips_operand, decode_micromips_operand): Declare.
84 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
86 * mips.h: Document MIPS16 "I" opcode.
88 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
90 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
91 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
92 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
93 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
94 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
95 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
96 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
97 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
98 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
99 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
100 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
101 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
102 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
104 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
105 (M_USD_AB): ...these.
107 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
109 * mips.h: Remove documentation of "[" and "]". Update documentation
110 of "k" and the MDMX formats.
112 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
114 * mips.h: Update documentation of "+s" and "+S".
116 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
118 * mips.h: Document "+i".
120 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
122 * mips.h: Remove "mi" documentation. Update "mh" documentation.
123 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
125 (INSN2_WRITE_GPR_MHI): Rename to...
126 (INSN2_WRITE_GPR_MH): ...this.
128 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
130 * mips.h: Remove documentation of "+D" and "+T".
132 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
134 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
135 Use "source" rather than "destination" for microMIPS "G".
137 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
139 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
142 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
144 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
146 2013-06-17 Catherine Moore <clm@codesourcery.com>
147 Maciej W. Rozycki <macro@codesourcery.com>
148 Chao-Ying Fu <fu@mips.com>
150 * mips.h (OP_SH_EVAOFFSET): Define.
151 (OP_MASK_EVAOFFSET): Define.
152 (INSN_ASE_MASK): Delete.
154 (M_CACHEE_AB, M_CACHEE_OB): New.
155 (M_LBE_OB, M_LBE_AB): New.
156 (M_LBUE_OB, M_LBUE_AB): New.
157 (M_LHE_OB, M_LHE_AB): New.
158 (M_LHUE_OB, M_LHUE_AB): New.
159 (M_LLE_AB, M_LLE_OB): New.
160 (M_LWE_OB, M_LWE_AB): New.
161 (M_LWLE_AB, M_LWLE_OB): New.
162 (M_LWRE_AB, M_LWRE_OB): New.
163 (M_PREFE_AB, M_PREFE_OB): New.
164 (M_SCE_AB, M_SCE_OB): New.
165 (M_SBE_OB, M_SBE_AB): New.
166 (M_SHE_OB, M_SHE_AB): New.
167 (M_SWE_OB, M_SWE_AB): New.
168 (M_SWLE_AB, M_SWLE_OB): New.
169 (M_SWRE_AB, M_SWRE_OB): New.
170 (MICROMIPSOP_SH_EVAOFFSET): Define.
171 (MICROMIPSOP_MASK_EVAOFFSET): Define.
173 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
175 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
177 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
179 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
181 2013-05-09 Andrew Pinski <apinski@cavium.com>
183 * mips.h (OP_MASK_CODE10): Correct definition.
184 (OP_SH_CODE10): Likewise.
185 Add a comment that "+J" is used now for OP_*CODE10.
186 (INSN_ASE_MASK): Update.
187 (INSN_VIRT): New macro.
188 (INSN_VIRT64): New macro
190 2013-05-02 Nick Clifton <nickc@redhat.com>
192 * msp430.h: Add patterns for MSP430X instructions.
194 2013-04-06 David S. Miller <davem@davemloft.net>
196 * sparc.h (F_PREFERRED): Define.
197 (F_PREF_ALIAS): Define.
199 2013-04-03 Nick Clifton <nickc@redhat.com>
201 * v850.h (V850_INVERSE_PCREL): Define.
203 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
206 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
208 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
211 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
213 * tic6xc-opcode-table.h: Add 16-bit insns.
214 * tic6x.h: Add support for 16-bit insns.
216 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
218 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
219 and mov.b/w/l Rs,@(d:32,ERd).
221 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
224 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
225 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
226 tic6x_operand_xregpair operand coding type.
227 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
228 opcode field, usu ORXREGD1324 for the src2 operand and remove the
231 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
234 * tic6x.h (enum tic6x_coding_method): Add
235 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
236 separately the msb and lsb of a register pair. This is needed to
237 encode the opcodes in the same way as TI assembler does.
238 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
239 and rsqrdp opcodes to use the new field coding types.
241 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
243 * arm.h (CRC_EXT_ARMV8): New constant.
244 (ARCH_CRC_ARMV8): New macro.
246 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
248 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
250 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
251 Andrew Jenner <andrew@codesourcery.com>
253 Based on patches from Altera Corporation.
257 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
259 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
261 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
264 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
266 2013-01-24 Nick Clifton <nickc@redhat.com>
268 * v850.h: Add e3v5 support.
270 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
272 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
274 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
276 * ppc.h (PPC_OPCODE_POWER8): New define.
277 (PPC_OPCODE_HTM): Likewise.
279 2013-01-10 Will Newton <will.newton@imgtec.com>
283 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
285 * cr16.h (make_instruction): Rename to cr16_make_instruction.
286 (match_opcode): Rename to cr16_match_opcode.
288 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
290 * mips.h: Add support for r5900 instructions including lq and sq.
292 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
294 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
295 (make_instruction,match_opcode): Added function prototypes.
296 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
298 2012-11-23 Alan Modra <amodra@gmail.com>
300 * ppc.h (ppc_parse_cpu): Update prototype.
302 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
304 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
305 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
307 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
309 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
311 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
313 * ia64.h (ia64_opnd): Add new operand types.
315 2012-08-21 David S. Miller <davem@davemloft.net>
317 * sparc.h (F3F4): New macro.
319 2012-08-13 Ian Bolton <ian.bolton@arm.com>
320 Laurent Desnogues <laurent.desnogues@arm.com>
321 Jim MacArthur <jim.macarthur@arm.com>
322 Marcus Shawcroft <marcus.shawcroft@arm.com>
323 Nigel Stephens <nigel.stephens@arm.com>
324 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
325 Richard Earnshaw <rearnsha@arm.com>
326 Sofiane Naci <sofiane.naci@arm.com>
327 Tejas Belagod <tejas.belagod@arm.com>
328 Yufeng Zhang <yufeng.zhang@arm.com>
330 * aarch64.h: New file.
332 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
333 Maciej W. Rozycki <macro@codesourcery.com>
335 * mips.h (mips_opcode): Add the exclusions field.
336 (OPCODE_IS_MEMBER): Remove macro.
337 (cpu_is_member): New inline function.
338 (opcode_is_member): Likewise.
340 2012-07-31 Chao-Ying Fu <fu@mips.com>
341 Catherine Moore <clm@codesourcery.com>
342 Maciej W. Rozycki <macro@codesourcery.com>
344 * mips.h: Document microMIPS DSP ASE usage.
345 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
346 microMIPS DSP ASE support.
347 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
348 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
349 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
350 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
351 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
352 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
353 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
355 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
357 * mips.h: Fix a typo in description.
359 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
361 * avr.h: (AVR_ISA_XCH): New define.
362 (AVR_ISA_XMEGA): Use it.
363 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
365 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
367 * m68hc11.h: Add XGate definitions.
368 (struct m68hc11_opcode): Add xg_mask field.
370 2012-05-14 Catherine Moore <clm@codesourcery.com>
371 Maciej W. Rozycki <macro@codesourcery.com>
372 Rhonda Wittels <rhonda@codesourcery.com>
374 * ppc.h (PPC_OPCODE_VLE): New definition.
375 (PPC_OP_SA): New macro.
376 (PPC_OP_SE_VLE): New macro.
377 (PPC_OP): Use a variable shift amount.
378 (powerpc_operand): Update comments.
379 (PPC_OPSHIFT_INV): New macro.
380 (PPC_OPERAND_CR): Replace with...
381 (PPC_OPERAND_CR_BIT): ...this and
382 (PPC_OPERAND_CR_REG): ...this.
385 2012-05-03 Sean Keys <skeys@ipdatasys.com>
387 * xgate.h: Header file for XGATE assembler.
389 2012-04-27 David S. Miller <davem@davemloft.net>
391 * sparc.h: Document new arg code' )' for crypto RS3
394 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
395 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
396 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
397 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
398 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
399 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
400 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
401 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
402 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
403 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
404 HWCAP_CBCOND, HWCAP_CRC32): New defines.
406 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
408 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
410 2012-02-27 Alan Modra <amodra@gmail.com>
412 * crx.h (cst4_map): Update declaration.
414 2012-02-25 Walter Lee <walt@tilera.com>
416 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
418 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
419 TILEPRO_OPC_LW_TLS_SN.
421 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
423 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
424 (XRELEASE_PREFIX_OPCODE): Likewise.
426 2011-12-08 Andrew Pinski <apinski@cavium.com>
427 Adam Nemet <anemet@caviumnetworks.com>
429 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
430 (INSN_OCTEON2): New macro.
431 (CPU_OCTEON2): New macro.
432 (OPCODE_IS_MEMBER): Add Octeon2.
434 2011-11-29 Andrew Pinski <apinski@cavium.com>
436 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
437 (INSN_OCTEONP): New macro.
438 (CPU_OCTEONP): New macro.
439 (OPCODE_IS_MEMBER): Add Octeon+.
440 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
442 2011-11-01 DJ Delorie <dj@redhat.com>
446 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
448 * mips.h: Fix a typo in description.
450 2011-09-21 David S. Miller <davem@davemloft.net>
452 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
453 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
454 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
455 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
457 2011-08-09 Chao-ying Fu <fu@mips.com>
458 Maciej W. Rozycki <macro@codesourcery.com>
460 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
461 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
462 (INSN_ASE_MASK): Add the MCU bit.
463 (INSN_MCU): New macro.
464 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
465 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
467 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
469 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
470 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
471 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
472 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
473 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
474 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
475 (INSN2_READ_GPR_MMN): Likewise.
476 (INSN2_READ_FPR_D): Change the bit used.
477 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
478 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
479 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
480 (INSN2_COND_BRANCH): Likewise.
481 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
482 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
483 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
484 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
485 (INSN2_MOD_GPR_MN): Likewise.
487 2011-08-05 David S. Miller <davem@davemloft.net>
489 * sparc.h: Document new format codes '4', '5', and '('.
490 (OPF_LOW4, RS3): New macros.
492 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
494 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
495 order of flags documented.
497 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
499 * mips.h: Clarify the description of microMIPS instruction
501 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
503 2011-07-24 Chao-ying Fu <fu@mips.com>
504 Maciej W. Rozycki <macro@codesourcery.com>
506 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
507 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
508 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
509 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
510 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
511 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
512 (OP_MASK_RS3, OP_SH_RS3): Likewise.
513 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
514 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
515 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
516 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
517 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
518 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
519 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
520 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
521 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
522 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
523 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
524 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
525 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
526 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
527 (INSN_WRITE_GPR_S): New macro.
528 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
529 (INSN2_READ_FPR_D): Likewise.
530 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
531 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
532 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
533 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
534 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
535 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
536 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
537 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
538 (CPU_MICROMIPS): New macro.
539 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
540 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
541 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
542 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
543 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
544 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
545 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
546 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
547 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
548 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
549 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
550 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
551 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
552 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
553 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
554 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
555 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
556 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
557 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
558 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
559 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
560 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
561 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
562 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
563 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
564 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
565 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
566 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
567 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
568 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
569 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
570 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
571 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
572 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
573 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
574 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
575 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
576 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
577 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
578 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
579 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
580 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
581 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
582 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
583 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
584 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
585 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
586 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
587 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
588 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
589 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
590 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
591 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
592 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
593 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
594 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
595 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
596 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
597 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
598 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
599 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
600 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
601 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
602 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
603 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
604 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
605 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
606 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
607 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
608 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
609 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
610 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
611 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
612 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
613 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
614 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
615 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
616 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
617 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
618 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
619 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
620 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
621 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
622 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
623 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
624 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
625 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
626 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
627 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
628 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
629 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
630 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
631 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
632 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
633 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
634 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
635 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
636 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
637 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
638 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
639 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
640 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
641 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
642 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
643 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
644 (micromips_opcodes): New declaration.
645 (bfd_micromips_num_opcodes): Likewise.
647 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
649 * mips.h (INSN_TRAP): Rename to...
650 (INSN_NO_DELAY_SLOT): ... this.
651 (INSN_SYNC): Remove macro.
653 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
655 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
656 a duplicate of AVR_ISA_SPM.
658 2011-07-01 Nick Clifton <nickc@redhat.com>
660 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
662 2011-06-18 Robin Getz <robin.getz@analog.com>
664 * bfin.h (is_macmod_signed): New func
666 2011-06-18 Mike Frysinger <vapier@gentoo.org>
668 * bfin.h (is_macmod_pmove): Add missing space before func args.
669 (is_macmod_hmove): Likewise.
671 2011-06-13 Walter Lee <walt@tilera.com>
673 * tilegx.h: New file.
674 * tilepro.h: New file.
676 2011-05-31 Paul Brook <paul@codesourcery.com>
678 * arm.h (ARM_ARCH_V7R_IDIV): Define.
680 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
682 * s390.h: Replace S390_OPERAND_REG_EVEN with
683 S390_OPERAND_REG_PAIR.
685 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
687 * s390.h: Add S390_OPCODE_REG_EVEN flag.
689 2011-04-18 Julian Brown <julian@codesourcery.com>
691 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
693 2011-04-11 Dan McDonald <dan@wellkeeper.com>
696 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
698 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
700 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
701 New instruction set flags.
702 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
704 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
706 * mips.h (M_PREF_AB): New enum value.
708 2011-02-12 Mike Frysinger <vapier@gentoo.org>
710 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
712 (is_macmod_pmove, is_macmod_hmove): New functions.
714 2011-02-11 Mike Frysinger <vapier@gentoo.org>
716 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
718 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
720 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
721 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
723 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
726 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
729 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
732 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
734 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
736 * mips.h: Update commentary after last commit.
738 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
740 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
741 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
742 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
744 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
746 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
748 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
750 * mips.h: Fix previous commit.
752 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
754 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
755 (INSN_LOONGSON_3A): Clear bit 31.
757 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
760 * arm.h (ARM_AEXT_V6M_ONLY): New define.
761 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
762 (ARM_ARCH_V6M_ONLY): New define.
764 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
766 * mips.h (INSN_LOONGSON_3A): Defined.
767 (CPU_LOONGSON_3A): Defined.
768 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
770 2010-10-09 Matt Rice <ratmice@gmail.com>
772 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
773 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
775 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
777 * arm.h (ARM_EXT_VIRT): New define.
778 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
779 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
782 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
784 * arm.h (ARM_AEXT_ADIV): New define.
785 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
787 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
789 * arm.h (ARM_EXT_OS): New define.
790 (ARM_AEXT_V6SM): Likewise.
791 (ARM_ARCH_V6SM): Likewise.
793 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
795 * arm.h (ARM_EXT_MP): Add.
796 (ARM_ARCH_V7A_MP): Likewise.
798 2010-09-22 Mike Frysinger <vapier@gentoo.org>
800 * bfin.h: Declare pseudoChr structs/defines.
802 2010-09-21 Mike Frysinger <vapier@gentoo.org>
804 * bfin.h: Strip trailing whitespace.
806 2010-07-29 DJ Delorie <dj@redhat.com>
808 * rx.h (RX_Operand_Type): Add TwoReg.
809 (RX_Opcode_ID): Remove ediv and ediv2.
811 2010-07-27 DJ Delorie <dj@redhat.com>
813 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
815 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
816 Ina Pandit <ina.pandit@kpitcummins.com>
818 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
819 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
820 PROCESSOR_V850E2_ALL.
821 Remove PROCESSOR_V850EA support.
822 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
823 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
824 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
825 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
826 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
827 V850_OPERAND_PERCENT.
828 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
830 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
833 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
835 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
836 (MIPS16_INSN_BRANCH): Rename to...
837 (MIPS16_INSN_COND_BRANCH): ... this.
839 2010-07-03 Alan Modra <amodra@gmail.com>
841 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
842 Renumber other PPC_OPCODE defines.
844 2010-07-03 Alan Modra <amodra@gmail.com>
846 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
848 2010-06-29 Alan Modra <amodra@gmail.com>
850 * maxq.h: Delete file.
852 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
854 * ppc.h (PPC_OPCODE_E500): Define.
856 2010-05-26 Catherine Moore <clm@codesourcery.com>
858 * opcode/mips.h (INSN_MIPS16): Remove.
860 2010-04-21 Joseph Myers <joseph@codesourcery.com>
862 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
864 2010-04-15 Nick Clifton <nickc@redhat.com>
866 * alpha.h: Update copyright notice to use GPLv3.
872 * convex.h: Likewise.
886 * m68hc11.h: Likewise.
892 * mn10200.h: Likewise.
893 * mn10300.h: Likewise.
894 * msp430.h: Likewise.
905 * score-datadep.h: Likewise.
906 * score-inst.h: Likewise.
908 * spu-insns.h: Likewise.
912 * tic54x.h: Likewise.
917 2010-03-25 Joseph Myers <joseph@codesourcery.com>
919 * tic6x-control-registers.h, tic6x-insn-formats.h,
920 tic6x-opcode-table.h, tic6x.h: New.
922 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
924 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
926 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
928 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
930 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
932 * ia64.h (ia64_find_opcode): Remove argument name.
933 (ia64_find_next_opcode): Likewise.
934 (ia64_dis_opcode): Likewise.
935 (ia64_free_opcode): Likewise.
936 (ia64_find_dependency): Likewise.
938 2009-11-22 Doug Evans <dje@sebabeach.org>
940 * cgen.h: Include bfd_stdint.h.
941 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
943 2009-11-18 Paul Brook <paul@codesourcery.com>
945 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
947 2009-11-17 Paul Brook <paul@codesourcery.com>
948 Daniel Jacobowitz <dan@codesourcery.com>
950 * arm.h (ARM_EXT_V6_DSP): Define.
951 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
952 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
954 2009-11-04 DJ Delorie <dj@redhat.com>
956 * rx.h (rx_decode_opcode) (mvtipl): Add.
957 (mvtcp, mvfcp, opecp): Remove.
959 2009-11-02 Paul Brook <paul@codesourcery.com>
961 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
962 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
963 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
964 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
965 FPU_ARCH_NEON_VFP_V4): Define.
967 2009-10-23 Doug Evans <dje@sebabeach.org>
969 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
970 * cgen.h: Update. Improve multi-inclusion macro name.
972 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
974 * ppc.h (PPC_OPCODE_476): Define.
976 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
978 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
980 2009-09-29 DJ Delorie <dj@redhat.com>
984 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
986 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
988 2009-09-21 Ben Elliston <bje@au.ibm.com>
990 * ppc.h (PPC_OPCODE_PPCA2): New.
992 2009-09-05 Martin Thuresson <martin@mtme.org>
994 * ia64.h (struct ia64_operand): Renamed member class to op_class.
996 2009-08-29 Martin Thuresson <martin@mtme.org>
998 * tic30.h (template): Rename type template to
999 insn_template. Updated code to use new name.
1000 * tic54x.h (template): Rename type template to
1003 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1005 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1007 2009-06-11 Anthony Green <green@moxielogic.com>
1009 * moxie.h (MOXIE_F3_PCREL): Define.
1010 (moxie_form3_opc_info): Grow.
1012 2009-06-06 Anthony Green <green@moxielogic.com>
1014 * moxie.h (MOXIE_F1_M): Define.
1016 2009-04-15 Anthony Green <green@moxielogic.com>
1020 2009-04-06 DJ Delorie <dj@redhat.com>
1022 * h8300.h: Add relaxation attributes to MOVA opcodes.
1024 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1026 * ppc.h (ppc_parse_cpu): Declare.
1028 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1030 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1031 and _IMM11 for mbitclr and mbitset.
1032 * score-datadep.h: Update dependency information.
1034 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1036 * ppc.h (PPC_OPCODE_POWER7): New.
1038 2009-02-06 Doug Evans <dje@google.com>
1040 * i386.h: Add comment regarding sse* insns and prefixes.
1042 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1044 * mips.h (INSN_XLR): Define.
1045 (INSN_CHIP_MASK): Update.
1047 (OPCODE_IS_MEMBER): Update.
1048 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1050 2009-01-28 Doug Evans <dje@google.com>
1052 * opcode/i386.h: Add multiple inclusion protection.
1053 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1054 (EDI_REG_NUM): New macros.
1055 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1056 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1057 (REX_PREFIX_P): New macro.
1059 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1061 * ppc.h (struct powerpc_opcode): New field "deprecated".
1062 (PPC_OPCODE_NOPOWER4): Delete.
1064 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1066 * mips.h: Define CPU_R14000, CPU_R16000.
1067 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1069 2008-11-18 Catherine Moore <clm@codesourcery.com>
1071 * arm.h (FPU_NEON_FP16): New.
1072 (FPU_ARCH_NEON_FP16): New.
1074 2008-11-06 Chao-ying Fu <fu@mips.com>
1076 * mips.h: Doucument '1' for 5-bit sync type.
1078 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1080 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1083 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1085 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1087 2008-07-30 Michael J. Eager <eager@eagercon.com>
1089 * ppc.h (PPC_OPCODE_405): Define.
1090 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1092 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1094 * ppc.h (ppc_cpu_t): New typedef.
1095 (struct powerpc_opcode <flags>): Use it.
1096 (struct powerpc_operand <insert, extract>): Likewise.
1097 (struct powerpc_macro <flags>): Likewise.
1099 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1101 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1102 Update comment before MIPS16 field descriptors to mention MIPS16.
1103 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1105 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1106 New bit masks and shift counts for cins and exts.
1108 * mips.h: Document new field descriptors +Q.
1109 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1111 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1113 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1114 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1116 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1118 * ppc.h: (PPC_OPCODE_E500MC): New.
1120 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1122 * i386.h (MAX_OPERANDS): Set to 5.
1123 (MAX_MNEM_SIZE): Changed to 20.
1125 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1127 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1129 2008-03-09 Paul Brook <paul@codesourcery.com>
1131 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1133 2008-03-04 Paul Brook <paul@codesourcery.com>
1135 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1136 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1137 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1139 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1140 Nick Clifton <nickc@redhat.com>
1143 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1144 with a 32-bit displacement but without the top bit of the 4th byte
1147 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1149 * cr16.h (cr16_num_optab): Declared.
1151 2008-02-14 Hakan Ardo <hakan@debian.org>
1154 * avr.h (AVR_ISA_2xxe): Define.
1156 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1158 * mips.h: Update copyright.
1159 (INSN_CHIP_MASK): New macro.
1160 (INSN_OCTEON): New macro.
1161 (CPU_OCTEON): New macro.
1162 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1164 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1166 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1168 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1170 * avr.h (AVR_ISA_USB162): Add new opcode set.
1171 (AVR_ISA_AVR3): Likewise.
1173 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1175 * mips.h (INSN_LOONGSON_2E): New.
1176 (INSN_LOONGSON_2F): New.
1177 (CPU_LOONGSON_2E): New.
1178 (CPU_LOONGSON_2F): New.
1179 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1181 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1183 * mips.h (INSN_ISA*): Redefine certain values as an
1184 enumeration. Update comments.
1185 (mips_isa_table): New.
1186 (ISA_MIPS*): Redefine to match enumeration.
1187 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1190 2007-08-08 Ben Elliston <bje@au.ibm.com>
1192 * ppc.h (PPC_OPCODE_PPCPS): New.
1194 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1196 * m68k.h: Document j K & E.
1198 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1200 * cr16.h: New file for CR16 target.
1202 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1204 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1206 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1208 * m68k.h (mcfisa_c): New.
1209 (mcfusp, mcf_mask): Adjust.
1211 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1213 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1214 (num_powerpc_operands): Declare.
1215 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1216 (PPC_OPERAND_PLUS1): Define.
1218 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1220 * i386.h (REX_MODE64): Renamed to ...
1222 (REX_EXTX): Renamed to ...
1224 (REX_EXTY): Renamed to ...
1226 (REX_EXTZ): Renamed to ...
1229 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1231 * i386.h: Add entries from config/tc-i386.h and move tables
1232 to opcodes/i386-opc.h.
1234 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1236 * i386.h (FloatDR): Removed.
1237 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1239 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1241 * spu-insns.h: Add soma double-float insns.
1243 2007-02-20 Thiemo Seufer <ths@mips.com>
1244 Chao-Ying Fu <fu@mips.com>
1246 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1247 (INSN_DSPR2): Add flag for DSP R2 instructions.
1248 (M_BALIGN): New macro.
1250 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1252 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1253 and Seg3ShortFrom with Shortform.
1255 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1258 * i386.h (i386_optab): Put the real "test" before the pseudo
1261 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1263 * m68k.h (m68010up): OR fido_a.
1265 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1267 * m68k.h (fido_a): New.
1269 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1271 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1272 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1275 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1277 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1279 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1281 * score-inst.h (enum score_insn_type): Add Insn_internal.
1283 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1284 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1285 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1286 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1287 Alan Modra <amodra@bigpond.net.au>
1289 * spu-insns.h: New file.
1292 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1294 * ppc.h (PPC_OPCODE_CELL): Define.
1296 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1298 * i386.h : Modify opcode to support for the change in POPCNT opcode
1299 in amdfam10 architecture.
1301 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1303 * i386.h: Replace CpuMNI with CpuSSSE3.
1305 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1306 Joseph Myers <joseph@codesourcery.com>
1307 Ian Lance Taylor <ian@wasabisystems.com>
1308 Ben Elliston <bje@wasabisystems.com>
1310 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1312 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1314 * score-datadep.h: New file.
1315 * score-inst.h: New file.
1317 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1319 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1320 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1321 movdq2q and movq2dq.
1323 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1324 Michael Meissner <michael.meissner@amd.com>
1326 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1328 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1330 * i386.h (i386_optab): Add "nop" with memory reference.
1332 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1334 * i386.h (i386_optab): Update comment for 64bit NOP.
1336 2006-06-06 Ben Elliston <bje@au.ibm.com>
1337 Anton Blanchard <anton@samba.org>
1339 * ppc.h (PPC_OPCODE_POWER6): Define.
1342 2006-06-05 Thiemo Seufer <ths@mips.com>
1344 * mips.h: Improve description of MT flags.
1346 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1348 * m68k.h (mcf_mask): Define.
1350 2006-05-05 Thiemo Seufer <ths@mips.com>
1351 David Ung <davidu@mips.com>
1353 * mips.h (enum): Add macro M_CACHE_AB.
1355 2006-05-04 Thiemo Seufer <ths@mips.com>
1356 Nigel Stephens <nigel@mips.com>
1357 David Ung <davidu@mips.com>
1359 * mips.h: Add INSN_SMARTMIPS define.
1361 2006-04-30 Thiemo Seufer <ths@mips.com>
1362 David Ung <davidu@mips.com>
1364 * mips.h: Defines udi bits and masks. Add description of
1365 characters which may appear in the args field of udi
1368 2006-04-26 Thiemo Seufer <ths@networkno.de>
1370 * mips.h: Improve comments describing the bitfield instruction
1373 2006-04-26 Julian Brown <julian@codesourcery.com>
1375 * arm.h (FPU_VFP_EXT_V3): Define constant.
1376 (FPU_NEON_EXT_V1): Likewise.
1377 (FPU_VFP_HARD): Update.
1378 (FPU_VFP_V3): Define macro.
1379 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1381 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1383 * avr.h (AVR_ISA_PWMx): New.
1385 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1387 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1388 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1389 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1390 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1391 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1393 2006-03-10 Paul Brook <paul@codesourcery.com>
1395 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1397 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1399 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1400 first. Correct mask of bb "B" opcode.
1402 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1404 * i386.h (i386_optab): Support Intel Merom New Instructions.
1406 2006-02-24 Paul Brook <paul@codesourcery.com>
1408 * arm.h: Add V7 feature bits.
1410 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1412 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1414 2006-01-31 Paul Brook <paul@codesourcery.com>
1415 Richard Earnshaw <rearnsha@arm.com>
1417 * arm.h: Use ARM_CPU_FEATURE.
1418 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1419 (arm_feature_set): Change to a structure.
1420 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1421 ARM_FEATURE): New macros.
1423 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1425 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1426 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1427 (ADD_PC_INCR_OPCODE): Don't define.
1429 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1432 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1434 2005-11-14 David Ung <davidu@mips.com>
1436 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1437 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1438 save/restore encoding of the args field.
1440 2005-10-28 Dave Brolley <brolley@redhat.com>
1442 Contribute the following changes:
1443 2005-02-16 Dave Brolley <brolley@redhat.com>
1445 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1446 cgen_isa_mask_* to cgen_bitset_*.
1449 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1451 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1452 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1453 (CGEN_CPU_TABLE): Make isas a ponter.
1455 2003-09-29 Dave Brolley <brolley@redhat.com>
1457 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1458 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1459 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1461 2002-12-13 Dave Brolley <brolley@redhat.com>
1463 * cgen.h (symcat.h): #include it.
1464 (cgen-bitset.h): #include it.
1465 (CGEN_ATTR_VALUE_TYPE): Now a union.
1466 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1467 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1468 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1469 * cgen-bitset.h: New file.
1471 2005-09-30 Catherine Moore <clm@cm00re.com>
1475 2005-10-24 Jan Beulich <jbeulich@novell.com>
1477 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1480 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1482 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1483 Add FLAG_STRICT to pa10 ftest opcode.
1485 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1487 * hppa.h (pa_opcodes): Remove lha entries.
1489 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1491 * hppa.h (FLAG_STRICT): Revise comment.
1492 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1493 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1496 2005-09-30 Catherine Moore <clm@cm00re.com>
1500 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1502 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1504 2005-09-06 Chao-ying Fu <fu@mips.com>
1506 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1507 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1509 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1510 (INSN_ASE_MASK): Update to include INSN_MT.
1511 (INSN_MT): New define for MT ASE.
1513 2005-08-25 Chao-ying Fu <fu@mips.com>
1515 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1516 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1517 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1518 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1519 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1520 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1522 (INSN_DSP): New define for DSP ASE.
1524 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1528 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1530 * ppc.h (PPC_OPCODE_E300): Define.
1532 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1534 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1536 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1539 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1542 2005-07-27 Jan Beulich <jbeulich@novell.com>
1544 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1545 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1546 Add movq-s as 64-bit variants of movd-s.
1548 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1550 * hppa.h: Fix punctuation in comment.
1552 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1553 implicit space-register addressing. Set space-register bits on opcodes
1554 using implicit space-register addressing. Add various missing pa20
1555 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1556 space-register addressing. Use "fE" instead of "fe" in various
1559 2005-07-18 Jan Beulich <jbeulich@novell.com>
1561 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1563 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1565 * i386.h (i386_optab): Support Intel VMX Instructions.
1567 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1569 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1571 2005-07-05 Jan Beulich <jbeulich@novell.com>
1573 * i386.h (i386_optab): Add new insns.
1575 2005-07-01 Nick Clifton <nickc@redhat.com>
1577 * sparc.h: Add typedefs to structure declarations.
1579 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1582 * i386.h (i386_optab): Update comments for 64bit addressing on
1583 mov. Allow 64bit addressing for mov and movq.
1585 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1587 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1588 respectively, in various floating-point load and store patterns.
1590 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1592 * hppa.h (FLAG_STRICT): Correct comment.
1593 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1594 PA 2.0 mneumonics when equivalent. Entries with cache control
1595 completers now require PA 1.1. Adjust whitespace.
1597 2005-05-19 Anton Blanchard <anton@samba.org>
1599 * ppc.h (PPC_OPCODE_POWER5): Define.
1601 2005-05-10 Nick Clifton <nickc@redhat.com>
1603 * Update the address and phone number of the FSF organization in
1604 the GPL notices in the following files:
1605 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1606 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1607 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1608 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1609 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1610 tic54x.h, tic80.h, v850.h, vax.h
1612 2005-05-09 Jan Beulich <jbeulich@novell.com>
1614 * i386.h (i386_optab): Add ht and hnt.
1616 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1618 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1619 Add xcrypt-ctr. Provide aliases without hyphens.
1621 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1623 Moved from ../ChangeLog
1625 2005-04-12 Paul Brook <paul@codesourcery.com>
1626 * m88k.h: Rename psr macros to avoid conflicts.
1628 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1629 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1630 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1631 and ARM_ARCH_V6ZKT2.
1633 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1634 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1635 Remove redundant instruction types.
1636 (struct argument): X_op - new field.
1637 (struct cst4_entry): Remove.
1638 (no_op_insn): Declare.
1640 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1641 * crx.h (enum argtype): Rename types, remove unused types.
1643 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1644 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1645 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1646 (enum operand_type): Rearrange operands, edit comments.
1647 replace us<N> with ui<N> for unsigned immediate.
1648 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1649 displacements (respectively).
1650 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1651 (instruction type): Add NO_TYPE_INS.
1652 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1653 (operand_entry): New field - 'flags'.
1654 (operand flags): New.
1656 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1657 * crx.h (operand_type): Remove redundant types i3, i4,
1659 Add new unsigned immediate types us3, us4, us5, us16.
1661 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1663 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1664 adjust them accordingly.
1666 2005-04-01 Jan Beulich <jbeulich@novell.com>
1668 * i386.h (i386_optab): Add rdtscp.
1670 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1672 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1673 between memory and segment register. Allow movq for moving between
1674 general-purpose register and segment register.
1676 2005-02-09 Jan Beulich <jbeulich@novell.com>
1679 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1680 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1683 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1685 * m68k.h (m68008, m68ec030, m68882): Remove.
1687 (cpu_m68k, cpu_cf): New.
1688 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1689 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1691 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1693 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1694 * cgen.h (enum cgen_parse_operand_type): Add
1695 CGEN_PARSE_OPERAND_SYMBOLIC.
1697 2005-01-21 Fred Fish <fnf@specifixinc.com>
1699 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1700 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1701 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1703 2005-01-19 Fred Fish <fnf@specifixinc.com>
1705 * mips.h (struct mips_opcode): Add new pinfo2 member.
1706 (INSN_ALIAS): New define for opcode table entries that are
1707 specific instances of another entry, such as 'move' for an 'or'
1708 with a zero operand.
1709 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1710 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1712 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1714 * mips.h (CPU_RM9000): Define.
1715 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1717 2004-11-25 Jan Beulich <jbeulich@novell.com>
1719 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1720 to/from test registers are illegal in 64-bit mode. Add missing
1721 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1722 (previously one had to explicitly encode a rex64 prefix). Re-enable
1723 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1724 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1726 2004-11-23 Jan Beulich <jbeulich@novell.com>
1728 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1729 available only with SSE2. Change the MMX additions introduced by SSE
1730 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1731 instructions by their now designated identifier (since combining i686
1732 and 3DNow! does not really imply 3DNow!A).
1734 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1736 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1737 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1739 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1740 Vineet Sharma <vineets@noida.hcltech.com>
1742 * maxq.h: New file: Disassembly information for the maxq port.
1744 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1746 * i386.h (i386_optab): Put back "movzb".
1748 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1750 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1751 comments. Remove member cris_ver_sim. Add members
1752 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1753 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1754 (struct cris_support_reg, struct cris_cond15): New types.
1755 (cris_conds15): Declare.
1756 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1757 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1758 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1759 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1760 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1761 SIZE_FIELD_UNSIGNED.
1763 2004-11-04 Jan Beulich <jbeulich@novell.com>
1765 * i386.h (sldx_Suf): Remove.
1766 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1767 (q_FP): Define, implying no REX64.
1768 (x_FP, sl_FP): Imply FloatMF.
1769 (i386_optab): Split reg and mem forms of moving from segment registers
1770 so that the memory forms can ignore the 16-/32-bit operand size
1771 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1772 all non-floating-point instructions. Unite 32- and 64-bit forms of
1773 movsx, movzx, and movd. Adjust floating point operations for the above
1774 changes to the *FP macros. Add DefaultSize to floating point control
1775 insns operating on larger memory ranges. Remove left over comments
1776 hinting at certain insns being Intel-syntax ones where the ones
1777 actually meant are already gone.
1779 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1781 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1784 2004-09-30 Paul Brook <paul@codesourcery.com>
1786 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1787 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1789 2004-09-11 Theodore A. Roth <troth@openavr.org>
1791 * avr.h: Add support for
1792 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1794 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1796 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1798 2004-08-24 Dmitry Diky <diwil@spec.ru>
1800 * msp430.h (msp430_opc): Add new instructions.
1801 (msp430_rcodes): Declare new instructions.
1802 (msp430_hcodes): Likewise..
1804 2004-08-13 Nick Clifton <nickc@redhat.com>
1807 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1810 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1812 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1814 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1816 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1818 2004-07-21 Jan Beulich <jbeulich@novell.com>
1820 * i386.h: Adjust instruction descriptions to better match the
1823 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1825 * arm.h: Remove all old content. Replace with architecture defines
1826 from gas/config/tc-arm.c.
1828 2004-07-09 Andreas Schwab <schwab@suse.de>
1830 * m68k.h: Fix comment.
1832 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1836 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1838 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1840 2004-05-24 Peter Barada <peter@the-baradas.com>
1842 * m68k.h: Add 'size' to m68k_opcode.
1844 2004-05-05 Peter Barada <peter@the-baradas.com>
1846 * m68k.h: Switch from ColdFire chip name to core variant.
1848 2004-04-22 Peter Barada <peter@the-baradas.com>
1850 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1851 descriptions for new EMAC cases.
1852 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1853 handle Motorola MAC syntax.
1854 Allow disassembly of ColdFire V4e object files.
1856 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1858 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1860 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1862 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1864 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1866 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1868 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1870 * i386.h (i386_optab): Added xstore/xcrypt insns.
1872 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1874 * h8300.h (32bit ldc/stc): Add relaxing support.
1876 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1878 * h8300.h (BITOP): Pass MEMRELAX flag.
1880 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1882 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1885 For older changes see ChangeLog-9103
1887 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1889 Copying and distribution of this file, with or without modification,
1890 are permitted in any medium without royalty provided the copyright
1891 notice and this notice are preserved.
1897 version-control: never
projects / deliverable / binutils-gdb.git / blob