include/opcode/ChangeLog

   1 2009-10-23  Doug Evans  <dje@sebabeach.org>
   2
   3         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
   4         * cgen.h: Update.  Improve multi-inclusion macro name.
   5
   6 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
   7
   8         * ppc.h (PPC_OPCODE_476): Define.
   9
  10 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
  11
  12         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
  13
  14 2009-09-29  DJ Delorie  <dj@redhat.com>
  15
  16         * rx.h: New file.
  17
  18 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  19
  20         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  21
  22 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  23
  24         * ppc.h (PPC_OPCODE_PPCA2): New.
  25
  26 2009-09-05  Martin Thuresson  <martin@mtme.org>
  27
  28         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  29
  30 2009-08-29  Martin Thuresson  <martin@mtme.org>
  31
  32         * tic30.h (template): Rename type template to
  33         insn_template. Updated code to use new name.
  34         * tic54x.h (template): Rename type template to
  35         insn_template.
  36
  37 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  38
  39         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  40
  41 2009-06-11  Anthony Green  <green@moxielogic.com>
  42
  43         * moxie.h (MOXIE_F3_PCREL): Define.
  44         (moxie_form3_opc_info): Grow.
  45
  46 2009-06-06  Anthony Green  <green@moxielogic.com>
  47
  48         * moxie.h (MOXIE_F1_M): Define.
  49
  50 2009-04-15  Anthony Green  <green@moxielogic.com>
  51
  52         * moxie.h: Created.
  53
  54 2009-04-06  DJ Delorie  <dj@redhat.com>
  55
  56         * h8300.h: Add relaxation attributes to MOVA opcodes.
  57
  58 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  59
  60         * ppc.h (ppc_parse_cpu): Declare.
  61
  62 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  63
  64         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  65         and _IMM11 for mbitclr and mbitset.
  66         * score-datadep.h: Update dependency information.
  67
  68 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  69
  70         * ppc.h (PPC_OPCODE_POWER7): New.
  71
  72 2009-02-06  Doug Evans  <dje@google.com>
  73
  74         * i386.h: Add comment regarding sse* insns and prefixes.
  75
  76 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  77
  78         * mips.h (INSN_XLR): Define.
  79         (INSN_CHIP_MASK): Update.
  80         (CPU_XLR): Define.
  81         (OPCODE_IS_MEMBER): Update.
  82         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  83
  84 2009-01-28  Doug Evans  <dje@google.com>
  85
  86         * opcode/i386.h: Add multiple inclusion protection.
  87         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  88         (EDI_REG_NUM): New macros.
  89         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  90         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  91         (REX_PREFIX_P): New macro.
  92
  93 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  94
  95         * ppc.h (struct powerpc_opcode): New field "deprecated".
  96         (PPC_OPCODE_NOPOWER4): Delete.
  97
  98 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  99
 100         * mips.h: Define CPU_R14000, CPU_R16000.
 101         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 102
 103 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 104
 105         * arm.h (FPU_NEON_FP16): New.
 106         (FPU_ARCH_NEON_FP16): New.
 107
 108 2008-11-06  Chao-ying Fu  <fu@mips.com>
 109
 110         * mips.h: Doucument '1' for 5-bit sync type.
 111
 112 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 115         IA64_RS_CR.
 116
 117 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 118
 119         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 120
 121 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 122
 123         * ppc.h (PPC_OPCODE_405): Define.
 124         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 125
 126 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 127
 128         * ppc.h (ppc_cpu_t): New typedef.
 129         (struct powerpc_opcode <flags>): Use it.
 130         (struct powerpc_operand <insert, extract>): Likewise.
 131         (struct powerpc_macro <flags>): Likewise.
 132
 133 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 134
 135         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 136         Update comment before MIPS16 field descriptors to mention MIPS16.
 137         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 138         BBIT.
 139         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 140         New bit masks and shift counts for cins and exts.
 141
 142         * mips.h: Document new field descriptors +Q.
 143         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 144
 145 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 146
 147         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 148         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 149
 150 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 151
 152         * ppc.h: (PPC_OPCODE_E500MC): New.
 153
 154 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         * i386.h (MAX_OPERANDS): Set to 5.
 157         (MAX_MNEM_SIZE): Changed to 20.
 158
 159 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 160
 161         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 162
 163 2008-03-09  Paul Brook  <paul@codesourcery.com>
 164
 165         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 166
 167 2008-03-04  Paul Brook  <paul@codesourcery.com>
 168
 169         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 170         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 171         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 172
 173 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 174             Nick Clifton  <nickc@redhat.com>
 175
 176         PR 3134
 177         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 178         with a 32-bit displacement but without the top bit of the 4th byte
 179         set.
 180
 181 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 182
 183         * cr16.h (cr16_num_optab): Declared.
 184
 185 2008-02-14  Hakan Ardo  <hakan@debian.org>
 186
 187         PR gas/2626
 188         * avr.h (AVR_ISA_2xxe): Define.
 189
 190 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 191
 192         * mips.h: Update copyright.
 193         (INSN_CHIP_MASK): New macro.
 194         (INSN_OCTEON): New macro.
 195         (CPU_OCTEON): New macro.
 196         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 197
 198 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 199
 200         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 201
 202 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 203
 204         * avr.h (AVR_ISA_USB162): Add new opcode set.
 205         (AVR_ISA_AVR3): Likewise.
 206
 207 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 208
 209         * mips.h (INSN_LOONGSON_2E): New.
 210         (INSN_LOONGSON_2F): New.
 211         (CPU_LOONGSON_2E): New.
 212         (CPU_LOONGSON_2F): New.
 213         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 214
 215 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 216
 217         * mips.h (INSN_ISA*): Redefine certain values as an
 218         enumeration.  Update comments.
 219         (mips_isa_table): New.
 220         (ISA_MIPS*): Redefine to match enumeration.
 221         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 222         values.
 223
 224 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 225
 226         * ppc.h (PPC_OPCODE_PPCPS): New.
 227
 228 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 229
 230         * m68k.h: Document j K & E.
 231
 232 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 233
 234         * cr16.h: New file for CR16 target.
 235
 236 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 237
 238         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 239
 240 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 241
 242         * m68k.h (mcfisa_c): New.
 243         (mcfusp, mcf_mask): Adjust.
 244
 245 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 246
 247         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 248         (num_powerpc_operands): Declare.
 249         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 250         (PPC_OPERAND_PLUS1): Define.
 251
 252 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 253
 254         * i386.h (REX_MODE64): Renamed to ...
 255         (REX_W): This.
 256         (REX_EXTX): Renamed to ...
 257         (REX_R): This.
 258         (REX_EXTY): Renamed to ...
 259         (REX_X): This.
 260         (REX_EXTZ): Renamed to ...
 261         (REX_B): This.
 262
 263 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         * i386.h: Add entries from config/tc-i386.h and move tables
 266         to opcodes/i386-opc.h.
 267
 268 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 269
 270         * i386.h (FloatDR): Removed.
 271         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 272
 273 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 274
 275         * spu-insns.h: Add soma double-float insns.
 276
 277 2007-02-20  Thiemo Seufer  <ths@mips.com>
 278             Chao-Ying Fu  <fu@mips.com>
 279
 280         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 281         (INSN_DSPR2): Add flag for DSP R2 instructions.
 282         (M_BALIGN): New macro.
 283
 284 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 285
 286         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 287         and Seg3ShortFrom with Shortform.
 288
 289 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         PR gas/4027
 292         * i386.h (i386_optab): Put the real "test" before the pseudo
 293         one.
 294
 295 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 296
 297         * m68k.h (m68010up): OR fido_a.
 298
 299 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 300
 301         * m68k.h (fido_a): New.
 302
 303 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 304
 305         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 306         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 307         values.
 308
 309 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 312
 313 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 314
 315         * score-inst.h (enum score_insn_type): Add Insn_internal.
 316
 317 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 318             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 319             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 320             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 321             Alan Modra  <amodra@bigpond.net.au>
 322
 323         * spu-insns.h: New file.
 324         * spu.h: New file.
 325
 326 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 327
 328         * ppc.h (PPC_OPCODE_CELL): Define.
 329
 330 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 331
 332         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 333         in amdfam10 architecture.
 334
 335 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386.h: Replace CpuMNI with CpuSSSE3.
 338
 339 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 340             Joseph Myers  <joseph@codesourcery.com>
 341             Ian Lance Taylor  <ian@wasabisystems.com>
 342             Ben Elliston  <bje@wasabisystems.com>
 343
 344         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 345
 346 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 347
 348         * score-datadep.h: New file.
 349         * score-inst.h: New file.
 350
 351 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 354         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 355         movdq2q and movq2dq.
 356
 357 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 358            Michael Meissner             <michael.meissner@amd.com>
 359
 360         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 361
 362 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 363
 364         * i386.h (i386_optab): Add "nop" with memory reference.
 365
 366 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386.h (i386_optab): Update comment for 64bit NOP.
 369
 370 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 371             Anton Blanchard  <anton@samba.org>
 372
 373         * ppc.h (PPC_OPCODE_POWER6): Define.
 374         Adjust whitespace.
 375
 376 2006-06-05  Thiemo Seufer  <ths@mips.com>
 377
 378         * mips.h: Improve description of MT flags.
 379
 380 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 381
 382         * m68k.h (mcf_mask): Define.
 383
 384 2006-05-05  Thiemo Seufer  <ths@mips.com>
 385             David Ung  <davidu@mips.com>
 386
 387         * mips.h (enum): Add macro M_CACHE_AB.
 388
 389 2006-05-04  Thiemo Seufer  <ths@mips.com>
 390             Nigel Stephens  <nigel@mips.com>
 391             David Ung  <davidu@mips.com>
 392
 393         * mips.h: Add INSN_SMARTMIPS define.
 394
 395 2006-04-30  Thiemo Seufer  <ths@mips.com>
 396             David Ung  <davidu@mips.com>
 397
 398         * mips.h: Defines udi bits and masks.  Add description of
 399         characters which may appear in the args field of udi
 400         instructions.
 401
 402 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 403
 404         * mips.h: Improve comments describing the bitfield instruction
 405         fields.
 406
 407 2006-04-26  Julian Brown  <julian@codesourcery.com>
 408
 409         * arm.h (FPU_VFP_EXT_V3): Define constant.
 410         (FPU_NEON_EXT_V1): Likewise.
 411         (FPU_VFP_HARD): Update.
 412         (FPU_VFP_V3): Define macro.
 413         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 414
 415 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 416
 417         * avr.h (AVR_ISA_PWMx): New.
 418
 419 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 420
 421         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 422         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 423         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 424         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 425         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 426
 427 2006-03-10  Paul Brook  <paul@codesourcery.com>
 428
 429         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 430
 431 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 432
 433         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 434         first.  Correct mask of bb "B" opcode.
 435
 436 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 437
 438         * i386.h (i386_optab): Support Intel Merom New Instructions.
 439
 440 2006-02-24  Paul Brook  <paul@codesourcery.com>
 441
 442         * arm.h: Add V7 feature bits.
 443
 444 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 445
 446         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 447
 448 2006-01-31  Paul Brook  <paul@codesourcery.com>
 449         Richard Earnshaw <rearnsha@arm.com>
 450
 451         * arm.h: Use ARM_CPU_FEATURE.
 452         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 453         (arm_feature_set): Change to a structure.
 454         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 455         ARM_FEATURE): New macros.
 456
 457 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 458
 459         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 460         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 461         (ADD_PC_INCR_OPCODE): Don't define.
 462
 463 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         PR gas/1874
 466         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 467
 468 2005-11-14  David Ung  <davidu@mips.com>
 469
 470         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 471         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 472         save/restore encoding of the args field.
 473
 474 2005-10-28  Dave Brolley  <brolley@redhat.com>
 475
 476         Contribute the following changes:
 477         2005-02-16  Dave Brolley  <brolley@redhat.com>
 478
 479         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 480         cgen_isa_mask_* to cgen_bitset_*.
 481         * cgen.h: Likewise.
 482
 483         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 484
 485         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 486         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 487         (CGEN_CPU_TABLE): Make isas a ponter.
 488
 489         2003-09-29  Dave Brolley  <brolley@redhat.com>
 490
 491         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 492         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 493         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 494
 495         2002-12-13  Dave Brolley  <brolley@redhat.com>
 496
 497         * cgen.h (symcat.h): #include it.
 498         (cgen-bitset.h): #include it.
 499         (CGEN_ATTR_VALUE_TYPE): Now a union.
 500         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 501         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 502         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 503         * cgen-bitset.h: New file.
 504
 505 2005-09-30  Catherine Moore  <clm@cm00re.com>
 506
 507         * bfin.h: New file.
 508
 509 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 510
 511         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 512         indirect operands.
 513
 514 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 515
 516         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 517         Add FLAG_STRICT to pa10 ftest opcode.
 518
 519 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 520
 521         * hppa.h (pa_opcodes): Remove lha entries.
 522
 523 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 524
 525         * hppa.h (FLAG_STRICT): Revise comment.
 526         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 527         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 528         entries for "fdc".
 529
 530 2005-09-30  Catherine Moore  <clm@cm00re.com>
 531
 532         * bfin.h: New file.
 533
 534 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 535
 536         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 537
 538 2005-09-06  Chao-ying Fu  <fu@mips.com>
 539
 540         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 541         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 542         define.
 543         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 544         (INSN_ASE_MASK): Update to include INSN_MT.
 545         (INSN_MT): New define for MT ASE.
 546
 547 2005-08-25  Chao-ying Fu  <fu@mips.com>
 548
 549         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 550         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 551         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 552         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 553         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 554         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 555         instructions.
 556         (INSN_DSP): New define for DSP ASE.
 557
 558 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 559
 560         * a29k.h: Delete.
 561
 562 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 563
 564         * ppc.h (PPC_OPCODE_E300): Define.
 565
 566 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 567
 568         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 569
 570 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 571
 572         PR gas/336
 573         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 574         and pitlb.
 575
 576 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 577
 578         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 579         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 580         Add movq-s as 64-bit variants of movd-s.
 581
 582 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 583
 584         * hppa.h: Fix punctuation in comment.
 585
 586         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 587         implicit space-register addressing.  Set space-register bits on opcodes
 588         using implicit space-register addressing.  Add various missing pa20
 589         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 590         space-register addressing.  Use "fE" instead of "fe" in various
 591         fstw opcodes.
 592
 593 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 594
 595         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 596
 597 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 598
 599         * i386.h (i386_optab): Support Intel VMX Instructions.
 600
 601 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 602
 603         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 604
 605 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 606
 607         * i386.h (i386_optab): Add new insns.
 608
 609 2005-07-01  Nick Clifton  <nickc@redhat.com>
 610
 611         * sparc.h: Add typedefs to structure declarations.
 612
 613 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 614
 615         PR 1013
 616         * i386.h (i386_optab): Update comments for 64bit addressing on
 617         mov. Allow 64bit addressing for mov and movq.
 618
 619 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 620
 621         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 622         respectively, in various floating-point load and store patterns.
 623
 624 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 625
 626         * hppa.h (FLAG_STRICT): Correct comment.
 627         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 628         PA 2.0 mneumonics when equivalent.  Entries with cache control
 629         completers now require PA 1.1.  Adjust whitespace.
 630
 631 2005-05-19  Anton Blanchard  <anton@samba.org>
 632
 633         * ppc.h (PPC_OPCODE_POWER5): Define.
 634
 635 2005-05-10  Nick Clifton  <nickc@redhat.com>
 636
 637         * Update the address and phone number of the FSF organization in
 638         the GPL notices in the following files:
 639         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 640         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 641         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 642         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 643         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 644         tic54x.h, tic80.h, v850.h, vax.h
 645
 646 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 647
 648         * i386.h (i386_optab): Add ht and hnt.
 649
 650 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 651
 652         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 653         Add xcrypt-ctr.  Provide aliases without hyphens.
 654
 655 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         Moved from ../ChangeLog
 658
 659         2005-04-12  Paul Brook  <paul@codesourcery.com>
 660         * m88k.h: Rename psr macros to avoid conflicts.
 661
 662         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 663         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 664         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 665         and ARM_ARCH_V6ZKT2.
 666
 667         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 668         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 669         Remove redundant instruction types.
 670         (struct argument): X_op - new field.
 671         (struct cst4_entry): Remove.
 672         (no_op_insn): Declare.
 673
 674         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 675         * crx.h (enum argtype): Rename types, remove unused types.
 676
 677         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 678         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 679         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 680         (enum operand_type): Rearrange operands, edit comments.
 681         replace us<N> with ui<N> for unsigned immediate.
 682         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 683         displacements (respectively).
 684         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 685         (instruction type): Add NO_TYPE_INS.
 686         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 687         (operand_entry): New field - 'flags'.
 688         (operand flags): New.
 689
 690         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 691         * crx.h (operand_type): Remove redundant types i3, i4,
 692         i5, i8, i12.
 693         Add new unsigned immediate types us3, us4, us5, us16.
 694
 695 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 696
 697         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 698         adjust them accordingly.
 699
 700 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 701
 702         * i386.h (i386_optab): Add rdtscp.
 703
 704 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 705
 706         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 707         between memory and segment register. Allow movq for moving between
 708         general-purpose register and segment register.
 709
 710 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 711
 712         PR gas/707
 713         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 714         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 715         fnstsw.
 716
 717 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 718
 719         * m68k.h (m68008, m68ec030, m68882): Remove.
 720         (m68k_mask): New.
 721         (cpu_m68k, cpu_cf): New.
 722         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 723         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 724
 725 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 726
 727         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 728         * cgen.h (enum cgen_parse_operand_type): Add
 729         CGEN_PARSE_OPERAND_SYMBOLIC.
 730
 731 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 732
 733         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 734         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 735         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 736
 737 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 738
 739         * mips.h (struct mips_opcode): Add new pinfo2 member.
 740         (INSN_ALIAS): New define for opcode table entries that are
 741         specific instances of another entry, such as 'move' for an 'or'
 742         with a zero operand.
 743         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 744         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 745
 746 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 747
 748         * mips.h (CPU_RM9000): Define.
 749         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 750
 751 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 752
 753         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 754         to/from test registers are illegal in 64-bit mode. Add missing
 755         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 756         (previously one had to explicitly encode a rex64 prefix). Re-enable
 757         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 758         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 759
 760 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 761
 762         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 763         available only with SSE2. Change the MMX additions introduced by SSE
 764         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 765         instructions by their now designated identifier (since combining i686
 766         and 3DNow! does not really imply 3DNow!A).
 767
 768 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 769
 770         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 771         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 772
 773 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 774             Vineet Sharma      <vineets@noida.hcltech.com>
 775
 776         * maxq.h: New file: Disassembly information for the maxq port.
 777
 778 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         * i386.h (i386_optab): Put back "movzb".
 781
 782 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 783
 784         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 785         comments.  Remove member cris_ver_sim.  Add members
 786         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 787         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 788         (struct cris_support_reg, struct cris_cond15): New types.
 789         (cris_conds15): Declare.
 790         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 791         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 792         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 793         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 794         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 795         SIZE_FIELD_UNSIGNED.
 796
 797 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 798
 799         * i386.h (sldx_Suf): Remove.
 800         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 801         (q_FP): Define, implying no REX64.
 802         (x_FP, sl_FP): Imply FloatMF.
 803         (i386_optab): Split reg and mem forms of moving from segment registers
 804         so that the memory forms can ignore the 16-/32-bit operand size
 805         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 806         all non-floating-point instructions. Unite 32- and 64-bit forms of
 807         movsx, movzx, and movd. Adjust floating point operations for the above
 808         changes to the *FP macros. Add DefaultSize to floating point control
 809         insns operating on larger memory ranges. Remove left over comments
 810         hinting at certain insns being Intel-syntax ones where the ones
 811         actually meant are already gone.
 812
 813 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 814
 815         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 816         instruction type.
 817
 818 2004-09-30  Paul Brook  <paul@codesourcery.com>
 819
 820         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 821         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 822
 823 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 824
 825         * avr.h: Add support for
 826         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 827
 828 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 829
 830         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 831
 832 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 833
 834         * msp430.h (msp430_opc): Add new instructions.
 835         (msp430_rcodes): Declare new instructions.
 836         (msp430_hcodes): Likewise..
 837
 838 2004-08-13  Nick Clifton  <nickc@redhat.com>
 839
 840         PR/301
 841         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 842         processors.
 843
 844 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 845
 846         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 847
 848 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 849
 850         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 851
 852 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 853
 854         * i386.h: Adjust instruction descriptions to better match the
 855         specification.
 856
 857 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 858
 859         * arm.h: Remove all old content.  Replace with architecture defines
 860         from gas/config/tc-arm.c.
 861
 862 2004-07-09  Andreas Schwab  <schwab@suse.de>
 863
 864         * m68k.h: Fix comment.
 865
 866 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 867
 868         * crx.h: New file.
 869
 870 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 871
 872         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 873
 874 2004-05-24  Peter Barada  <peter@the-baradas.com>
 875
 876         * m68k.h: Add 'size' to m68k_opcode.
 877
 878 2004-05-05  Peter Barada  <peter@the-baradas.com>
 879
 880         * m68k.h: Switch from ColdFire chip name to core variant.
 881
 882 2004-04-22  Peter Barada  <peter@the-baradas.com>
 883
 884         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 885         descriptions for new EMAC cases.
 886         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 887         handle Motorola MAC syntax.
 888         Allow disassembly of ColdFire V4e object files.
 889
 890 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 891
 892         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 893
 894 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 895
 896         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 897
 898 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 899
 900         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 901
 902 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 903
 904         * i386.h (i386_optab): Added xstore/xcrypt insns.
 905
 906 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 907
 908         * h8300.h (32bit ldc/stc): Add relaxing support.
 909
 910 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 911
 912         * h8300.h (BITOP): Pass MEMRELAX flag.
 913
 914 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 915
 916         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 917         except for the H8S.
 918
 919 For older changes see ChangeLog-9103
 920 \f
 921 Local Variables:
 922 mode: change-log
 923 left-margin: 8
 924 fill-column: 74
 925 version-control: never
 926 End: