1 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
3 * ppc.h: (PPC_OPCODE_E500MC): New.
5 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
7 * i386.h (MAX_OPERANDS): Set to 5.
8 (MAX_MNEM_SIZE): Changed to 20.
10 2008-03-09 Paul Brook <paul@codesourcery.com>
12 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
14 2008-03-04 Paul Brook <paul@codesourcery.com>
16 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
17 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
18 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
20 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
21 Nick Clifton <nickc@redhat.com>
24 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
25 with a 32-bit displacement but without the top bit of the 4th byte
28 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
30 * cr16.h (cr16_num_optab): Declared.
32 2008-02-14 Hakan Ardo <hakan@debian.org>
35 * avr.h (AVR_ISA_2xxe): Define.
37 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
39 * mips.h: Update copyright.
40 (INSN_CHIP_MASK): New macro.
41 (INSN_OCTEON): New macro.
42 (CPU_OCTEON): New macro.
43 (OPCODE_IS_MEMBER): Handle Octeon instructions.
45 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
47 * mips.h (INSN_LOONGSON_2E): New.
48 (INSN_LOONGSON_2F): New.
49 (CPU_LOONGSON_2E): New.
50 (CPU_LOONGSON_2F): New.
51 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
53 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
55 * mips.h (INSN_ISA*): Redefine certain values as an
56 enumeration. Update comments.
57 (mips_isa_table): New.
58 (ISA_MIPS*): Redefine to match enumeration.
59 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
62 2007-08-08 Ben Elliston <bje@au.ibm.com>
64 * ppc.h (PPC_OPCODE_PPCPS): New.
66 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
68 * m68k.h: Document j K & E.
70 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
72 * cr16.h: New file for CR16 target.
74 2007-05-02 Alan Modra <amodra@bigpond.net.au>
76 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
78 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
80 * m68k.h (mcfisa_c): New.
81 (mcfusp, mcf_mask): Adjust.
83 2007-04-20 Alan Modra <amodra@bigpond.net.au>
85 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
86 (num_powerpc_operands): Declare.
87 (PPC_OPERAND_SIGNED et al): Redefine as hex.
88 (PPC_OPERAND_PLUS1): Define.
90 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
92 * i386.h (REX_MODE64): Renamed to ...
94 (REX_EXTX): Renamed to ...
96 (REX_EXTY): Renamed to ...
98 (REX_EXTZ): Renamed to ...
101 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
103 * i386.h: Add entries from config/tc-i386.h and move tables
104 to opcodes/i386-opc.h.
106 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
108 * i386.h (FloatDR): Removed.
109 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
111 2007-03-01 Alan Modra <amodra@bigpond.net.au>
113 * spu-insns.h: Add soma double-float insns.
115 2007-02-20 Thiemo Seufer <ths@mips.com>
116 Chao-Ying Fu <fu@mips.com>
118 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
119 (INSN_DSPR2): Add flag for DSP R2 instructions.
120 (M_BALIGN): New macro.
122 2007-02-14 Alan Modra <amodra@bigpond.net.au>
124 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
125 and Seg3ShortFrom with Shortform.
127 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
130 * i386.h (i386_optab): Put the real "test" before the pseudo
133 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
135 * m68k.h (m68010up): OR fido_a.
137 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
139 * m68k.h (fido_a): New.
141 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
143 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
144 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
147 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
149 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
151 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
153 * score-inst.h (enum score_insn_type): Add Insn_internal.
155 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
156 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
157 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
158 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
159 Alan Modra <amodra@bigpond.net.au>
161 * spu-insns.h: New file.
164 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
166 * ppc.h (PPC_OPCODE_CELL): Define.
168 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
170 * i386.h : Modify opcode to support for the change in POPCNT opcode
171 in amdfam10 architecture.
173 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
175 * i386.h: Replace CpuMNI with CpuSSSE3.
177 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
178 Joseph Myers <joseph@codesourcery.com>
179 Ian Lance Taylor <ian@wasabisystems.com>
180 Ben Elliston <bje@wasabisystems.com>
182 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
184 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
186 * score-datadep.h: New file.
187 * score-inst.h: New file.
189 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
191 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
192 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
195 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
196 Michael Meissner <michael.meissner@amd.com>
198 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
200 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
202 * i386.h (i386_optab): Add "nop" with memory reference.
204 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
206 * i386.h (i386_optab): Update comment for 64bit NOP.
208 2006-06-06 Ben Elliston <bje@au.ibm.com>
209 Anton Blanchard <anton@samba.org>
211 * ppc.h (PPC_OPCODE_POWER6): Define.
214 2006-06-05 Thiemo Seufer <ths@mips.com>
216 * mips.h: Improve description of MT flags.
218 2006-05-25 Richard Sandiford <richard@codesourcery.com>
220 * m68k.h (mcf_mask): Define.
222 2006-05-05 Thiemo Seufer <ths@mips.com>
223 David Ung <davidu@mips.com>
225 * mips.h (enum): Add macro M_CACHE_AB.
227 2006-05-04 Thiemo Seufer <ths@mips.com>
228 Nigel Stephens <nigel@mips.com>
229 David Ung <davidu@mips.com>
231 * mips.h: Add INSN_SMARTMIPS define.
233 2006-04-30 Thiemo Seufer <ths@mips.com>
234 David Ung <davidu@mips.com>
236 * mips.h: Defines udi bits and masks. Add description of
237 characters which may appear in the args field of udi
240 2006-04-26 Thiemo Seufer <ths@networkno.de>
242 * mips.h: Improve comments describing the bitfield instruction
245 2006-04-26 Julian Brown <julian@codesourcery.com>
247 * arm.h (FPU_VFP_EXT_V3): Define constant.
248 (FPU_NEON_EXT_V1): Likewise.
249 (FPU_VFP_HARD): Update.
250 (FPU_VFP_V3): Define macro.
251 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
253 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
255 * avr.h (AVR_ISA_PWMx): New.
257 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
259 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
260 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
261 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
262 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
263 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
265 2006-03-10 Paul Brook <paul@codesourcery.com>
267 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
269 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
271 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
272 first. Correct mask of bb "B" opcode.
274 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
276 * i386.h (i386_optab): Support Intel Merom New Instructions.
278 2006-02-24 Paul Brook <paul@codesourcery.com>
280 * arm.h: Add V7 feature bits.
282 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
284 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
286 2006-01-31 Paul Brook <paul@codesourcery.com>
287 Richard Earnshaw <rearnsha@arm.com>
289 * arm.h: Use ARM_CPU_FEATURE.
290 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
291 (arm_feature_set): Change to a structure.
292 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
293 ARM_FEATURE): New macros.
295 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
297 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
298 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
299 (ADD_PC_INCR_OPCODE): Don't define.
301 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
304 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
306 2005-11-14 David Ung <davidu@mips.com>
308 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
309 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
310 save/restore encoding of the args field.
312 2005-10-28 Dave Brolley <brolley@redhat.com>
314 Contribute the following changes:
315 2005-02-16 Dave Brolley <brolley@redhat.com>
317 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
318 cgen_isa_mask_* to cgen_bitset_*.
321 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
323 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
324 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
325 (CGEN_CPU_TABLE): Make isas a ponter.
327 2003-09-29 Dave Brolley <brolley@redhat.com>
329 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
330 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
331 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
333 2002-12-13 Dave Brolley <brolley@redhat.com>
335 * cgen.h (symcat.h): #include it.
336 (cgen-bitset.h): #include it.
337 (CGEN_ATTR_VALUE_TYPE): Now a union.
338 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
339 (CGEN_ATTR_ENTRY): 'value' now unsigned.
340 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
341 * cgen-bitset.h: New file.
343 2005-09-30 Catherine Moore <clm@cm00re.com>
347 2005-10-24 Jan Beulich <jbeulich@novell.com>
349 * ia64.h (enum ia64_opnd): Move memory operand out of set of
352 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
354 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
355 Add FLAG_STRICT to pa10 ftest opcode.
357 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
359 * hppa.h (pa_opcodes): Remove lha entries.
361 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
363 * hppa.h (FLAG_STRICT): Revise comment.
364 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
365 before corresponding pa11 opcodes. Add strict pa10 register-immediate
368 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
370 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
372 2005-09-06 Chao-ying Fu <fu@mips.com>
374 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
375 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
377 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
378 (INSN_ASE_MASK): Update to include INSN_MT.
379 (INSN_MT): New define for MT ASE.
381 2005-08-25 Chao-ying Fu <fu@mips.com>
383 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
384 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
385 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
386 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
387 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
388 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
390 (INSN_DSP): New define for DSP ASE.
392 2005-08-18 Alan Modra <amodra@bigpond.net.au>
396 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
398 * ppc.h (PPC_OPCODE_E300): Define.
400 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
402 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
404 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
407 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
410 2005-07-27 Jan Beulich <jbeulich@novell.com>
412 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
413 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
414 Add movq-s as 64-bit variants of movd-s.
416 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
418 * hppa.h: Fix punctuation in comment.
420 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
421 implicit space-register addressing. Set space-register bits on opcodes
422 using implicit space-register addressing. Add various missing pa20
423 long-immediate opcodes. Remove various opcodes using implicit 3-bit
424 space-register addressing. Use "fE" instead of "fe" in various
427 2005-07-18 Jan Beulich <jbeulich@novell.com>
429 * i386.h (i386_optab): Operands of aam and aad are unsigned.
431 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
433 * i386.h (i386_optab): Support Intel VMX Instructions.
435 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
437 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
439 2005-07-05 Jan Beulich <jbeulich@novell.com>
441 * i386.h (i386_optab): Add new insns.
443 2005-07-01 Nick Clifton <nickc@redhat.com>
445 * sparc.h: Add typedefs to structure declarations.
447 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
450 * i386.h (i386_optab): Update comments for 64bit addressing on
451 mov. Allow 64bit addressing for mov and movq.
453 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
455 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
456 respectively, in various floating-point load and store patterns.
458 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
460 * hppa.h (FLAG_STRICT): Correct comment.
461 (pa_opcodes): Update load and store entries to allow both PA 1.X and
462 PA 2.0 mneumonics when equivalent. Entries with cache control
463 completers now require PA 1.1. Adjust whitespace.
465 2005-05-19 Anton Blanchard <anton@samba.org>
467 * ppc.h (PPC_OPCODE_POWER5): Define.
469 2005-05-10 Nick Clifton <nickc@redhat.com>
471 * Update the address and phone number of the FSF organization in
472 the GPL notices in the following files:
473 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
474 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
475 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
476 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
477 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
478 tic54x.h, tic80.h, v850.h, vax.h
480 2005-05-09 Jan Beulich <jbeulich@novell.com>
482 * i386.h (i386_optab): Add ht and hnt.
484 2005-04-18 Mark Kettenis <kettenis@gnu.org>
486 * i386.h: Insert hyphens into selected VIA PadLock extensions.
487 Add xcrypt-ctr. Provide aliases without hyphens.
489 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
491 Moved from ../ChangeLog
493 2005-04-12 Paul Brook <paul@codesourcery.com>
494 * m88k.h: Rename psr macros to avoid conflicts.
496 2005-03-12 Zack Weinberg <zack@codesourcery.com>
497 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
498 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
501 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
502 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
503 Remove redundant instruction types.
504 (struct argument): X_op - new field.
505 (struct cst4_entry): Remove.
506 (no_op_insn): Declare.
508 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
509 * crx.h (enum argtype): Rename types, remove unused types.
511 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
512 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
513 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
514 (enum operand_type): Rearrange operands, edit comments.
515 replace us<N> with ui<N> for unsigned immediate.
516 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
517 displacements (respectively).
518 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
519 (instruction type): Add NO_TYPE_INS.
520 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
521 (operand_entry): New field - 'flags'.
522 (operand flags): New.
524 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
525 * crx.h (operand_type): Remove redundant types i3, i4,
527 Add new unsigned immediate types us3, us4, us5, us16.
529 2005-04-12 Mark Kettenis <kettenis@gnu.org>
531 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
532 adjust them accordingly.
534 2005-04-01 Jan Beulich <jbeulich@novell.com>
536 * i386.h (i386_optab): Add rdtscp.
538 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
540 * i386.h (i386_optab): Don't allow the `l' suffix for moving
541 between memory and segment register. Allow movq for moving between
542 general-purpose register and segment register.
544 2005-02-09 Jan Beulich <jbeulich@novell.com>
547 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
548 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
551 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
553 * m68k.h (m68008, m68ec030, m68882): Remove.
555 (cpu_m68k, cpu_cf): New.
556 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
557 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
559 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
561 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
562 * cgen.h (enum cgen_parse_operand_type): Add
563 CGEN_PARSE_OPERAND_SYMBOLIC.
565 2005-01-21 Fred Fish <fnf@specifixinc.com>
567 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
568 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
569 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
571 2005-01-19 Fred Fish <fnf@specifixinc.com>
573 * mips.h (struct mips_opcode): Add new pinfo2 member.
574 (INSN_ALIAS): New define for opcode table entries that are
575 specific instances of another entry, such as 'move' for an 'or'
577 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
578 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
580 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
582 * mips.h (CPU_RM9000): Define.
583 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
585 2004-11-25 Jan Beulich <jbeulich@novell.com>
587 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
588 to/from test registers are illegal in 64-bit mode. Add missing
589 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
590 (previously one had to explicitly encode a rex64 prefix). Re-enable
591 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
592 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
594 2004-11-23 Jan Beulich <jbeulich@novell.com>
596 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
597 available only with SSE2. Change the MMX additions introduced by SSE
598 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
599 instructions by their now designated identifier (since combining i686
600 and 3DNow! does not really imply 3DNow!A).
602 2004-11-19 Alan Modra <amodra@bigpond.net.au>
604 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
605 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
607 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
608 Vineet Sharma <vineets@noida.hcltech.com>
610 * maxq.h: New file: Disassembly information for the maxq port.
612 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
614 * i386.h (i386_optab): Put back "movzb".
616 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
618 * cris.h (enum cris_insn_version_usage): Tweak formatting and
619 comments. Remove member cris_ver_sim. Add members
620 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
621 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
622 (struct cris_support_reg, struct cris_cond15): New types.
623 (cris_conds15): Declare.
624 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
625 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
626 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
627 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
628 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
631 2004-11-04 Jan Beulich <jbeulich@novell.com>
633 * i386.h (sldx_Suf): Remove.
634 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
635 (q_FP): Define, implying no REX64.
636 (x_FP, sl_FP): Imply FloatMF.
637 (i386_optab): Split reg and mem forms of moving from segment registers
638 so that the memory forms can ignore the 16-/32-bit operand size
639 distinction. Adjust a few others for Intel mode. Remove *FP uses from
640 all non-floating-point instructions. Unite 32- and 64-bit forms of
641 movsx, movzx, and movd. Adjust floating point operations for the above
642 changes to the *FP macros. Add DefaultSize to floating point control
643 insns operating on larger memory ranges. Remove left over comments
644 hinting at certain insns being Intel-syntax ones where the ones
645 actually meant are already gone.
647 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
649 * crx.h: Add COPS_REG_INS - Coprocessor Special register
652 2004-09-30 Paul Brook <paul@codesourcery.com>
654 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
655 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
657 2004-09-11 Theodore A. Roth <troth@openavr.org>
659 * avr.h: Add support for
660 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
662 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
664 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
666 2004-08-24 Dmitry Diky <diwil@spec.ru>
668 * msp430.h (msp430_opc): Add new instructions.
669 (msp430_rcodes): Declare new instructions.
670 (msp430_hcodes): Likewise..
672 2004-08-13 Nick Clifton <nickc@redhat.com>
675 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
678 2004-08-30 Michal Ludvig <mludvig@suse.cz>
680 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
682 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
684 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
686 2004-07-21 Jan Beulich <jbeulich@novell.com>
688 * i386.h: Adjust instruction descriptions to better match the
691 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
693 * arm.h: Remove all old content. Replace with architecture defines
694 from gas/config/tc-arm.c.
696 2004-07-09 Andreas Schwab <schwab@suse.de>
698 * m68k.h: Fix comment.
700 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
704 2004-06-24 Alan Modra <amodra@bigpond.net.au>
706 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
708 2004-05-24 Peter Barada <peter@the-baradas.com>
710 * m68k.h: Add 'size' to m68k_opcode.
712 2004-05-05 Peter Barada <peter@the-baradas.com>
714 * m68k.h: Switch from ColdFire chip name to core variant.
716 2004-04-22 Peter Barada <peter@the-baradas.com>
718 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
719 descriptions for new EMAC cases.
720 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
721 handle Motorola MAC syntax.
722 Allow disassembly of ColdFire V4e object files.
724 2004-03-16 Alan Modra <amodra@bigpond.net.au>
726 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
728 2004-03-12 Jakub Jelinek <jakub@redhat.com>
730 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
732 2004-03-12 Michal Ludvig <mludvig@suse.cz>
734 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
736 2004-03-12 Michal Ludvig <mludvig@suse.cz>
738 * i386.h (i386_optab): Added xstore/xcrypt insns.
740 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
742 * h8300.h (32bit ldc/stc): Add relaxing support.
744 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
746 * h8300.h (BITOP): Pass MEMRELAX flag.
748 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
750 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
753 For older changes see ChangeLog-9103
759 version-control: never