include/opcode/ChangeLog

   1 2013-01-24  Nick Clifton  <nickc@redhat.com>
   2
   3         * v850.h: Add e3v5 support.
   4
   5 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
   6
   7         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
   8
   9 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  10
  11         * ppc.h (PPC_OPCODE_POWER8): New define.
  12         (PPC_OPCODE_HTM): Likewise.
  13
  14 2013-01-10  Will Newton <will.newton@imgtec.com>
  15
  16         * metag.h: New file.
  17
  18 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  19
  20         * cr16.h (make_instruction): Rename to cr16_make_instruction.
  21         (match_opcode): Rename to cr16_match_opcode.
  22
  23 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
  24
  25         * mips.h: Add support for r5900 instructions including lq and sq.
  26
  27 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  28
  29         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
  30         (make_instruction,match_opcode): Added function prototypes.
  31         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
  32
  33 2012-11-23  Alan Modra  <amodra@gmail.com>
  34
  35         * ppc.h (ppc_parse_cpu): Update prototype.
  36
  37 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  38
  39         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
  40         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
  41
  42 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  43
  44         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
  45
  46 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
  47
  48         * ia64.h (ia64_opnd): Add new operand types.
  49
  50 2012-08-21  David S. Miller  <davem@davemloft.net>
  51
  52         * sparc.h (F3F4): New macro.
  53
  54 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
  55             Laurent Desnogues  <laurent.desnogues@arm.com>
  56             Jim MacArthur  <jim.macarthur@arm.com>
  57             Marcus Shawcroft  <marcus.shawcroft@arm.com>
  58             Nigel Stephens  <nigel.stephens@arm.com>
  59             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  60             Richard Earnshaw  <rearnsha@arm.com>
  61             Sofiane Naci  <sofiane.naci@arm.com>
  62             Tejas Belagod  <tejas.belagod@arm.com>
  63             Yufeng Zhang  <yufeng.zhang@arm.com>
  64
  65         * aarch64.h: New file.
  66
  67 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
  68             Maciej W. Rozycki  <macro@codesourcery.com>
  69
  70         * mips.h (mips_opcode): Add the exclusions field.
  71         (OPCODE_IS_MEMBER): Remove macro.
  72         (cpu_is_member): New inline function.
  73         (opcode_is_member): Likewise.
  74
  75 2012-07-31  Chao-Ying Fu  <fu@mips.com>
  76             Catherine Moore  <clm@codesourcery.com>
  77             Maciej W. Rozycki  <macro@codesourcery.com>
  78
  79         * mips.h: Document microMIPS DSP ASE usage.
  80         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
  81         microMIPS DSP ASE support.
  82         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
  83         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
  84         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
  85         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
  86         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
  87         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
  88         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
  89
  90 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
  91
  92         * mips.h: Fix a typo in description.
  93
  94 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
  95
  96         * avr.h: (AVR_ISA_XCH): New define.
  97         (AVR_ISA_XMEGA): Use it.
  98         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
  99
 100 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 101
 102         * m68hc11.h: Add XGate definitions.
 103         (struct m68hc11_opcode): Add xg_mask field.
 104
 105 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 106             Maciej W. Rozycki  <macro@codesourcery.com>
 107             Rhonda Wittels  <rhonda@codesourcery.com>
 108
 109         * ppc.h (PPC_OPCODE_VLE): New definition.
 110         (PPC_OP_SA): New macro.
 111         (PPC_OP_SE_VLE): New macro.
 112         (PPC_OP): Use a variable shift amount.
 113         (powerpc_operand): Update comments.
 114         (PPC_OPSHIFT_INV): New macro.
 115         (PPC_OPERAND_CR): Replace with...
 116         (PPC_OPERAND_CR_BIT): ...this and
 117         (PPC_OPERAND_CR_REG): ...this.
 118
 119
 120 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 121
 122         * xgate.h: Header file for XGATE assembler.
 123
 124 2012-04-27  David S. Miller  <davem@davemloft.net>
 125
 126         * sparc.h: Document new arg code' )' for crypto RS3
 127         immediates.
 128
 129         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 130         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 131         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 132         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 133         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 134         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 135         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 136         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 137         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 138         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 139         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 140
 141 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 142
 143         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 144
 145 2012-02-27  Alan Modra  <amodra@gmail.com>
 146
 147         * crx.h (cst4_map): Update declaration.
 148
 149 2012-02-25  Walter Lee  <walt@tilera.com>
 150
 151         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 152         TILEGX_OPC_LD_TLS.
 153         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 154         TILEPRO_OPC_LW_TLS_SN.
 155
 156 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 159         (XRELEASE_PREFIX_OPCODE): Likewise.
 160
 161 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 162             Adam Nemet  <anemet@caviumnetworks.com>
 163
 164         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 165         (INSN_OCTEON2): New macro.
 166         (CPU_OCTEON2): New macro.
 167         (OPCODE_IS_MEMBER): Add Octeon2.
 168
 169 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 170
 171         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 172         (INSN_OCTEONP): New macro.
 173         (CPU_OCTEONP): New macro.
 174         (OPCODE_IS_MEMBER): Add Octeon+.
 175         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 176
 177 2011-11-01  DJ Delorie  <dj@redhat.com>
 178
 179         * rl78.h: New file.
 180
 181 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 182
 183         * mips.h: Fix a typo in description.
 184
 185 2011-09-21  David S. Miller  <davem@davemloft.net>
 186
 187         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 188         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 189         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 190         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 191
 192 2011-08-09  Chao-ying Fu  <fu@mips.com>
 193             Maciej W. Rozycki  <macro@codesourcery.com>
 194
 195         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 196         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 197         (INSN_ASE_MASK): Add the MCU bit.
 198         (INSN_MCU): New macro.
 199         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 200         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 201
 202 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 203
 204         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 205         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 206         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 207         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 208         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 209         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 210         (INSN2_READ_GPR_MMN): Likewise.
 211         (INSN2_READ_FPR_D): Change the bit used.
 212         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 213         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 214         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 215         (INSN2_COND_BRANCH): Likewise.
 216         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 217         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 218         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 219         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 220         (INSN2_MOD_GPR_MN): Likewise.
 221
 222 2011-08-05  David S. Miller  <davem@davemloft.net>
 223
 224         * sparc.h: Document new format codes '4', '5', and '('.
 225         (OPF_LOW4, RS3): New macros.
 226
 227 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 228
 229         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 230         order of flags documented.
 231
 232 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 233
 234         * mips.h: Clarify the description of microMIPS instruction
 235         manipulation macros.
 236         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 237
 238 2011-07-24  Chao-ying Fu  <fu@mips.com>
 239             Maciej W. Rozycki  <macro@codesourcery.com>
 240
 241         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 242         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 243         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 244         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 245         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 246         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 247         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 248         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 249         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 250         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 251         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 252         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 253         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 254         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 255         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 256         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 257         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 258         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 259         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 260         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 261         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 262         (INSN_WRITE_GPR_S): New macro.
 263         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 264         (INSN2_READ_FPR_D): Likewise.
 265         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 266         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 267         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 268         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 269         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 270         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 271         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 272         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 273         (CPU_MICROMIPS): New macro.
 274         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 275         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 276         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 277         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 278         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 279         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 280         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 281         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 282         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 283         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 284         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 285         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 286         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 287         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 288         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 289         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 290         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 291         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 292         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 293         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 294         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 295         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 296         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 297         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 298         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 299         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 300         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 301         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 302         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 303         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 304         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 305         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 306         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 307         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 308         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 309         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 310         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 311         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 312         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 313         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 314         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 315         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 316         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 317         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 318         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 319         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 320         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 321         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 322         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 323         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 324         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 325         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 326         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 327         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 328         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 329         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 330         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 331         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 332         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 333         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 334         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 335         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 336         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 337         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 338         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 339         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 340         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 341         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 342         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 343         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 344         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 345         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 346         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 347         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 348         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 349         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 350         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 351         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 352         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 353         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 354         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 355         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 356         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 357         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 358         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 359         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 360         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 361         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 362         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 363         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 364         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 365         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 366         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 367         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 368         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 369         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 370         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 371         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 372         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 373         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 374         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 375         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 376         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 377         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 378         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 379         (micromips_opcodes): New declaration.
 380         (bfd_micromips_num_opcodes): Likewise.
 381
 382 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 383
 384         * mips.h (INSN_TRAP): Rename to...
 385         (INSN_NO_DELAY_SLOT): ... this.
 386         (INSN_SYNC): Remove macro.
 387
 388 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 389
 390         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 391         a duplicate of AVR_ISA_SPM.
 392
 393 2011-07-01  Nick Clifton  <nickc@redhat.com>
 394
 395         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 396
 397 2011-06-18  Robin Getz  <robin.getz@analog.com>
 398
 399         * bfin.h (is_macmod_signed): New func
 400
 401 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 402
 403         * bfin.h (is_macmod_pmove): Add missing space before func args.
 404         (is_macmod_hmove): Likewise.
 405
 406 2011-06-13  Walter Lee  <walt@tilera.com>
 407
 408         * tilegx.h: New file.
 409         * tilepro.h: New file.
 410
 411 2011-05-31  Paul Brook  <paul@codesourcery.com>
 412
 413         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 414
 415 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 416
 417         * s390.h: Replace S390_OPERAND_REG_EVEN with
 418         S390_OPERAND_REG_PAIR.
 419
 420 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 421
 422         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 423
 424 2011-04-18  Julian Brown  <julian@codesourcery.com>
 425
 426         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 427
 428 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 429
 430         PR gas/12296
 431         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 432
 433 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 434
 435         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 436         New instruction set flags.
 437         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 438
 439 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 440
 441         * mips.h (M_PREF_AB): New enum value.
 442
 443 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 444
 445         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 446         M_IU): Define.
 447         (is_macmod_pmove, is_macmod_hmove): New functions.
 448
 449 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 450
 451         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 452
 453 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 454
 455         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 456         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 457
 458 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 459
 460         PR gas/11395
 461         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 462         "bb" entries.
 463
 464 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 465
 466         PR gas/11395
 467         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 468
 469 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 470
 471         * mips.h: Update commentary after last commit.
 472
 473 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 474
 475         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 476         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 477         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 478
 479 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 480
 481         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 482
 483 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 484
 485         * mips.h: Fix previous commit.
 486
 487 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 488
 489         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 490         (INSN_LOONGSON_3A): Clear bit 31.
 491
 492 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 493
 494         PR gas/12198
 495         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 496         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 497         (ARM_ARCH_V6M_ONLY): New define.
 498
 499 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 500
 501         * mips.h (INSN_LOONGSON_3A): Defined.
 502         (CPU_LOONGSON_3A): Defined.
 503         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 504
 505 2010-10-09  Matt Rice  <ratmice@gmail.com>
 506
 507         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 508         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 509
 510 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 511
 512         * arm.h (ARM_EXT_VIRT): New define.
 513         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 514         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 515         Extensions.
 516
 517 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 518
 519         * arm.h (ARM_AEXT_ADIV): New define.
 520         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 521
 522 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 523
 524         * arm.h (ARM_EXT_OS): New define.
 525         (ARM_AEXT_V6SM): Likewise.
 526         (ARM_ARCH_V6SM): Likewise.
 527
 528 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 529
 530         * arm.h (ARM_EXT_MP): Add.
 531         (ARM_ARCH_V7A_MP): Likewise.
 532
 533 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 534
 535         * bfin.h: Declare pseudoChr structs/defines.
 536
 537 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 538
 539         * bfin.h: Strip trailing whitespace.
 540
 541 2010-07-29  DJ Delorie  <dj@redhat.com>
 542
 543         * rx.h (RX_Operand_Type): Add TwoReg.
 544         (RX_Opcode_ID): Remove ediv and ediv2.
 545
 546 2010-07-27  DJ Delorie  <dj@redhat.com>
 547
 548         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 549
 550 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 551             Ina Pandit  <ina.pandit@kpitcummins.com>
 552
 553         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 554         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 555         PROCESSOR_V850E2_ALL.
 556         Remove PROCESSOR_V850EA support.
 557         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 558         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 559         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 560         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 561         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 562         V850_OPERAND_PERCENT.
 563         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 564         V850_NOT_R0.
 565         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 566         and V850E_PUSH_POP
 567
 568 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 569
 570         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 571         (MIPS16_INSN_BRANCH): Rename to...
 572         (MIPS16_INSN_COND_BRANCH): ... this.
 573
 574 2010-07-03  Alan Modra  <amodra@gmail.com>
 575
 576         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 577         Renumber other PPC_OPCODE defines.
 578
 579 2010-07-03  Alan Modra  <amodra@gmail.com>
 580
 581         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 582
 583 2010-06-29  Alan Modra  <amodra@gmail.com>
 584
 585         * maxq.h: Delete file.
 586
 587 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 588
 589         * ppc.h (PPC_OPCODE_E500): Define.
 590
 591 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 592
 593         * opcode/mips.h (INSN_MIPS16): Remove.
 594
 595 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 596
 597         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 598
 599 2010-04-15  Nick Clifton  <nickc@redhat.com>
 600
 601         * alpha.h: Update copyright notice to use GPLv3.
 602         * arc.h: Likewise.
 603         * arm.h: Likewise.
 604         * avr.h: Likewise.
 605         * bfin.h: Likewise.
 606         * cgen.h: Likewise.
 607         * convex.h: Likewise.
 608         * cr16.h: Likewise.
 609         * cris.h: Likewise.
 610         * crx.h: Likewise.
 611         * d10v.h: Likewise.
 612         * d30v.h: Likewise.
 613         * dlx.h: Likewise.
 614         * h8300.h: Likewise.
 615         * hppa.h: Likewise.
 616         * i370.h: Likewise.
 617         * i386.h: Likewise.
 618         * i860.h: Likewise.
 619         * i960.h: Likewise.
 620         * ia64.h: Likewise.
 621         * m68hc11.h: Likewise.
 622         * m68k.h: Likewise.
 623         * m88k.h: Likewise.
 624         * maxq.h: Likewise.
 625         * mips.h: Likewise.
 626         * mmix.h: Likewise.
 627         * mn10200.h: Likewise.
 628         * mn10300.h: Likewise.
 629         * msp430.h: Likewise.
 630         * np1.h: Likewise.
 631         * ns32k.h: Likewise.
 632         * or32.h: Likewise.
 633         * pdp11.h: Likewise.
 634         * pj.h: Likewise.
 635         * pn.h: Likewise.
 636         * ppc.h: Likewise.
 637         * pyr.h: Likewise.
 638         * rx.h: Likewise.
 639         * s390.h: Likewise.
 640         * score-datadep.h: Likewise.
 641         * score-inst.h: Likewise.
 642         * sparc.h: Likewise.
 643         * spu-insns.h: Likewise.
 644         * spu.h: Likewise.
 645         * tic30.h: Likewise.
 646         * tic4x.h: Likewise.
 647         * tic54x.h: Likewise.
 648         * tic80.h: Likewise.
 649         * v850.h: Likewise.
 650         * vax.h: Likewise.
 651
 652 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 653
 654         * tic6x-control-registers.h, tic6x-insn-formats.h,
 655         tic6x-opcode-table.h, tic6x.h: New.
 656
 657 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 658
 659         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 660
 661 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 662
 663         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 664
 665 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 666
 667         * ia64.h (ia64_find_opcode): Remove argument name.
 668         (ia64_find_next_opcode): Likewise.
 669         (ia64_dis_opcode): Likewise.
 670         (ia64_free_opcode): Likewise.
 671         (ia64_find_dependency): Likewise.
 672
 673 2009-11-22  Doug Evans  <dje@sebabeach.org>
 674
 675         * cgen.h: Include bfd_stdint.h.
 676         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 677
 678 2009-11-18  Paul Brook  <paul@codesourcery.com>
 679
 680         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 681
 682 2009-11-17  Paul Brook  <paul@codesourcery.com>
 683         Daniel Jacobowitz  <dan@codesourcery.com>
 684
 685         * arm.h (ARM_EXT_V6_DSP): Define.
 686         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 687         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 688
 689 2009-11-04  DJ Delorie  <dj@redhat.com>
 690
 691         * rx.h (rx_decode_opcode) (mvtipl): Add.
 692         (mvtcp, mvfcp, opecp): Remove.
 693
 694 2009-11-02  Paul Brook  <paul@codesourcery.com>
 695
 696         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 697         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 698         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 699         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 700         FPU_ARCH_NEON_VFP_V4): Define.
 701
 702 2009-10-23  Doug Evans  <dje@sebabeach.org>
 703
 704         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 705         * cgen.h: Update.  Improve multi-inclusion macro name.
 706
 707 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 708
 709         * ppc.h (PPC_OPCODE_476): Define.
 710
 711 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 712
 713         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 714
 715 2009-09-29  DJ Delorie  <dj@redhat.com>
 716
 717         * rx.h: New file.
 718
 719 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 720
 721         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 722
 723 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 724
 725         * ppc.h (PPC_OPCODE_PPCA2): New.
 726
 727 2009-09-05  Martin Thuresson  <martin@mtme.org>
 728
 729         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 730
 731 2009-08-29  Martin Thuresson  <martin@mtme.org>
 732
 733         * tic30.h (template): Rename type template to
 734         insn_template. Updated code to use new name.
 735         * tic54x.h (template): Rename type template to
 736         insn_template.
 737
 738 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 739
 740         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 741
 742 2009-06-11  Anthony Green  <green@moxielogic.com>
 743
 744         * moxie.h (MOXIE_F3_PCREL): Define.
 745         (moxie_form3_opc_info): Grow.
 746
 747 2009-06-06  Anthony Green  <green@moxielogic.com>
 748
 749         * moxie.h (MOXIE_F1_M): Define.
 750
 751 2009-04-15  Anthony Green  <green@moxielogic.com>
 752
 753         * moxie.h: Created.
 754
 755 2009-04-06  DJ Delorie  <dj@redhat.com>
 756
 757         * h8300.h: Add relaxation attributes to MOVA opcodes.
 758
 759 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 760
 761         * ppc.h (ppc_parse_cpu): Declare.
 762
 763 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 764
 765         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 766         and _IMM11 for mbitclr and mbitset.
 767         * score-datadep.h: Update dependency information.
 768
 769 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 770
 771         * ppc.h (PPC_OPCODE_POWER7): New.
 772
 773 2009-02-06  Doug Evans  <dje@google.com>
 774
 775         * i386.h: Add comment regarding sse* insns and prefixes.
 776
 777 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 778
 779         * mips.h (INSN_XLR): Define.
 780         (INSN_CHIP_MASK): Update.
 781         (CPU_XLR): Define.
 782         (OPCODE_IS_MEMBER): Update.
 783         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 784
 785 2009-01-28  Doug Evans  <dje@google.com>
 786
 787         * opcode/i386.h: Add multiple inclusion protection.
 788         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 789         (EDI_REG_NUM): New macros.
 790         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 791         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 792         (REX_PREFIX_P): New macro.
 793
 794 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 795
 796         * ppc.h (struct powerpc_opcode): New field "deprecated".
 797         (PPC_OPCODE_NOPOWER4): Delete.
 798
 799 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 800
 801         * mips.h: Define CPU_R14000, CPU_R16000.
 802         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 803
 804 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 805
 806         * arm.h (FPU_NEON_FP16): New.
 807         (FPU_ARCH_NEON_FP16): New.
 808
 809 2008-11-06  Chao-ying Fu  <fu@mips.com>
 810
 811         * mips.h: Doucument '1' for 5-bit sync type.
 812
 813 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 814
 815         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 816         IA64_RS_CR.
 817
 818 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 819
 820         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 821
 822 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 823
 824         * ppc.h (PPC_OPCODE_405): Define.
 825         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 826
 827 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 828
 829         * ppc.h (ppc_cpu_t): New typedef.
 830         (struct powerpc_opcode <flags>): Use it.
 831         (struct powerpc_operand <insert, extract>): Likewise.
 832         (struct powerpc_macro <flags>): Likewise.
 833
 834 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 835
 836         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 837         Update comment before MIPS16 field descriptors to mention MIPS16.
 838         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 839         BBIT.
 840         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 841         New bit masks and shift counts for cins and exts.
 842
 843         * mips.h: Document new field descriptors +Q.
 844         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 845
 846 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 847
 848         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 849         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 850
 851 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 852
 853         * ppc.h: (PPC_OPCODE_E500MC): New.
 854
 855 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         * i386.h (MAX_OPERANDS): Set to 5.
 858         (MAX_MNEM_SIZE): Changed to 20.
 859
 860 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 861
 862         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 863
 864 2008-03-09  Paul Brook  <paul@codesourcery.com>
 865
 866         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 867
 868 2008-03-04  Paul Brook  <paul@codesourcery.com>
 869
 870         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 871         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 872         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 873
 874 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 875             Nick Clifton  <nickc@redhat.com>
 876
 877         PR 3134
 878         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 879         with a 32-bit displacement but without the top bit of the 4th byte
 880         set.
 881
 882 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 883
 884         * cr16.h (cr16_num_optab): Declared.
 885
 886 2008-02-14  Hakan Ardo  <hakan@debian.org>
 887
 888         PR gas/2626
 889         * avr.h (AVR_ISA_2xxe): Define.
 890
 891 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 892
 893         * mips.h: Update copyright.
 894         (INSN_CHIP_MASK): New macro.
 895         (INSN_OCTEON): New macro.
 896         (CPU_OCTEON): New macro.
 897         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 898
 899 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 900
 901         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 902
 903 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 904
 905         * avr.h (AVR_ISA_USB162): Add new opcode set.
 906         (AVR_ISA_AVR3): Likewise.
 907
 908 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 909
 910         * mips.h (INSN_LOONGSON_2E): New.
 911         (INSN_LOONGSON_2F): New.
 912         (CPU_LOONGSON_2E): New.
 913         (CPU_LOONGSON_2F): New.
 914         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 915
 916 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 917
 918         * mips.h (INSN_ISA*): Redefine certain values as an
 919         enumeration.  Update comments.
 920         (mips_isa_table): New.
 921         (ISA_MIPS*): Redefine to match enumeration.
 922         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 923         values.
 924
 925 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 926
 927         * ppc.h (PPC_OPCODE_PPCPS): New.
 928
 929 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 930
 931         * m68k.h: Document j K & E.
 932
 933 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 934
 935         * cr16.h: New file for CR16 target.
 936
 937 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 938
 939         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 940
 941 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 942
 943         * m68k.h (mcfisa_c): New.
 944         (mcfusp, mcf_mask): Adjust.
 945
 946 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 947
 948         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 949         (num_powerpc_operands): Declare.
 950         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 951         (PPC_OPERAND_PLUS1): Define.
 952
 953 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         * i386.h (REX_MODE64): Renamed to ...
 956         (REX_W): This.
 957         (REX_EXTX): Renamed to ...
 958         (REX_R): This.
 959         (REX_EXTY): Renamed to ...
 960         (REX_X): This.
 961         (REX_EXTZ): Renamed to ...
 962         (REX_B): This.
 963
 964 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         * i386.h: Add entries from config/tc-i386.h and move tables
 967         to opcodes/i386-opc.h.
 968
 969 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 970
 971         * i386.h (FloatDR): Removed.
 972         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 973
 974 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 975
 976         * spu-insns.h: Add soma double-float insns.
 977
 978 2007-02-20  Thiemo Seufer  <ths@mips.com>
 979             Chao-Ying Fu  <fu@mips.com>
 980
 981         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 982         (INSN_DSPR2): Add flag for DSP R2 instructions.
 983         (M_BALIGN): New macro.
 984
 985 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 986
 987         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 988         and Seg3ShortFrom with Shortform.
 989
 990 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 991
 992         PR gas/4027
 993         * i386.h (i386_optab): Put the real "test" before the pseudo
 994         one.
 995
 996 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 997
 998         * m68k.h (m68010up): OR fido_a.
 999
1000 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1001
1002         * m68k.h (fido_a): New.
1003
1004 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1005
1006         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1007         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1008         values.
1009
1010 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1011
1012         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1013
1014 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1015
1016         * score-inst.h (enum score_insn_type): Add Insn_internal.
1017
1018 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1019             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1020             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1021             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1022             Alan Modra  <amodra@bigpond.net.au>
1023
1024         * spu-insns.h: New file.
1025         * spu.h: New file.
1026
1027 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1028
1029         * ppc.h (PPC_OPCODE_CELL): Define.
1030
1031 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1032
1033         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1034         in amdfam10 architecture.
1035
1036 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1037
1038         * i386.h: Replace CpuMNI with CpuSSSE3.
1039
1040 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1041             Joseph Myers  <joseph@codesourcery.com>
1042             Ian Lance Taylor  <ian@wasabisystems.com>
1043             Ben Elliston  <bje@wasabisystems.com>
1044
1045         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1046
1047 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1048
1049         * score-datadep.h: New file.
1050         * score-inst.h: New file.
1051
1052 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1053
1054         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1055         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1056         movdq2q and movq2dq.
1057
1058 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1059            Michael Meissner             <michael.meissner@amd.com>
1060
1061         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1062
1063 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1064
1065         * i386.h (i386_optab): Add "nop" with memory reference.
1066
1067 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1068
1069         * i386.h (i386_optab): Update comment for 64bit NOP.
1070
1071 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1072             Anton Blanchard  <anton@samba.org>
1073
1074         * ppc.h (PPC_OPCODE_POWER6): Define.
1075         Adjust whitespace.
1076
1077 2006-06-05  Thiemo Seufer  <ths@mips.com>
1078
1079         * mips.h: Improve description of MT flags.
1080
1081 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1082
1083         * m68k.h (mcf_mask): Define.
1084
1085 2006-05-05  Thiemo Seufer  <ths@mips.com>
1086             David Ung  <davidu@mips.com>
1087
1088         * mips.h (enum): Add macro M_CACHE_AB.
1089
1090 2006-05-04  Thiemo Seufer  <ths@mips.com>
1091             Nigel Stephens  <nigel@mips.com>
1092             David Ung  <davidu@mips.com>
1093
1094         * mips.h: Add INSN_SMARTMIPS define.
1095
1096 2006-04-30  Thiemo Seufer  <ths@mips.com>
1097             David Ung  <davidu@mips.com>
1098
1099         * mips.h: Defines udi bits and masks.  Add description of
1100         characters which may appear in the args field of udi
1101         instructions.
1102
1103 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1104
1105         * mips.h: Improve comments describing the bitfield instruction
1106         fields.
1107
1108 2006-04-26  Julian Brown  <julian@codesourcery.com>
1109
1110         * arm.h (FPU_VFP_EXT_V3): Define constant.
1111         (FPU_NEON_EXT_V1): Likewise.
1112         (FPU_VFP_HARD): Update.
1113         (FPU_VFP_V3): Define macro.
1114         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1115
1116 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1117
1118         * avr.h (AVR_ISA_PWMx): New.
1119
1120 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1121
1122         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1123         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1124         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1125         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1126         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1127
1128 2006-03-10  Paul Brook  <paul@codesourcery.com>
1129
1130         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1131
1132 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1133
1134         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1135         first.  Correct mask of bb "B" opcode.
1136
1137 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1138
1139         * i386.h (i386_optab): Support Intel Merom New Instructions.
1140
1141 2006-02-24  Paul Brook  <paul@codesourcery.com>
1142
1143         * arm.h: Add V7 feature bits.
1144
1145 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1148
1149 2006-01-31  Paul Brook  <paul@codesourcery.com>
1150         Richard Earnshaw <rearnsha@arm.com>
1151
1152         * arm.h: Use ARM_CPU_FEATURE.
1153         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1154         (arm_feature_set): Change to a structure.
1155         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1156         ARM_FEATURE): New macros.
1157
1158 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1159
1160         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1161         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1162         (ADD_PC_INCR_OPCODE): Don't define.
1163
1164 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1165
1166         PR gas/1874
1167         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1168
1169 2005-11-14  David Ung  <davidu@mips.com>
1170
1171         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1172         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1173         save/restore encoding of the args field.
1174
1175 2005-10-28  Dave Brolley  <brolley@redhat.com>
1176
1177         Contribute the following changes:
1178         2005-02-16  Dave Brolley  <brolley@redhat.com>
1179
1180         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1181         cgen_isa_mask_* to cgen_bitset_*.
1182         * cgen.h: Likewise.
1183
1184         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1185
1186         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1187         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1188         (CGEN_CPU_TABLE): Make isas a ponter.
1189
1190         2003-09-29  Dave Brolley  <brolley@redhat.com>
1191
1192         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1193         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1194         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1195
1196         2002-12-13  Dave Brolley  <brolley@redhat.com>
1197
1198         * cgen.h (symcat.h): #include it.
1199         (cgen-bitset.h): #include it.
1200         (CGEN_ATTR_VALUE_TYPE): Now a union.
1201         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1202         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1203         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1204         * cgen-bitset.h: New file.
1205
1206 2005-09-30  Catherine Moore  <clm@cm00re.com>
1207
1208         * bfin.h: New file.
1209
1210 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1211
1212         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1213         indirect operands.
1214
1215 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1216
1217         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1218         Add FLAG_STRICT to pa10 ftest opcode.
1219
1220 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1221
1222         * hppa.h (pa_opcodes): Remove lha entries.
1223
1224 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1225
1226         * hppa.h (FLAG_STRICT): Revise comment.
1227         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1228         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1229         entries for "fdc".
1230
1231 2005-09-30  Catherine Moore  <clm@cm00re.com>
1232
1233         * bfin.h: New file.
1234
1235 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1236
1237         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1238
1239 2005-09-06  Chao-ying Fu  <fu@mips.com>
1240
1241         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1242         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1243         define.
1244         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1245         (INSN_ASE_MASK): Update to include INSN_MT.
1246         (INSN_MT): New define for MT ASE.
1247
1248 2005-08-25  Chao-ying Fu  <fu@mips.com>
1249
1250         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1251         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1252         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1253         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1254         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1255         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1256         instructions.
1257         (INSN_DSP): New define for DSP ASE.
1258
1259 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1260
1261         * a29k.h: Delete.
1262
1263 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1264
1265         * ppc.h (PPC_OPCODE_E300): Define.
1266
1267 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1268
1269         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1270
1271 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1272
1273         PR gas/336
1274         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1275         and pitlb.
1276
1277 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1278
1279         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1280         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1281         Add movq-s as 64-bit variants of movd-s.
1282
1283 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1284
1285         * hppa.h: Fix punctuation in comment.
1286
1287         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1288         implicit space-register addressing.  Set space-register bits on opcodes
1289         using implicit space-register addressing.  Add various missing pa20
1290         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1291         space-register addressing.  Use "fE" instead of "fe" in various
1292         fstw opcodes.
1293
1294 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1295
1296         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1297
1298 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1299
1300         * i386.h (i386_optab): Support Intel VMX Instructions.
1301
1302 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1303
1304         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1305
1306 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1307
1308         * i386.h (i386_optab): Add new insns.
1309
1310 2005-07-01  Nick Clifton  <nickc@redhat.com>
1311
1312         * sparc.h: Add typedefs to structure declarations.
1313
1314 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1315
1316         PR 1013
1317         * i386.h (i386_optab): Update comments for 64bit addressing on
1318         mov. Allow 64bit addressing for mov and movq.
1319
1320 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1321
1322         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1323         respectively, in various floating-point load and store patterns.
1324
1325 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1326
1327         * hppa.h (FLAG_STRICT): Correct comment.
1328         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1329         PA 2.0 mneumonics when equivalent.  Entries with cache control
1330         completers now require PA 1.1.  Adjust whitespace.
1331
1332 2005-05-19  Anton Blanchard  <anton@samba.org>
1333
1334         * ppc.h (PPC_OPCODE_POWER5): Define.
1335
1336 2005-05-10  Nick Clifton  <nickc@redhat.com>
1337
1338         * Update the address and phone number of the FSF organization in
1339         the GPL notices in the following files:
1340         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1341         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1342         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1343         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1344         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1345         tic54x.h, tic80.h, v850.h, vax.h
1346
1347 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1348
1349         * i386.h (i386_optab): Add ht and hnt.
1350
1351 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1352
1353         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1354         Add xcrypt-ctr.  Provide aliases without hyphens.
1355
1356 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1357
1358         Moved from ../ChangeLog
1359
1360         2005-04-12  Paul Brook  <paul@codesourcery.com>
1361         * m88k.h: Rename psr macros to avoid conflicts.
1362
1363         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1364         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1365         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1366         and ARM_ARCH_V6ZKT2.
1367
1368         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1369         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1370         Remove redundant instruction types.
1371         (struct argument): X_op - new field.
1372         (struct cst4_entry): Remove.
1373         (no_op_insn): Declare.
1374
1375         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1376         * crx.h (enum argtype): Rename types, remove unused types.
1377
1378         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1379         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1380         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1381         (enum operand_type): Rearrange operands, edit comments.
1382         replace us<N> with ui<N> for unsigned immediate.
1383         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1384         displacements (respectively).
1385         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1386         (instruction type): Add NO_TYPE_INS.
1387         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1388         (operand_entry): New field - 'flags'.
1389         (operand flags): New.
1390
1391         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1392         * crx.h (operand_type): Remove redundant types i3, i4,
1393         i5, i8, i12.
1394         Add new unsigned immediate types us3, us4, us5, us16.
1395
1396 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1397
1398         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1399         adjust them accordingly.
1400
1401 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1402
1403         * i386.h (i386_optab): Add rdtscp.
1404
1405 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1406
1407         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1408         between memory and segment register. Allow movq for moving between
1409         general-purpose register and segment register.
1410
1411 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1412
1413         PR gas/707
1414         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1415         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1416         fnstsw.
1417
1418 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1419
1420         * m68k.h (m68008, m68ec030, m68882): Remove.
1421         (m68k_mask): New.
1422         (cpu_m68k, cpu_cf): New.
1423         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1424         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1425
1426 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1427
1428         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1429         * cgen.h (enum cgen_parse_operand_type): Add
1430         CGEN_PARSE_OPERAND_SYMBOLIC.
1431
1432 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1433
1434         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1435         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1436         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1437
1438 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1439
1440         * mips.h (struct mips_opcode): Add new pinfo2 member.
1441         (INSN_ALIAS): New define for opcode table entries that are
1442         specific instances of another entry, such as 'move' for an 'or'
1443         with a zero operand.
1444         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1445         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1446
1447 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1448
1449         * mips.h (CPU_RM9000): Define.
1450         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1451
1452 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1453
1454         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1455         to/from test registers are illegal in 64-bit mode. Add missing
1456         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1457         (previously one had to explicitly encode a rex64 prefix). Re-enable
1458         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1459         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1460
1461 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1462
1463         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1464         available only with SSE2. Change the MMX additions introduced by SSE
1465         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1466         instructions by their now designated identifier (since combining i686
1467         and 3DNow! does not really imply 3DNow!A).
1468
1469 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1470
1471         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1472         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1473
1474 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1475             Vineet Sharma      <vineets@noida.hcltech.com>
1476
1477         * maxq.h: New file: Disassembly information for the maxq port.
1478
1479 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1480
1481         * i386.h (i386_optab): Put back "movzb".
1482
1483 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1484
1485         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1486         comments.  Remove member cris_ver_sim.  Add members
1487         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1488         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1489         (struct cris_support_reg, struct cris_cond15): New types.
1490         (cris_conds15): Declare.
1491         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1492         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1493         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1494         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1495         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1496         SIZE_FIELD_UNSIGNED.
1497
1498 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1499
1500         * i386.h (sldx_Suf): Remove.
1501         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1502         (q_FP): Define, implying no REX64.
1503         (x_FP, sl_FP): Imply FloatMF.
1504         (i386_optab): Split reg and mem forms of moving from segment registers
1505         so that the memory forms can ignore the 16-/32-bit operand size
1506         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1507         all non-floating-point instructions. Unite 32- and 64-bit forms of
1508         movsx, movzx, and movd. Adjust floating point operations for the above
1509         changes to the *FP macros. Add DefaultSize to floating point control
1510         insns operating on larger memory ranges. Remove left over comments
1511         hinting at certain insns being Intel-syntax ones where the ones
1512         actually meant are already gone.
1513
1514 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1515
1516         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1517         instruction type.
1518
1519 2004-09-30  Paul Brook  <paul@codesourcery.com>
1520
1521         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1522         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1523
1524 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1525
1526         * avr.h: Add support for
1527         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1528
1529 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1530
1531         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1532
1533 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1534
1535         * msp430.h (msp430_opc): Add new instructions.
1536         (msp430_rcodes): Declare new instructions.
1537         (msp430_hcodes): Likewise..
1538
1539 2004-08-13  Nick Clifton  <nickc@redhat.com>
1540
1541         PR/301
1542         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1543         processors.
1544
1545 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1546
1547         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1548
1549 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1550
1551         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1552
1553 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1554
1555         * i386.h: Adjust instruction descriptions to better match the
1556         specification.
1557
1558 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1559
1560         * arm.h: Remove all old content.  Replace with architecture defines
1561         from gas/config/tc-arm.c.
1562
1563 2004-07-09  Andreas Schwab  <schwab@suse.de>
1564
1565         * m68k.h: Fix comment.
1566
1567 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1568
1569         * crx.h: New file.
1570
1571 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1572
1573         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1574
1575 2004-05-24  Peter Barada  <peter@the-baradas.com>
1576
1577         * m68k.h: Add 'size' to m68k_opcode.
1578
1579 2004-05-05  Peter Barada  <peter@the-baradas.com>
1580
1581         * m68k.h: Switch from ColdFire chip name to core variant.
1582
1583 2004-04-22  Peter Barada  <peter@the-baradas.com>
1584
1585         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1586         descriptions for new EMAC cases.
1587         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1588         handle Motorola MAC syntax.
1589         Allow disassembly of ColdFire V4e object files.
1590
1591 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1592
1593         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1594
1595 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1596
1597         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1598
1599 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1600
1601         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1602
1603 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1604
1605         * i386.h (i386_optab): Added xstore/xcrypt insns.
1606
1607 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1608
1609         * h8300.h (32bit ldc/stc): Add relaxing support.
1610
1611 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1612
1613         * h8300.h (BITOP): Pass MEMRELAX flag.
1614
1615 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1616
1617         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1618         except for the H8S.
1619
1620 For older changes see ChangeLog-9103
1621 \f
1622 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1623
1624 Copying and distribution of this file, with or without modification,
1625 are permitted in any medium without royalty provided the copyright
1626 notice and this notice are preserved.
1627
1628 Local Variables:
1629 mode: change-log
1630 left-margin: 8
1631 fill-column: 74
1632 version-control: never
1633 End: