1 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
4 (mips_operand, mips_int_operand, mips_mapped_int_operand)
5 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
6 (mips_pcrel_operand): New structures.
7 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
8 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
9 (decode_mips_operand, decode_micromips_operand): Declare.
11 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
13 * mips.h: Document MIPS16 "I" opcode.
15 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
17 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
18 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
19 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
20 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
21 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
22 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
23 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
24 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
25 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
26 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
27 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
28 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
29 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
31 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
34 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
36 * mips.h: Remove documentation of "[" and "]". Update documentation
37 of "k" and the MDMX formats.
39 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
41 * mips.h: Update documentation of "+s" and "+S".
43 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
45 * mips.h: Document "+i".
47 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
49 * mips.h: Remove "mi" documentation. Update "mh" documentation.
50 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
52 (INSN2_WRITE_GPR_MHI): Rename to...
53 (INSN2_WRITE_GPR_MH): ...this.
55 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
57 * mips.h: Remove documentation of "+D" and "+T".
59 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
61 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
62 Use "source" rather than "destination" for microMIPS "G".
64 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
66 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
69 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
71 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
73 2013-06-17 Catherine Moore <clm@codesourcery.com>
74 Maciej W. Rozycki <macro@codesourcery.com>
75 Chao-Ying Fu <fu@mips.com>
77 * mips.h (OP_SH_EVAOFFSET): Define.
78 (OP_MASK_EVAOFFSET): Define.
79 (INSN_ASE_MASK): Delete.
81 (M_CACHEE_AB, M_CACHEE_OB): New.
82 (M_LBE_OB, M_LBE_AB): New.
83 (M_LBUE_OB, M_LBUE_AB): New.
84 (M_LHE_OB, M_LHE_AB): New.
85 (M_LHUE_OB, M_LHUE_AB): New.
86 (M_LLE_AB, M_LLE_OB): New.
87 (M_LWE_OB, M_LWE_AB): New.
88 (M_LWLE_AB, M_LWLE_OB): New.
89 (M_LWRE_AB, M_LWRE_OB): New.
90 (M_PREFE_AB, M_PREFE_OB): New.
91 (M_SCE_AB, M_SCE_OB): New.
92 (M_SBE_OB, M_SBE_AB): New.
93 (M_SHE_OB, M_SHE_AB): New.
94 (M_SWE_OB, M_SWE_AB): New.
95 (M_SWLE_AB, M_SWLE_OB): New.
96 (M_SWRE_AB, M_SWRE_OB): New.
97 (MICROMIPSOP_SH_EVAOFFSET): Define.
98 (MICROMIPSOP_MASK_EVAOFFSET): Define.
100 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
102 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
104 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
106 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
108 2013-05-09 Andrew Pinski <apinski@cavium.com>
110 * mips.h (OP_MASK_CODE10): Correct definition.
111 (OP_SH_CODE10): Likewise.
112 Add a comment that "+J" is used now for OP_*CODE10.
113 (INSN_ASE_MASK): Update.
114 (INSN_VIRT): New macro.
115 (INSN_VIRT64): New macro
117 2013-05-02 Nick Clifton <nickc@redhat.com>
119 * msp430.h: Add patterns for MSP430X instructions.
121 2013-04-06 David S. Miller <davem@davemloft.net>
123 * sparc.h (F_PREFERRED): Define.
124 (F_PREF_ALIAS): Define.
126 2013-04-03 Nick Clifton <nickc@redhat.com>
128 * v850.h (V850_INVERSE_PCREL): Define.
130 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
133 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
135 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
138 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
140 * tic6xc-opcode-table.h: Add 16-bit insns.
141 * tic6x.h: Add support for 16-bit insns.
143 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
145 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
146 and mov.b/w/l Rs,@(d:32,ERd).
148 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
151 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
152 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
153 tic6x_operand_xregpair operand coding type.
154 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
155 opcode field, usu ORXREGD1324 for the src2 operand and remove the
158 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
161 * tic6x.h (enum tic6x_coding_method): Add
162 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
163 separately the msb and lsb of a register pair. This is needed to
164 encode the opcodes in the same way as TI assembler does.
165 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
166 and rsqrdp opcodes to use the new field coding types.
168 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
170 * arm.h (CRC_EXT_ARMV8): New constant.
171 (ARCH_CRC_ARMV8): New macro.
173 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
175 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
177 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
178 Andrew Jenner <andrew@codesourcery.com>
180 Based on patches from Altera Corporation.
184 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
186 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
188 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
191 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
193 2013-01-24 Nick Clifton <nickc@redhat.com>
195 * v850.h: Add e3v5 support.
197 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
199 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
201 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
203 * ppc.h (PPC_OPCODE_POWER8): New define.
204 (PPC_OPCODE_HTM): Likewise.
206 2013-01-10 Will Newton <will.newton@imgtec.com>
210 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
212 * cr16.h (make_instruction): Rename to cr16_make_instruction.
213 (match_opcode): Rename to cr16_match_opcode.
215 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
217 * mips.h: Add support for r5900 instructions including lq and sq.
219 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
221 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
222 (make_instruction,match_opcode): Added function prototypes.
223 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
225 2012-11-23 Alan Modra <amodra@gmail.com>
227 * ppc.h (ppc_parse_cpu): Update prototype.
229 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
231 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
232 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
234 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
236 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
238 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
240 * ia64.h (ia64_opnd): Add new operand types.
242 2012-08-21 David S. Miller <davem@davemloft.net>
244 * sparc.h (F3F4): New macro.
246 2012-08-13 Ian Bolton <ian.bolton@arm.com>
247 Laurent Desnogues <laurent.desnogues@arm.com>
248 Jim MacArthur <jim.macarthur@arm.com>
249 Marcus Shawcroft <marcus.shawcroft@arm.com>
250 Nigel Stephens <nigel.stephens@arm.com>
251 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
252 Richard Earnshaw <rearnsha@arm.com>
253 Sofiane Naci <sofiane.naci@arm.com>
254 Tejas Belagod <tejas.belagod@arm.com>
255 Yufeng Zhang <yufeng.zhang@arm.com>
257 * aarch64.h: New file.
259 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
260 Maciej W. Rozycki <macro@codesourcery.com>
262 * mips.h (mips_opcode): Add the exclusions field.
263 (OPCODE_IS_MEMBER): Remove macro.
264 (cpu_is_member): New inline function.
265 (opcode_is_member): Likewise.
267 2012-07-31 Chao-Ying Fu <fu@mips.com>
268 Catherine Moore <clm@codesourcery.com>
269 Maciej W. Rozycki <macro@codesourcery.com>
271 * mips.h: Document microMIPS DSP ASE usage.
272 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
273 microMIPS DSP ASE support.
274 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
275 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
276 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
277 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
278 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
279 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
280 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
282 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
284 * mips.h: Fix a typo in description.
286 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
288 * avr.h: (AVR_ISA_XCH): New define.
289 (AVR_ISA_XMEGA): Use it.
290 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
292 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
294 * m68hc11.h: Add XGate definitions.
295 (struct m68hc11_opcode): Add xg_mask field.
297 2012-05-14 Catherine Moore <clm@codesourcery.com>
298 Maciej W. Rozycki <macro@codesourcery.com>
299 Rhonda Wittels <rhonda@codesourcery.com>
301 * ppc.h (PPC_OPCODE_VLE): New definition.
302 (PPC_OP_SA): New macro.
303 (PPC_OP_SE_VLE): New macro.
304 (PPC_OP): Use a variable shift amount.
305 (powerpc_operand): Update comments.
306 (PPC_OPSHIFT_INV): New macro.
307 (PPC_OPERAND_CR): Replace with...
308 (PPC_OPERAND_CR_BIT): ...this and
309 (PPC_OPERAND_CR_REG): ...this.
312 2012-05-03 Sean Keys <skeys@ipdatasys.com>
314 * xgate.h: Header file for XGATE assembler.
316 2012-04-27 David S. Miller <davem@davemloft.net>
318 * sparc.h: Document new arg code' )' for crypto RS3
321 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
322 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
323 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
324 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
325 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
326 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
327 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
328 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
329 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
330 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
331 HWCAP_CBCOND, HWCAP_CRC32): New defines.
333 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
335 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
337 2012-02-27 Alan Modra <amodra@gmail.com>
339 * crx.h (cst4_map): Update declaration.
341 2012-02-25 Walter Lee <walt@tilera.com>
343 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
345 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
346 TILEPRO_OPC_LW_TLS_SN.
348 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
350 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
351 (XRELEASE_PREFIX_OPCODE): Likewise.
353 2011-12-08 Andrew Pinski <apinski@cavium.com>
354 Adam Nemet <anemet@caviumnetworks.com>
356 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
357 (INSN_OCTEON2): New macro.
358 (CPU_OCTEON2): New macro.
359 (OPCODE_IS_MEMBER): Add Octeon2.
361 2011-11-29 Andrew Pinski <apinski@cavium.com>
363 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
364 (INSN_OCTEONP): New macro.
365 (CPU_OCTEONP): New macro.
366 (OPCODE_IS_MEMBER): Add Octeon+.
367 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
369 2011-11-01 DJ Delorie <dj@redhat.com>
373 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
375 * mips.h: Fix a typo in description.
377 2011-09-21 David S. Miller <davem@davemloft.net>
379 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
380 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
381 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
382 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
384 2011-08-09 Chao-ying Fu <fu@mips.com>
385 Maciej W. Rozycki <macro@codesourcery.com>
387 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
388 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
389 (INSN_ASE_MASK): Add the MCU bit.
390 (INSN_MCU): New macro.
391 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
392 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
394 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
396 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
397 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
398 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
399 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
400 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
401 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
402 (INSN2_READ_GPR_MMN): Likewise.
403 (INSN2_READ_FPR_D): Change the bit used.
404 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
405 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
406 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
407 (INSN2_COND_BRANCH): Likewise.
408 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
409 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
410 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
411 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
412 (INSN2_MOD_GPR_MN): Likewise.
414 2011-08-05 David S. Miller <davem@davemloft.net>
416 * sparc.h: Document new format codes '4', '5', and '('.
417 (OPF_LOW4, RS3): New macros.
419 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
421 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
422 order of flags documented.
424 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
426 * mips.h: Clarify the description of microMIPS instruction
428 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
430 2011-07-24 Chao-ying Fu <fu@mips.com>
431 Maciej W. Rozycki <macro@codesourcery.com>
433 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
434 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
435 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
436 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
437 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
438 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
439 (OP_MASK_RS3, OP_SH_RS3): Likewise.
440 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
441 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
442 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
443 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
444 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
445 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
446 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
447 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
448 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
449 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
450 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
451 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
452 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
453 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
454 (INSN_WRITE_GPR_S): New macro.
455 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
456 (INSN2_READ_FPR_D): Likewise.
457 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
458 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
459 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
460 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
461 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
462 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
463 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
464 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
465 (CPU_MICROMIPS): New macro.
466 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
467 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
468 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
469 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
470 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
471 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
472 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
473 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
474 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
475 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
476 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
477 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
478 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
479 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
480 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
481 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
482 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
483 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
484 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
485 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
486 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
487 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
488 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
489 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
490 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
491 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
492 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
493 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
494 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
495 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
496 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
497 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
498 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
499 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
500 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
501 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
502 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
503 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
504 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
505 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
506 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
507 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
508 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
509 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
510 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
511 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
512 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
513 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
514 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
515 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
516 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
517 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
518 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
519 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
520 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
521 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
522 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
523 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
524 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
525 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
526 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
527 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
528 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
529 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
530 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
531 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
532 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
533 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
534 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
535 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
536 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
537 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
538 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
539 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
540 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
541 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
542 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
543 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
544 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
545 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
546 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
547 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
548 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
549 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
550 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
551 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
552 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
553 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
554 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
555 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
556 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
557 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
558 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
559 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
560 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
561 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
562 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
563 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
564 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
565 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
566 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
567 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
568 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
569 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
570 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
571 (micromips_opcodes): New declaration.
572 (bfd_micromips_num_opcodes): Likewise.
574 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
576 * mips.h (INSN_TRAP): Rename to...
577 (INSN_NO_DELAY_SLOT): ... this.
578 (INSN_SYNC): Remove macro.
580 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
582 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
583 a duplicate of AVR_ISA_SPM.
585 2011-07-01 Nick Clifton <nickc@redhat.com>
587 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
589 2011-06-18 Robin Getz <robin.getz@analog.com>
591 * bfin.h (is_macmod_signed): New func
593 2011-06-18 Mike Frysinger <vapier@gentoo.org>
595 * bfin.h (is_macmod_pmove): Add missing space before func args.
596 (is_macmod_hmove): Likewise.
598 2011-06-13 Walter Lee <walt@tilera.com>
600 * tilegx.h: New file.
601 * tilepro.h: New file.
603 2011-05-31 Paul Brook <paul@codesourcery.com>
605 * arm.h (ARM_ARCH_V7R_IDIV): Define.
607 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
609 * s390.h: Replace S390_OPERAND_REG_EVEN with
610 S390_OPERAND_REG_PAIR.
612 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
614 * s390.h: Add S390_OPCODE_REG_EVEN flag.
616 2011-04-18 Julian Brown <julian@codesourcery.com>
618 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
620 2011-04-11 Dan McDonald <dan@wellkeeper.com>
623 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
625 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
627 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
628 New instruction set flags.
629 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
631 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
633 * mips.h (M_PREF_AB): New enum value.
635 2011-02-12 Mike Frysinger <vapier@gentoo.org>
637 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
639 (is_macmod_pmove, is_macmod_hmove): New functions.
641 2011-02-11 Mike Frysinger <vapier@gentoo.org>
643 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
645 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
647 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
648 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
650 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
653 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
656 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
659 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
661 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
663 * mips.h: Update commentary after last commit.
665 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
667 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
668 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
669 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
671 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
673 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
675 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
677 * mips.h: Fix previous commit.
679 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
681 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
682 (INSN_LOONGSON_3A): Clear bit 31.
684 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
687 * arm.h (ARM_AEXT_V6M_ONLY): New define.
688 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
689 (ARM_ARCH_V6M_ONLY): New define.
691 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
693 * mips.h (INSN_LOONGSON_3A): Defined.
694 (CPU_LOONGSON_3A): Defined.
695 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
697 2010-10-09 Matt Rice <ratmice@gmail.com>
699 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
700 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
702 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
704 * arm.h (ARM_EXT_VIRT): New define.
705 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
706 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
709 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
711 * arm.h (ARM_AEXT_ADIV): New define.
712 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
714 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
716 * arm.h (ARM_EXT_OS): New define.
717 (ARM_AEXT_V6SM): Likewise.
718 (ARM_ARCH_V6SM): Likewise.
720 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
722 * arm.h (ARM_EXT_MP): Add.
723 (ARM_ARCH_V7A_MP): Likewise.
725 2010-09-22 Mike Frysinger <vapier@gentoo.org>
727 * bfin.h: Declare pseudoChr structs/defines.
729 2010-09-21 Mike Frysinger <vapier@gentoo.org>
731 * bfin.h: Strip trailing whitespace.
733 2010-07-29 DJ Delorie <dj@redhat.com>
735 * rx.h (RX_Operand_Type): Add TwoReg.
736 (RX_Opcode_ID): Remove ediv and ediv2.
738 2010-07-27 DJ Delorie <dj@redhat.com>
740 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
742 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
743 Ina Pandit <ina.pandit@kpitcummins.com>
745 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
746 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
747 PROCESSOR_V850E2_ALL.
748 Remove PROCESSOR_V850EA support.
749 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
750 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
751 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
752 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
753 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
754 V850_OPERAND_PERCENT.
755 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
757 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
760 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
762 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
763 (MIPS16_INSN_BRANCH): Rename to...
764 (MIPS16_INSN_COND_BRANCH): ... this.
766 2010-07-03 Alan Modra <amodra@gmail.com>
768 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
769 Renumber other PPC_OPCODE defines.
771 2010-07-03 Alan Modra <amodra@gmail.com>
773 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
775 2010-06-29 Alan Modra <amodra@gmail.com>
777 * maxq.h: Delete file.
779 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
781 * ppc.h (PPC_OPCODE_E500): Define.
783 2010-05-26 Catherine Moore <clm@codesourcery.com>
785 * opcode/mips.h (INSN_MIPS16): Remove.
787 2010-04-21 Joseph Myers <joseph@codesourcery.com>
789 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
791 2010-04-15 Nick Clifton <nickc@redhat.com>
793 * alpha.h: Update copyright notice to use GPLv3.
799 * convex.h: Likewise.
813 * m68hc11.h: Likewise.
819 * mn10200.h: Likewise.
820 * mn10300.h: Likewise.
821 * msp430.h: Likewise.
832 * score-datadep.h: Likewise.
833 * score-inst.h: Likewise.
835 * spu-insns.h: Likewise.
839 * tic54x.h: Likewise.
844 2010-03-25 Joseph Myers <joseph@codesourcery.com>
846 * tic6x-control-registers.h, tic6x-insn-formats.h,
847 tic6x-opcode-table.h, tic6x.h: New.
849 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
851 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
853 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
855 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
857 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
859 * ia64.h (ia64_find_opcode): Remove argument name.
860 (ia64_find_next_opcode): Likewise.
861 (ia64_dis_opcode): Likewise.
862 (ia64_free_opcode): Likewise.
863 (ia64_find_dependency): Likewise.
865 2009-11-22 Doug Evans <dje@sebabeach.org>
867 * cgen.h: Include bfd_stdint.h.
868 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
870 2009-11-18 Paul Brook <paul@codesourcery.com>
872 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
874 2009-11-17 Paul Brook <paul@codesourcery.com>
875 Daniel Jacobowitz <dan@codesourcery.com>
877 * arm.h (ARM_EXT_V6_DSP): Define.
878 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
879 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
881 2009-11-04 DJ Delorie <dj@redhat.com>
883 * rx.h (rx_decode_opcode) (mvtipl): Add.
884 (mvtcp, mvfcp, opecp): Remove.
886 2009-11-02 Paul Brook <paul@codesourcery.com>
888 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
889 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
890 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
891 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
892 FPU_ARCH_NEON_VFP_V4): Define.
894 2009-10-23 Doug Evans <dje@sebabeach.org>
896 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
897 * cgen.h: Update. Improve multi-inclusion macro name.
899 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
901 * ppc.h (PPC_OPCODE_476): Define.
903 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
905 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
907 2009-09-29 DJ Delorie <dj@redhat.com>
911 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
913 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
915 2009-09-21 Ben Elliston <bje@au.ibm.com>
917 * ppc.h (PPC_OPCODE_PPCA2): New.
919 2009-09-05 Martin Thuresson <martin@mtme.org>
921 * ia64.h (struct ia64_operand): Renamed member class to op_class.
923 2009-08-29 Martin Thuresson <martin@mtme.org>
925 * tic30.h (template): Rename type template to
926 insn_template. Updated code to use new name.
927 * tic54x.h (template): Rename type template to
930 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
932 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
934 2009-06-11 Anthony Green <green@moxielogic.com>
936 * moxie.h (MOXIE_F3_PCREL): Define.
937 (moxie_form3_opc_info): Grow.
939 2009-06-06 Anthony Green <green@moxielogic.com>
941 * moxie.h (MOXIE_F1_M): Define.
943 2009-04-15 Anthony Green <green@moxielogic.com>
947 2009-04-06 DJ Delorie <dj@redhat.com>
949 * h8300.h: Add relaxation attributes to MOVA opcodes.
951 2009-03-10 Alan Modra <amodra@bigpond.net.au>
953 * ppc.h (ppc_parse_cpu): Declare.
955 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
957 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
958 and _IMM11 for mbitclr and mbitset.
959 * score-datadep.h: Update dependency information.
961 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
963 * ppc.h (PPC_OPCODE_POWER7): New.
965 2009-02-06 Doug Evans <dje@google.com>
967 * i386.h: Add comment regarding sse* insns and prefixes.
969 2009-02-03 Sandip Matte <sandip@rmicorp.com>
971 * mips.h (INSN_XLR): Define.
972 (INSN_CHIP_MASK): Update.
974 (OPCODE_IS_MEMBER): Update.
975 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
977 2009-01-28 Doug Evans <dje@google.com>
979 * opcode/i386.h: Add multiple inclusion protection.
980 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
981 (EDI_REG_NUM): New macros.
982 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
983 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
984 (REX_PREFIX_P): New macro.
986 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
988 * ppc.h (struct powerpc_opcode): New field "deprecated".
989 (PPC_OPCODE_NOPOWER4): Delete.
991 2008-11-28 Joshua Kinard <kumba@gentoo.org>
993 * mips.h: Define CPU_R14000, CPU_R16000.
994 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
996 2008-11-18 Catherine Moore <clm@codesourcery.com>
998 * arm.h (FPU_NEON_FP16): New.
999 (FPU_ARCH_NEON_FP16): New.
1001 2008-11-06 Chao-ying Fu <fu@mips.com>
1003 * mips.h: Doucument '1' for 5-bit sync type.
1005 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1007 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1010 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1012 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1014 2008-07-30 Michael J. Eager <eager@eagercon.com>
1016 * ppc.h (PPC_OPCODE_405): Define.
1017 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1019 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1021 * ppc.h (ppc_cpu_t): New typedef.
1022 (struct powerpc_opcode <flags>): Use it.
1023 (struct powerpc_operand <insert, extract>): Likewise.
1024 (struct powerpc_macro <flags>): Likewise.
1026 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1028 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1029 Update comment before MIPS16 field descriptors to mention MIPS16.
1030 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1032 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1033 New bit masks and shift counts for cins and exts.
1035 * mips.h: Document new field descriptors +Q.
1036 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1038 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1040 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1041 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1043 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1045 * ppc.h: (PPC_OPCODE_E500MC): New.
1047 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1049 * i386.h (MAX_OPERANDS): Set to 5.
1050 (MAX_MNEM_SIZE): Changed to 20.
1052 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1054 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1056 2008-03-09 Paul Brook <paul@codesourcery.com>
1058 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1060 2008-03-04 Paul Brook <paul@codesourcery.com>
1062 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1063 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1064 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1066 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1067 Nick Clifton <nickc@redhat.com>
1070 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1071 with a 32-bit displacement but without the top bit of the 4th byte
1074 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1076 * cr16.h (cr16_num_optab): Declared.
1078 2008-02-14 Hakan Ardo <hakan@debian.org>
1081 * avr.h (AVR_ISA_2xxe): Define.
1083 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1085 * mips.h: Update copyright.
1086 (INSN_CHIP_MASK): New macro.
1087 (INSN_OCTEON): New macro.
1088 (CPU_OCTEON): New macro.
1089 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1091 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1093 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1095 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1097 * avr.h (AVR_ISA_USB162): Add new opcode set.
1098 (AVR_ISA_AVR3): Likewise.
1100 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1102 * mips.h (INSN_LOONGSON_2E): New.
1103 (INSN_LOONGSON_2F): New.
1104 (CPU_LOONGSON_2E): New.
1105 (CPU_LOONGSON_2F): New.
1106 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1108 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1110 * mips.h (INSN_ISA*): Redefine certain values as an
1111 enumeration. Update comments.
1112 (mips_isa_table): New.
1113 (ISA_MIPS*): Redefine to match enumeration.
1114 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1117 2007-08-08 Ben Elliston <bje@au.ibm.com>
1119 * ppc.h (PPC_OPCODE_PPCPS): New.
1121 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1123 * m68k.h: Document j K & E.
1125 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1127 * cr16.h: New file for CR16 target.
1129 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1131 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1133 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1135 * m68k.h (mcfisa_c): New.
1136 (mcfusp, mcf_mask): Adjust.
1138 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1140 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1141 (num_powerpc_operands): Declare.
1142 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1143 (PPC_OPERAND_PLUS1): Define.
1145 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386.h (REX_MODE64): Renamed to ...
1149 (REX_EXTX): Renamed to ...
1151 (REX_EXTY): Renamed to ...
1153 (REX_EXTZ): Renamed to ...
1156 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386.h: Add entries from config/tc-i386.h and move tables
1159 to opcodes/i386-opc.h.
1161 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1163 * i386.h (FloatDR): Removed.
1164 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1166 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1168 * spu-insns.h: Add soma double-float insns.
1170 2007-02-20 Thiemo Seufer <ths@mips.com>
1171 Chao-Ying Fu <fu@mips.com>
1173 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1174 (INSN_DSPR2): Add flag for DSP R2 instructions.
1175 (M_BALIGN): New macro.
1177 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1179 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1180 and Seg3ShortFrom with Shortform.
1182 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1185 * i386.h (i386_optab): Put the real "test" before the pseudo
1188 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1190 * m68k.h (m68010up): OR fido_a.
1192 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1194 * m68k.h (fido_a): New.
1196 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1198 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1199 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1202 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1204 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1206 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1208 * score-inst.h (enum score_insn_type): Add Insn_internal.
1210 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1211 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1212 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1213 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1214 Alan Modra <amodra@bigpond.net.au>
1216 * spu-insns.h: New file.
1219 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1221 * ppc.h (PPC_OPCODE_CELL): Define.
1223 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1225 * i386.h : Modify opcode to support for the change in POPCNT opcode
1226 in amdfam10 architecture.
1228 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1230 * i386.h: Replace CpuMNI with CpuSSSE3.
1232 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1233 Joseph Myers <joseph@codesourcery.com>
1234 Ian Lance Taylor <ian@wasabisystems.com>
1235 Ben Elliston <bje@wasabisystems.com>
1237 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1239 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1241 * score-datadep.h: New file.
1242 * score-inst.h: New file.
1244 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1246 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1247 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1248 movdq2q and movq2dq.
1250 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1251 Michael Meissner <michael.meissner@amd.com>
1253 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1255 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1257 * i386.h (i386_optab): Add "nop" with memory reference.
1259 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1261 * i386.h (i386_optab): Update comment for 64bit NOP.
1263 2006-06-06 Ben Elliston <bje@au.ibm.com>
1264 Anton Blanchard <anton@samba.org>
1266 * ppc.h (PPC_OPCODE_POWER6): Define.
1269 2006-06-05 Thiemo Seufer <ths@mips.com>
1271 * mips.h: Improve description of MT flags.
1273 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1275 * m68k.h (mcf_mask): Define.
1277 2006-05-05 Thiemo Seufer <ths@mips.com>
1278 David Ung <davidu@mips.com>
1280 * mips.h (enum): Add macro M_CACHE_AB.
1282 2006-05-04 Thiemo Seufer <ths@mips.com>
1283 Nigel Stephens <nigel@mips.com>
1284 David Ung <davidu@mips.com>
1286 * mips.h: Add INSN_SMARTMIPS define.
1288 2006-04-30 Thiemo Seufer <ths@mips.com>
1289 David Ung <davidu@mips.com>
1291 * mips.h: Defines udi bits and masks. Add description of
1292 characters which may appear in the args field of udi
1295 2006-04-26 Thiemo Seufer <ths@networkno.de>
1297 * mips.h: Improve comments describing the bitfield instruction
1300 2006-04-26 Julian Brown <julian@codesourcery.com>
1302 * arm.h (FPU_VFP_EXT_V3): Define constant.
1303 (FPU_NEON_EXT_V1): Likewise.
1304 (FPU_VFP_HARD): Update.
1305 (FPU_VFP_V3): Define macro.
1306 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1308 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1310 * avr.h (AVR_ISA_PWMx): New.
1312 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1314 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1315 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1316 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1317 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1318 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1320 2006-03-10 Paul Brook <paul@codesourcery.com>
1322 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1324 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1326 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1327 first. Correct mask of bb "B" opcode.
1329 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1331 * i386.h (i386_optab): Support Intel Merom New Instructions.
1333 2006-02-24 Paul Brook <paul@codesourcery.com>
1335 * arm.h: Add V7 feature bits.
1337 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1339 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1341 2006-01-31 Paul Brook <paul@codesourcery.com>
1342 Richard Earnshaw <rearnsha@arm.com>
1344 * arm.h: Use ARM_CPU_FEATURE.
1345 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1346 (arm_feature_set): Change to a structure.
1347 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1348 ARM_FEATURE): New macros.
1350 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1352 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1353 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1354 (ADD_PC_INCR_OPCODE): Don't define.
1356 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1359 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1361 2005-11-14 David Ung <davidu@mips.com>
1363 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1364 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1365 save/restore encoding of the args field.
1367 2005-10-28 Dave Brolley <brolley@redhat.com>
1369 Contribute the following changes:
1370 2005-02-16 Dave Brolley <brolley@redhat.com>
1372 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1373 cgen_isa_mask_* to cgen_bitset_*.
1376 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1378 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1379 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1380 (CGEN_CPU_TABLE): Make isas a ponter.
1382 2003-09-29 Dave Brolley <brolley@redhat.com>
1384 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1385 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1386 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1388 2002-12-13 Dave Brolley <brolley@redhat.com>
1390 * cgen.h (symcat.h): #include it.
1391 (cgen-bitset.h): #include it.
1392 (CGEN_ATTR_VALUE_TYPE): Now a union.
1393 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1394 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1395 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1396 * cgen-bitset.h: New file.
1398 2005-09-30 Catherine Moore <clm@cm00re.com>
1402 2005-10-24 Jan Beulich <jbeulich@novell.com>
1404 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1407 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1409 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1410 Add FLAG_STRICT to pa10 ftest opcode.
1412 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1414 * hppa.h (pa_opcodes): Remove lha entries.
1416 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1418 * hppa.h (FLAG_STRICT): Revise comment.
1419 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1420 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1423 2005-09-30 Catherine Moore <clm@cm00re.com>
1427 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1429 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1431 2005-09-06 Chao-ying Fu <fu@mips.com>
1433 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1434 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1436 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1437 (INSN_ASE_MASK): Update to include INSN_MT.
1438 (INSN_MT): New define for MT ASE.
1440 2005-08-25 Chao-ying Fu <fu@mips.com>
1442 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1443 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1444 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1445 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1446 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1447 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1449 (INSN_DSP): New define for DSP ASE.
1451 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1455 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1457 * ppc.h (PPC_OPCODE_E300): Define.
1459 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1461 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1463 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1466 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1469 2005-07-27 Jan Beulich <jbeulich@novell.com>
1471 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1472 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1473 Add movq-s as 64-bit variants of movd-s.
1475 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1477 * hppa.h: Fix punctuation in comment.
1479 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1480 implicit space-register addressing. Set space-register bits on opcodes
1481 using implicit space-register addressing. Add various missing pa20
1482 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1483 space-register addressing. Use "fE" instead of "fe" in various
1486 2005-07-18 Jan Beulich <jbeulich@novell.com>
1488 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1490 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1492 * i386.h (i386_optab): Support Intel VMX Instructions.
1494 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1496 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1498 2005-07-05 Jan Beulich <jbeulich@novell.com>
1500 * i386.h (i386_optab): Add new insns.
1502 2005-07-01 Nick Clifton <nickc@redhat.com>
1504 * sparc.h: Add typedefs to structure declarations.
1506 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1509 * i386.h (i386_optab): Update comments for 64bit addressing on
1510 mov. Allow 64bit addressing for mov and movq.
1512 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1514 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1515 respectively, in various floating-point load and store patterns.
1517 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1519 * hppa.h (FLAG_STRICT): Correct comment.
1520 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1521 PA 2.0 mneumonics when equivalent. Entries with cache control
1522 completers now require PA 1.1. Adjust whitespace.
1524 2005-05-19 Anton Blanchard <anton@samba.org>
1526 * ppc.h (PPC_OPCODE_POWER5): Define.
1528 2005-05-10 Nick Clifton <nickc@redhat.com>
1530 * Update the address and phone number of the FSF organization in
1531 the GPL notices in the following files:
1532 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1533 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1534 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1535 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1536 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1537 tic54x.h, tic80.h, v850.h, vax.h
1539 2005-05-09 Jan Beulich <jbeulich@novell.com>
1541 * i386.h (i386_optab): Add ht and hnt.
1543 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1545 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1546 Add xcrypt-ctr. Provide aliases without hyphens.
1548 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1550 Moved from ../ChangeLog
1552 2005-04-12 Paul Brook <paul@codesourcery.com>
1553 * m88k.h: Rename psr macros to avoid conflicts.
1555 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1556 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1557 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1558 and ARM_ARCH_V6ZKT2.
1560 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1561 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1562 Remove redundant instruction types.
1563 (struct argument): X_op - new field.
1564 (struct cst4_entry): Remove.
1565 (no_op_insn): Declare.
1567 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1568 * crx.h (enum argtype): Rename types, remove unused types.
1570 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1571 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1572 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1573 (enum operand_type): Rearrange operands, edit comments.
1574 replace us<N> with ui<N> for unsigned immediate.
1575 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1576 displacements (respectively).
1577 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1578 (instruction type): Add NO_TYPE_INS.
1579 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1580 (operand_entry): New field - 'flags'.
1581 (operand flags): New.
1583 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1584 * crx.h (operand_type): Remove redundant types i3, i4,
1586 Add new unsigned immediate types us3, us4, us5, us16.
1588 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1590 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1591 adjust them accordingly.
1593 2005-04-01 Jan Beulich <jbeulich@novell.com>
1595 * i386.h (i386_optab): Add rdtscp.
1597 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1599 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1600 between memory and segment register. Allow movq for moving between
1601 general-purpose register and segment register.
1603 2005-02-09 Jan Beulich <jbeulich@novell.com>
1606 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1607 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1610 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1612 * m68k.h (m68008, m68ec030, m68882): Remove.
1614 (cpu_m68k, cpu_cf): New.
1615 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1616 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1618 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1620 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1621 * cgen.h (enum cgen_parse_operand_type): Add
1622 CGEN_PARSE_OPERAND_SYMBOLIC.
1624 2005-01-21 Fred Fish <fnf@specifixinc.com>
1626 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1627 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1628 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1630 2005-01-19 Fred Fish <fnf@specifixinc.com>
1632 * mips.h (struct mips_opcode): Add new pinfo2 member.
1633 (INSN_ALIAS): New define for opcode table entries that are
1634 specific instances of another entry, such as 'move' for an 'or'
1635 with a zero operand.
1636 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1637 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1639 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1641 * mips.h (CPU_RM9000): Define.
1642 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1644 2004-11-25 Jan Beulich <jbeulich@novell.com>
1646 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1647 to/from test registers are illegal in 64-bit mode. Add missing
1648 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1649 (previously one had to explicitly encode a rex64 prefix). Re-enable
1650 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1651 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1653 2004-11-23 Jan Beulich <jbeulich@novell.com>
1655 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1656 available only with SSE2. Change the MMX additions introduced by SSE
1657 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1658 instructions by their now designated identifier (since combining i686
1659 and 3DNow! does not really imply 3DNow!A).
1661 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1663 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1664 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1666 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1667 Vineet Sharma <vineets@noida.hcltech.com>
1669 * maxq.h: New file: Disassembly information for the maxq port.
1671 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1673 * i386.h (i386_optab): Put back "movzb".
1675 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1677 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1678 comments. Remove member cris_ver_sim. Add members
1679 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1680 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1681 (struct cris_support_reg, struct cris_cond15): New types.
1682 (cris_conds15): Declare.
1683 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1684 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1685 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1686 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1687 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1688 SIZE_FIELD_UNSIGNED.
1690 2004-11-04 Jan Beulich <jbeulich@novell.com>
1692 * i386.h (sldx_Suf): Remove.
1693 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1694 (q_FP): Define, implying no REX64.
1695 (x_FP, sl_FP): Imply FloatMF.
1696 (i386_optab): Split reg and mem forms of moving from segment registers
1697 so that the memory forms can ignore the 16-/32-bit operand size
1698 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1699 all non-floating-point instructions. Unite 32- and 64-bit forms of
1700 movsx, movzx, and movd. Adjust floating point operations for the above
1701 changes to the *FP macros. Add DefaultSize to floating point control
1702 insns operating on larger memory ranges. Remove left over comments
1703 hinting at certain insns being Intel-syntax ones where the ones
1704 actually meant are already gone.
1706 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1708 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1711 2004-09-30 Paul Brook <paul@codesourcery.com>
1713 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1714 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1716 2004-09-11 Theodore A. Roth <troth@openavr.org>
1718 * avr.h: Add support for
1719 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1721 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1723 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1725 2004-08-24 Dmitry Diky <diwil@spec.ru>
1727 * msp430.h (msp430_opc): Add new instructions.
1728 (msp430_rcodes): Declare new instructions.
1729 (msp430_hcodes): Likewise..
1731 2004-08-13 Nick Clifton <nickc@redhat.com>
1734 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1737 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1739 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1741 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1743 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1745 2004-07-21 Jan Beulich <jbeulich@novell.com>
1747 * i386.h: Adjust instruction descriptions to better match the
1750 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1752 * arm.h: Remove all old content. Replace with architecture defines
1753 from gas/config/tc-arm.c.
1755 2004-07-09 Andreas Schwab <schwab@suse.de>
1757 * m68k.h: Fix comment.
1759 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1763 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1765 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1767 2004-05-24 Peter Barada <peter@the-baradas.com>
1769 * m68k.h: Add 'size' to m68k_opcode.
1771 2004-05-05 Peter Barada <peter@the-baradas.com>
1773 * m68k.h: Switch from ColdFire chip name to core variant.
1775 2004-04-22 Peter Barada <peter@the-baradas.com>
1777 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1778 descriptions for new EMAC cases.
1779 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1780 handle Motorola MAC syntax.
1781 Allow disassembly of ColdFire V4e object files.
1783 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1785 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1787 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1789 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1791 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1793 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1795 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1797 * i386.h (i386_optab): Added xstore/xcrypt insns.
1799 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1801 * h8300.h (32bit ldc/stc): Add relaxing support.
1803 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1805 * h8300.h (BITOP): Pass MEMRELAX flag.
1807 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1809 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1812 For older changes see ChangeLog-9103
1814 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1816 Copying and distribution of this file, with or without modification,
1817 are permitted in any medium without royalty provided the copyright
1818 notice and this notice are preserved.
1824 version-control: never