1 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * sparc.h (HWCAP2_VIS3B): Documentation improved.
5 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
7 * sparc.h (sparc_opcode): new field `hwcaps2'.
8 (HWCAP2_FJATHPLUS): New define.
9 (HWCAP2_VIS3B): Likewise.
10 (HWCAP2_ADP): Likewise.
11 (HWCAP2_SPARC5): Likewise.
12 (HWCAP2_MWAIT): Likewise.
13 (HWCAP2_XMPMUL): Likewise.
14 (HWCAP2_XMONT): Likewise.
15 (HWCAP2_NSEC): Likewise.
16 (HWCAP2_FJATHHPC): Likewise.
17 (HWCAP2_FJDES): Likewise.
18 (HWCAP2_FJAES): Likewise.
19 Document the new operand kind `{', corresponding to the mcdper
20 ancillary state register.
21 Document the new operand kind }, which represents frsd floating
22 point registers (double precision) which must be the same than
23 frs1 in its containing instruction.
25 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
27 * nds32.h: Add new opcode declaration.
29 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
30 Matthew Fortune <matthew.fortune@imgtec.com>
32 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
33 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
34 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
35 +I, +O, +R, +:, +\, +", +;
36 (mips_check_prev_operand): New struct.
37 (INSN2_FORBIDDEN_SLOT): New define.
38 (INSN_ISA32R6): New define.
39 (INSN_ISA64R6): New define.
40 (INSN_UPTO32R6): New define.
41 (INSN_UPTO64R6): New define.
42 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
43 (ISA_MIPS32R6): New define.
44 (ISA_MIPS64R6): New define.
45 (CPU_MIPS32R6): New define.
46 (CPU_MIPS64R6): New define.
47 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
49 2014-09-03 Jiong Wang <jiong.wang@arm.com>
51 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
52 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
53 (aarch64_insn_class): Add lse_atomic.
54 (F_LSE_SZ): New field added.
55 (opcode_has_special_coder): Recognize F_LSE_SZ.
57 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
59 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
62 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
64 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
65 (INSN_LOAD_COPROC): New define.
66 (INSN_COPROC_MOVE_DELAY): Rename to...
67 (INSN_COPROC_MOVE): New define.
69 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
70 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
71 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
72 Soundararajan <Sounderarajan.D@atmel.com>
74 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
75 (AVR_ISA_2xxxa): Define ISA without LPM.
76 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
77 Add doc for contraint used in 16 bit lds/sts.
78 Adjust ISA group for icall, ijmp, pop and push.
79 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
81 2014-05-19 Nick Clifton <nickc@redhat.com>
83 * msp430.h (struct msp430_operand_s): Add vshift field.
85 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
87 * mips.h (INSN_ISA_MASK): Updated.
88 (INSN_ISA32R3): New define.
89 (INSN_ISA32R5): New define.
90 (INSN_ISA64R3): New define.
91 (INSN_ISA64R5): New define.
92 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
93 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
94 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
96 (INSN_UPTO32R3): New define.
97 (INSN_UPTO32R5): New define.
98 (INSN_UPTO64R3): New define.
99 (INSN_UPTO64R5): New define.
100 (ISA_MIPS32R3): New define.
101 (ISA_MIPS32R5): New define.
102 (ISA_MIPS64R3): New define.
103 (ISA_MIPS64R5): New define.
104 (CPU_MIPS32R3): New define.
105 (CPU_MIPS32R5): New define.
106 (CPU_MIPS64R3): New define.
107 (CPU_MIPS64R5): New define.
109 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
111 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
113 2014-04-22 Christian Svensson <blue@cmd.nu>
117 2014-03-05 Alan Modra <amodra@gmail.com>
119 Update copyright years.
121 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
123 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
126 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
127 Wei-Cheng Wang <cole945@gmail.com>
129 * nds32.h: New file for Andes NDS32.
131 2013-12-07 Mike Frysinger <vapier@gentoo.org>
133 * bfin.h: Remove +x file mode.
135 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
137 * aarch64.h (aarch64_pstatefields): Change element type to
140 2013-11-18 Renlin Li <Renlin.Li@arm.com>
142 * arm.h (ARM_AEXT_V7VE): New define.
143 (ARM_ARCH_V7VE): New define.
144 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
146 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
150 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
152 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
153 (aarch64_sys_reg_writeonly_p): Ditto.
155 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
157 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
158 (aarch64_sys_reg_writeonly_p): Ditto.
160 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
162 * aarch64.h (aarch64_sys_reg): New typedef.
163 (aarch64_sys_regs): Change to define with the new type.
164 (aarch64_sys_reg_deprecated_p): Declare.
166 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
168 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
169 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
171 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
173 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
174 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
175 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
176 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
177 For MIPS, update extension character sequences after +.
178 (ASE_MSA): New define.
179 (ASE_MSA64): New define.
180 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
181 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
182 For microMIPS, update extension character sequences after +.
184 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
189 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
191 * mips.h: Remove references to "+I" and imm2_expr.
193 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
195 * mips.h (M_DEXT, M_DINS): Delete.
197 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
199 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
200 (mips_optional_operand_p): New function.
202 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
203 Richard Sandiford <rdsandiford@googlemail.com>
205 * mips.h: Document new VU0 operand characters.
206 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
207 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
208 (OP_REG_R5900_ACC): New mips_reg_operand_types.
209 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
210 (mips_vu0_channel_mask): Declare.
212 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
214 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
215 (mips_int_operand_min, mips_int_operand_max): New functions.
216 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
218 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
220 * mips.h (mips_decode_reg_operand): New function.
221 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
222 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
223 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
225 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
226 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
227 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
228 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
229 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
230 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
231 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
232 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
233 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
234 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
235 macros to cover the gaps.
236 (INSN2_MOD_SP): Replace with...
237 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
238 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
239 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
240 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
241 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
244 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
246 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
247 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
248 (MIPS16_INSN_COND_BRANCH): Delete.
250 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
251 Kirill Yukhin <kirill.yukhin@intel.com>
252 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
254 * i386.h (BND_PREFIX_OPCODE): New.
256 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
258 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
259 OP_SAVE_RESTORE_LIST.
260 (decode_mips16_operand): Declare.
262 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
264 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
265 (mips_operand, mips_int_operand, mips_mapped_int_operand)
266 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
267 (mips_pcrel_operand): New structures.
268 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
269 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
270 (decode_mips_operand, decode_micromips_operand): Declare.
272 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
274 * mips.h: Document MIPS16 "I" opcode.
276 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
278 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
279 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
280 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
281 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
282 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
283 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
284 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
285 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
286 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
287 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
288 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
289 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
290 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
292 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
293 (M_USD_AB): ...these.
295 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
297 * mips.h: Remove documentation of "[" and "]". Update documentation
298 of "k" and the MDMX formats.
300 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
302 * mips.h: Update documentation of "+s" and "+S".
304 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
306 * mips.h: Document "+i".
308 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
310 * mips.h: Remove "mi" documentation. Update "mh" documentation.
311 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
313 (INSN2_WRITE_GPR_MHI): Rename to...
314 (INSN2_WRITE_GPR_MH): ...this.
316 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
318 * mips.h: Remove documentation of "+D" and "+T".
320 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
322 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
323 Use "source" rather than "destination" for microMIPS "G".
325 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
327 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
330 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
332 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
334 2013-06-17 Catherine Moore <clm@codesourcery.com>
335 Maciej W. Rozycki <macro@codesourcery.com>
336 Chao-Ying Fu <fu@mips.com>
338 * mips.h (OP_SH_EVAOFFSET): Define.
339 (OP_MASK_EVAOFFSET): Define.
340 (INSN_ASE_MASK): Delete.
342 (M_CACHEE_AB, M_CACHEE_OB): New.
343 (M_LBE_OB, M_LBE_AB): New.
344 (M_LBUE_OB, M_LBUE_AB): New.
345 (M_LHE_OB, M_LHE_AB): New.
346 (M_LHUE_OB, M_LHUE_AB): New.
347 (M_LLE_AB, M_LLE_OB): New.
348 (M_LWE_OB, M_LWE_AB): New.
349 (M_LWLE_AB, M_LWLE_OB): New.
350 (M_LWRE_AB, M_LWRE_OB): New.
351 (M_PREFE_AB, M_PREFE_OB): New.
352 (M_SCE_AB, M_SCE_OB): New.
353 (M_SBE_OB, M_SBE_AB): New.
354 (M_SHE_OB, M_SHE_AB): New.
355 (M_SWE_OB, M_SWE_AB): New.
356 (M_SWLE_AB, M_SWLE_OB): New.
357 (M_SWRE_AB, M_SWRE_OB): New.
358 (MICROMIPSOP_SH_EVAOFFSET): Define.
359 (MICROMIPSOP_MASK_EVAOFFSET): Define.
361 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
363 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
365 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
367 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
369 2013-05-09 Andrew Pinski <apinski@cavium.com>
371 * mips.h (OP_MASK_CODE10): Correct definition.
372 (OP_SH_CODE10): Likewise.
373 Add a comment that "+J" is used now for OP_*CODE10.
374 (INSN_ASE_MASK): Update.
375 (INSN_VIRT): New macro.
376 (INSN_VIRT64): New macro
378 2013-05-02 Nick Clifton <nickc@redhat.com>
380 * msp430.h: Add patterns for MSP430X instructions.
382 2013-04-06 David S. Miller <davem@davemloft.net>
384 * sparc.h (F_PREFERRED): Define.
385 (F_PREF_ALIAS): Define.
387 2013-04-03 Nick Clifton <nickc@redhat.com>
389 * v850.h (V850_INVERSE_PCREL): Define.
391 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
394 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
396 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
399 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
401 * tic6xc-opcode-table.h: Add 16-bit insns.
402 * tic6x.h: Add support for 16-bit insns.
404 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
406 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
407 and mov.b/w/l Rs,@(d:32,ERd).
409 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
412 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
413 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
414 tic6x_operand_xregpair operand coding type.
415 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
416 opcode field, usu ORXREGD1324 for the src2 operand and remove the
419 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
422 * tic6x.h (enum tic6x_coding_method): Add
423 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
424 separately the msb and lsb of a register pair. This is needed to
425 encode the opcodes in the same way as TI assembler does.
426 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
427 and rsqrdp opcodes to use the new field coding types.
429 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
431 * arm.h (CRC_EXT_ARMV8): New constant.
432 (ARCH_CRC_ARMV8): New macro.
434 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
436 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
438 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
439 Andrew Jenner <andrew@codesourcery.com>
441 Based on patches from Altera Corporation.
445 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
447 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
449 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
452 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
454 2013-01-24 Nick Clifton <nickc@redhat.com>
456 * v850.h: Add e3v5 support.
458 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
460 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
462 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
464 * ppc.h (PPC_OPCODE_POWER8): New define.
465 (PPC_OPCODE_HTM): Likewise.
467 2013-01-10 Will Newton <will.newton@imgtec.com>
471 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
473 * cr16.h (make_instruction): Rename to cr16_make_instruction.
474 (match_opcode): Rename to cr16_match_opcode.
476 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
478 * mips.h: Add support for r5900 instructions including lq and sq.
480 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
482 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
483 (make_instruction,match_opcode): Added function prototypes.
484 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
486 2012-11-23 Alan Modra <amodra@gmail.com>
488 * ppc.h (ppc_parse_cpu): Update prototype.
490 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
492 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
493 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
495 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
497 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
499 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
501 * ia64.h (ia64_opnd): Add new operand types.
503 2012-08-21 David S. Miller <davem@davemloft.net>
505 * sparc.h (F3F4): New macro.
507 2012-08-13 Ian Bolton <ian.bolton@arm.com>
508 Laurent Desnogues <laurent.desnogues@arm.com>
509 Jim MacArthur <jim.macarthur@arm.com>
510 Marcus Shawcroft <marcus.shawcroft@arm.com>
511 Nigel Stephens <nigel.stephens@arm.com>
512 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
513 Richard Earnshaw <rearnsha@arm.com>
514 Sofiane Naci <sofiane.naci@arm.com>
515 Tejas Belagod <tejas.belagod@arm.com>
516 Yufeng Zhang <yufeng.zhang@arm.com>
518 * aarch64.h: New file.
520 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
521 Maciej W. Rozycki <macro@codesourcery.com>
523 * mips.h (mips_opcode): Add the exclusions field.
524 (OPCODE_IS_MEMBER): Remove macro.
525 (cpu_is_member): New inline function.
526 (opcode_is_member): Likewise.
528 2012-07-31 Chao-Ying Fu <fu@mips.com>
529 Catherine Moore <clm@codesourcery.com>
530 Maciej W. Rozycki <macro@codesourcery.com>
532 * mips.h: Document microMIPS DSP ASE usage.
533 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
534 microMIPS DSP ASE support.
535 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
536 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
537 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
538 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
539 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
540 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
541 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
543 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
545 * mips.h: Fix a typo in description.
547 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
549 * avr.h: (AVR_ISA_XCH): New define.
550 (AVR_ISA_XMEGA): Use it.
551 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
553 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
555 * m68hc11.h: Add XGate definitions.
556 (struct m68hc11_opcode): Add xg_mask field.
558 2012-05-14 Catherine Moore <clm@codesourcery.com>
559 Maciej W. Rozycki <macro@codesourcery.com>
560 Rhonda Wittels <rhonda@codesourcery.com>
562 * ppc.h (PPC_OPCODE_VLE): New definition.
563 (PPC_OP_SA): New macro.
564 (PPC_OP_SE_VLE): New macro.
565 (PPC_OP): Use a variable shift amount.
566 (powerpc_operand): Update comments.
567 (PPC_OPSHIFT_INV): New macro.
568 (PPC_OPERAND_CR): Replace with...
569 (PPC_OPERAND_CR_BIT): ...this and
570 (PPC_OPERAND_CR_REG): ...this.
573 2012-05-03 Sean Keys <skeys@ipdatasys.com>
575 * xgate.h: Header file for XGATE assembler.
577 2012-04-27 David S. Miller <davem@davemloft.net>
579 * sparc.h: Document new arg code' )' for crypto RS3
582 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
583 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
584 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
585 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
586 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
587 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
588 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
589 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
590 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
591 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
592 HWCAP_CBCOND, HWCAP_CRC32): New defines.
594 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
596 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
598 2012-02-27 Alan Modra <amodra@gmail.com>
600 * crx.h (cst4_map): Update declaration.
602 2012-02-25 Walter Lee <walt@tilera.com>
604 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
606 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
607 TILEPRO_OPC_LW_TLS_SN.
609 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
611 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
612 (XRELEASE_PREFIX_OPCODE): Likewise.
614 2011-12-08 Andrew Pinski <apinski@cavium.com>
615 Adam Nemet <anemet@caviumnetworks.com>
617 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
618 (INSN_OCTEON2): New macro.
619 (CPU_OCTEON2): New macro.
620 (OPCODE_IS_MEMBER): Add Octeon2.
622 2011-11-29 Andrew Pinski <apinski@cavium.com>
624 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
625 (INSN_OCTEONP): New macro.
626 (CPU_OCTEONP): New macro.
627 (OPCODE_IS_MEMBER): Add Octeon+.
628 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
630 2011-11-01 DJ Delorie <dj@redhat.com>
634 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
636 * mips.h: Fix a typo in description.
638 2011-09-21 David S. Miller <davem@davemloft.net>
640 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
641 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
642 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
643 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
645 2011-08-09 Chao-ying Fu <fu@mips.com>
646 Maciej W. Rozycki <macro@codesourcery.com>
648 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
649 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
650 (INSN_ASE_MASK): Add the MCU bit.
651 (INSN_MCU): New macro.
652 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
653 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
655 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
657 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
658 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
659 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
660 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
661 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
662 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
663 (INSN2_READ_GPR_MMN): Likewise.
664 (INSN2_READ_FPR_D): Change the bit used.
665 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
666 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
667 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
668 (INSN2_COND_BRANCH): Likewise.
669 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
670 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
671 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
672 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
673 (INSN2_MOD_GPR_MN): Likewise.
675 2011-08-05 David S. Miller <davem@davemloft.net>
677 * sparc.h: Document new format codes '4', '5', and '('.
678 (OPF_LOW4, RS3): New macros.
680 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
682 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
683 order of flags documented.
685 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
687 * mips.h: Clarify the description of microMIPS instruction
689 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
691 2011-07-24 Chao-ying Fu <fu@mips.com>
692 Maciej W. Rozycki <macro@codesourcery.com>
694 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
695 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
696 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
697 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
698 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
699 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
700 (OP_MASK_RS3, OP_SH_RS3): Likewise.
701 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
702 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
703 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
704 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
705 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
706 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
707 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
708 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
709 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
710 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
711 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
712 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
713 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
714 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
715 (INSN_WRITE_GPR_S): New macro.
716 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
717 (INSN2_READ_FPR_D): Likewise.
718 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
719 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
720 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
721 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
722 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
723 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
724 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
725 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
726 (CPU_MICROMIPS): New macro.
727 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
728 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
729 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
730 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
731 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
732 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
733 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
734 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
735 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
736 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
737 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
738 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
739 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
740 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
741 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
742 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
743 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
744 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
745 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
746 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
747 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
748 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
749 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
750 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
751 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
752 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
753 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
754 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
755 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
756 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
757 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
758 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
759 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
760 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
761 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
762 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
763 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
764 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
765 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
766 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
767 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
768 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
769 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
770 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
771 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
772 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
773 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
774 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
775 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
776 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
777 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
778 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
779 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
780 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
781 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
782 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
783 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
784 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
785 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
786 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
787 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
788 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
789 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
790 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
791 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
792 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
793 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
794 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
795 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
796 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
797 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
798 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
799 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
800 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
801 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
802 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
803 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
804 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
805 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
806 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
807 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
808 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
809 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
810 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
811 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
812 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
813 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
814 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
815 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
816 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
817 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
818 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
819 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
820 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
821 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
822 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
823 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
824 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
825 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
826 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
827 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
828 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
829 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
830 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
831 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
832 (micromips_opcodes): New declaration.
833 (bfd_micromips_num_opcodes): Likewise.
835 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
837 * mips.h (INSN_TRAP): Rename to...
838 (INSN_NO_DELAY_SLOT): ... this.
839 (INSN_SYNC): Remove macro.
841 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
843 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
844 a duplicate of AVR_ISA_SPM.
846 2011-07-01 Nick Clifton <nickc@redhat.com>
848 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
850 2011-06-18 Robin Getz <robin.getz@analog.com>
852 * bfin.h (is_macmod_signed): New func
854 2011-06-18 Mike Frysinger <vapier@gentoo.org>
856 * bfin.h (is_macmod_pmove): Add missing space before func args.
857 (is_macmod_hmove): Likewise.
859 2011-06-13 Walter Lee <walt@tilera.com>
861 * tilegx.h: New file.
862 * tilepro.h: New file.
864 2011-05-31 Paul Brook <paul@codesourcery.com>
866 * arm.h (ARM_ARCH_V7R_IDIV): Define.
868 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
870 * s390.h: Replace S390_OPERAND_REG_EVEN with
871 S390_OPERAND_REG_PAIR.
873 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
875 * s390.h: Add S390_OPCODE_REG_EVEN flag.
877 2011-04-18 Julian Brown <julian@codesourcery.com>
879 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
881 2011-04-11 Dan McDonald <dan@wellkeeper.com>
884 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
886 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
888 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
889 New instruction set flags.
890 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
892 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
894 * mips.h (M_PREF_AB): New enum value.
896 2011-02-12 Mike Frysinger <vapier@gentoo.org>
898 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
900 (is_macmod_pmove, is_macmod_hmove): New functions.
902 2011-02-11 Mike Frysinger <vapier@gentoo.org>
904 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
906 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
908 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
909 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
911 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
914 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
917 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
920 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
922 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
924 * mips.h: Update commentary after last commit.
926 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
928 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
929 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
930 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
932 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
934 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
936 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
938 * mips.h: Fix previous commit.
940 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
942 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
943 (INSN_LOONGSON_3A): Clear bit 31.
945 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
948 * arm.h (ARM_AEXT_V6M_ONLY): New define.
949 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
950 (ARM_ARCH_V6M_ONLY): New define.
952 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
954 * mips.h (INSN_LOONGSON_3A): Defined.
955 (CPU_LOONGSON_3A): Defined.
956 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
958 2010-10-09 Matt Rice <ratmice@gmail.com>
960 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
961 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
963 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
965 * arm.h (ARM_EXT_VIRT): New define.
966 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
967 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
970 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
972 * arm.h (ARM_AEXT_ADIV): New define.
973 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
975 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
977 * arm.h (ARM_EXT_OS): New define.
978 (ARM_AEXT_V6SM): Likewise.
979 (ARM_ARCH_V6SM): Likewise.
981 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
983 * arm.h (ARM_EXT_MP): Add.
984 (ARM_ARCH_V7A_MP): Likewise.
986 2010-09-22 Mike Frysinger <vapier@gentoo.org>
988 * bfin.h: Declare pseudoChr structs/defines.
990 2010-09-21 Mike Frysinger <vapier@gentoo.org>
992 * bfin.h: Strip trailing whitespace.
994 2010-07-29 DJ Delorie <dj@redhat.com>
996 * rx.h (RX_Operand_Type): Add TwoReg.
997 (RX_Opcode_ID): Remove ediv and ediv2.
999 2010-07-27 DJ Delorie <dj@redhat.com>
1001 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1003 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1004 Ina Pandit <ina.pandit@kpitcummins.com>
1006 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1007 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1008 PROCESSOR_V850E2_ALL.
1009 Remove PROCESSOR_V850EA support.
1010 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1011 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1012 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1013 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1014 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1015 V850_OPERAND_PERCENT.
1016 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1018 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1021 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1023 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1024 (MIPS16_INSN_BRANCH): Rename to...
1025 (MIPS16_INSN_COND_BRANCH): ... this.
1027 2010-07-03 Alan Modra <amodra@gmail.com>
1029 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1030 Renumber other PPC_OPCODE defines.
1032 2010-07-03 Alan Modra <amodra@gmail.com>
1034 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1036 2010-06-29 Alan Modra <amodra@gmail.com>
1038 * maxq.h: Delete file.
1040 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1042 * ppc.h (PPC_OPCODE_E500): Define.
1044 2010-05-26 Catherine Moore <clm@codesourcery.com>
1046 * opcode/mips.h (INSN_MIPS16): Remove.
1048 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1050 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1052 2010-04-15 Nick Clifton <nickc@redhat.com>
1054 * alpha.h: Update copyright notice to use GPLv3.
1060 * convex.h: Likewise.
1067 * h8300.h: Likewise.
1074 * m68hc11.h: Likewise.
1080 * mn10200.h: Likewise.
1081 * mn10300.h: Likewise.
1082 * msp430.h: Likewise.
1084 * ns32k.h: Likewise.
1086 * pdp11.h: Likewise.
1093 * score-datadep.h: Likewise.
1094 * score-inst.h: Likewise.
1095 * sparc.h: Likewise.
1096 * spu-insns.h: Likewise.
1098 * tic30.h: Likewise.
1099 * tic4x.h: Likewise.
1100 * tic54x.h: Likewise.
1101 * tic80.h: Likewise.
1105 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1107 * tic6x-control-registers.h, tic6x-insn-formats.h,
1108 tic6x-opcode-table.h, tic6x.h: New.
1110 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1112 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1114 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1116 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1118 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1120 * ia64.h (ia64_find_opcode): Remove argument name.
1121 (ia64_find_next_opcode): Likewise.
1122 (ia64_dis_opcode): Likewise.
1123 (ia64_free_opcode): Likewise.
1124 (ia64_find_dependency): Likewise.
1126 2009-11-22 Doug Evans <dje@sebabeach.org>
1128 * cgen.h: Include bfd_stdint.h.
1129 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1131 2009-11-18 Paul Brook <paul@codesourcery.com>
1133 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1135 2009-11-17 Paul Brook <paul@codesourcery.com>
1136 Daniel Jacobowitz <dan@codesourcery.com>
1138 * arm.h (ARM_EXT_V6_DSP): Define.
1139 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1140 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1142 2009-11-04 DJ Delorie <dj@redhat.com>
1144 * rx.h (rx_decode_opcode) (mvtipl): Add.
1145 (mvtcp, mvfcp, opecp): Remove.
1147 2009-11-02 Paul Brook <paul@codesourcery.com>
1149 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1150 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1151 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1152 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1153 FPU_ARCH_NEON_VFP_V4): Define.
1155 2009-10-23 Doug Evans <dje@sebabeach.org>
1157 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1158 * cgen.h: Update. Improve multi-inclusion macro name.
1160 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1162 * ppc.h (PPC_OPCODE_476): Define.
1164 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1166 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1168 2009-09-29 DJ Delorie <dj@redhat.com>
1172 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1174 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1176 2009-09-21 Ben Elliston <bje@au.ibm.com>
1178 * ppc.h (PPC_OPCODE_PPCA2): New.
1180 2009-09-05 Martin Thuresson <martin@mtme.org>
1182 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1184 2009-08-29 Martin Thuresson <martin@mtme.org>
1186 * tic30.h (template): Rename type template to
1187 insn_template. Updated code to use new name.
1188 * tic54x.h (template): Rename type template to
1191 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1193 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1195 2009-06-11 Anthony Green <green@moxielogic.com>
1197 * moxie.h (MOXIE_F3_PCREL): Define.
1198 (moxie_form3_opc_info): Grow.
1200 2009-06-06 Anthony Green <green@moxielogic.com>
1202 * moxie.h (MOXIE_F1_M): Define.
1204 2009-04-15 Anthony Green <green@moxielogic.com>
1208 2009-04-06 DJ Delorie <dj@redhat.com>
1210 * h8300.h: Add relaxation attributes to MOVA opcodes.
1212 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1214 * ppc.h (ppc_parse_cpu): Declare.
1216 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1218 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1219 and _IMM11 for mbitclr and mbitset.
1220 * score-datadep.h: Update dependency information.
1222 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1224 * ppc.h (PPC_OPCODE_POWER7): New.
1226 2009-02-06 Doug Evans <dje@google.com>
1228 * i386.h: Add comment regarding sse* insns and prefixes.
1230 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1232 * mips.h (INSN_XLR): Define.
1233 (INSN_CHIP_MASK): Update.
1235 (OPCODE_IS_MEMBER): Update.
1236 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1238 2009-01-28 Doug Evans <dje@google.com>
1240 * opcode/i386.h: Add multiple inclusion protection.
1241 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1242 (EDI_REG_NUM): New macros.
1243 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1244 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1245 (REX_PREFIX_P): New macro.
1247 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1249 * ppc.h (struct powerpc_opcode): New field "deprecated".
1250 (PPC_OPCODE_NOPOWER4): Delete.
1252 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1254 * mips.h: Define CPU_R14000, CPU_R16000.
1255 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1257 2008-11-18 Catherine Moore <clm@codesourcery.com>
1259 * arm.h (FPU_NEON_FP16): New.
1260 (FPU_ARCH_NEON_FP16): New.
1262 2008-11-06 Chao-ying Fu <fu@mips.com>
1264 * mips.h: Doucument '1' for 5-bit sync type.
1266 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1268 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1271 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1273 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1275 2008-07-30 Michael J. Eager <eager@eagercon.com>
1277 * ppc.h (PPC_OPCODE_405): Define.
1278 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1280 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1282 * ppc.h (ppc_cpu_t): New typedef.
1283 (struct powerpc_opcode <flags>): Use it.
1284 (struct powerpc_operand <insert, extract>): Likewise.
1285 (struct powerpc_macro <flags>): Likewise.
1287 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1289 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1290 Update comment before MIPS16 field descriptors to mention MIPS16.
1291 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1293 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1294 New bit masks and shift counts for cins and exts.
1296 * mips.h: Document new field descriptors +Q.
1297 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1299 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1301 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1302 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1304 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1306 * ppc.h: (PPC_OPCODE_E500MC): New.
1308 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1310 * i386.h (MAX_OPERANDS): Set to 5.
1311 (MAX_MNEM_SIZE): Changed to 20.
1313 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1315 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1317 2008-03-09 Paul Brook <paul@codesourcery.com>
1319 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1321 2008-03-04 Paul Brook <paul@codesourcery.com>
1323 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1324 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1325 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1327 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1328 Nick Clifton <nickc@redhat.com>
1331 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1332 with a 32-bit displacement but without the top bit of the 4th byte
1335 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1337 * cr16.h (cr16_num_optab): Declared.
1339 2008-02-14 Hakan Ardo <hakan@debian.org>
1342 * avr.h (AVR_ISA_2xxe): Define.
1344 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1346 * mips.h: Update copyright.
1347 (INSN_CHIP_MASK): New macro.
1348 (INSN_OCTEON): New macro.
1349 (CPU_OCTEON): New macro.
1350 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1352 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1354 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1356 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1358 * avr.h (AVR_ISA_USB162): Add new opcode set.
1359 (AVR_ISA_AVR3): Likewise.
1361 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1363 * mips.h (INSN_LOONGSON_2E): New.
1364 (INSN_LOONGSON_2F): New.
1365 (CPU_LOONGSON_2E): New.
1366 (CPU_LOONGSON_2F): New.
1367 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1369 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1371 * mips.h (INSN_ISA*): Redefine certain values as an
1372 enumeration. Update comments.
1373 (mips_isa_table): New.
1374 (ISA_MIPS*): Redefine to match enumeration.
1375 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1378 2007-08-08 Ben Elliston <bje@au.ibm.com>
1380 * ppc.h (PPC_OPCODE_PPCPS): New.
1382 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1384 * m68k.h: Document j K & E.
1386 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1388 * cr16.h: New file for CR16 target.
1390 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1392 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1394 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1396 * m68k.h (mcfisa_c): New.
1397 (mcfusp, mcf_mask): Adjust.
1399 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1401 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1402 (num_powerpc_operands): Declare.
1403 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1404 (PPC_OPERAND_PLUS1): Define.
1406 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1408 * i386.h (REX_MODE64): Renamed to ...
1410 (REX_EXTX): Renamed to ...
1412 (REX_EXTY): Renamed to ...
1414 (REX_EXTZ): Renamed to ...
1417 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1419 * i386.h: Add entries from config/tc-i386.h and move tables
1420 to opcodes/i386-opc.h.
1422 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1424 * i386.h (FloatDR): Removed.
1425 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1427 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1429 * spu-insns.h: Add soma double-float insns.
1431 2007-02-20 Thiemo Seufer <ths@mips.com>
1432 Chao-Ying Fu <fu@mips.com>
1434 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1435 (INSN_DSPR2): Add flag for DSP R2 instructions.
1436 (M_BALIGN): New macro.
1438 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1440 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1441 and Seg3ShortFrom with Shortform.
1443 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386.h (i386_optab): Put the real "test" before the pseudo
1449 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1451 * m68k.h (m68010up): OR fido_a.
1453 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1455 * m68k.h (fido_a): New.
1457 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1459 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1460 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1463 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1465 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1467 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1469 * score-inst.h (enum score_insn_type): Add Insn_internal.
1471 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1472 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1473 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1474 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1475 Alan Modra <amodra@bigpond.net.au>
1477 * spu-insns.h: New file.
1480 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1482 * ppc.h (PPC_OPCODE_CELL): Define.
1484 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1486 * i386.h : Modify opcode to support for the change in POPCNT opcode
1487 in amdfam10 architecture.
1489 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1491 * i386.h: Replace CpuMNI with CpuSSSE3.
1493 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1494 Joseph Myers <joseph@codesourcery.com>
1495 Ian Lance Taylor <ian@wasabisystems.com>
1496 Ben Elliston <bje@wasabisystems.com>
1498 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1500 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1502 * score-datadep.h: New file.
1503 * score-inst.h: New file.
1505 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1507 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1508 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1509 movdq2q and movq2dq.
1511 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1512 Michael Meissner <michael.meissner@amd.com>
1514 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1516 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1518 * i386.h (i386_optab): Add "nop" with memory reference.
1520 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1522 * i386.h (i386_optab): Update comment for 64bit NOP.
1524 2006-06-06 Ben Elliston <bje@au.ibm.com>
1525 Anton Blanchard <anton@samba.org>
1527 * ppc.h (PPC_OPCODE_POWER6): Define.
1530 2006-06-05 Thiemo Seufer <ths@mips.com>
1532 * mips.h: Improve description of MT flags.
1534 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1536 * m68k.h (mcf_mask): Define.
1538 2006-05-05 Thiemo Seufer <ths@mips.com>
1539 David Ung <davidu@mips.com>
1541 * mips.h (enum): Add macro M_CACHE_AB.
1543 2006-05-04 Thiemo Seufer <ths@mips.com>
1544 Nigel Stephens <nigel@mips.com>
1545 David Ung <davidu@mips.com>
1547 * mips.h: Add INSN_SMARTMIPS define.
1549 2006-04-30 Thiemo Seufer <ths@mips.com>
1550 David Ung <davidu@mips.com>
1552 * mips.h: Defines udi bits and masks. Add description of
1553 characters which may appear in the args field of udi
1556 2006-04-26 Thiemo Seufer <ths@networkno.de>
1558 * mips.h: Improve comments describing the bitfield instruction
1561 2006-04-26 Julian Brown <julian@codesourcery.com>
1563 * arm.h (FPU_VFP_EXT_V3): Define constant.
1564 (FPU_NEON_EXT_V1): Likewise.
1565 (FPU_VFP_HARD): Update.
1566 (FPU_VFP_V3): Define macro.
1567 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1569 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1571 * avr.h (AVR_ISA_PWMx): New.
1573 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1575 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1576 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1577 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1578 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1579 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1581 2006-03-10 Paul Brook <paul@codesourcery.com>
1583 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1585 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1587 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1588 first. Correct mask of bb "B" opcode.
1590 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386.h (i386_optab): Support Intel Merom New Instructions.
1594 2006-02-24 Paul Brook <paul@codesourcery.com>
1596 * arm.h: Add V7 feature bits.
1598 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1600 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1602 2006-01-31 Paul Brook <paul@codesourcery.com>
1603 Richard Earnshaw <rearnsha@arm.com>
1605 * arm.h: Use ARM_CPU_FEATURE.
1606 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1607 (arm_feature_set): Change to a structure.
1608 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1609 ARM_FEATURE): New macros.
1611 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1613 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1614 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1615 (ADD_PC_INCR_OPCODE): Don't define.
1617 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1620 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1622 2005-11-14 David Ung <davidu@mips.com>
1624 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1625 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1626 save/restore encoding of the args field.
1628 2005-10-28 Dave Brolley <brolley@redhat.com>
1630 Contribute the following changes:
1631 2005-02-16 Dave Brolley <brolley@redhat.com>
1633 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1634 cgen_isa_mask_* to cgen_bitset_*.
1637 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1639 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1640 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1641 (CGEN_CPU_TABLE): Make isas a ponter.
1643 2003-09-29 Dave Brolley <brolley@redhat.com>
1645 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1646 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1647 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1649 2002-12-13 Dave Brolley <brolley@redhat.com>
1651 * cgen.h (symcat.h): #include it.
1652 (cgen-bitset.h): #include it.
1653 (CGEN_ATTR_VALUE_TYPE): Now a union.
1654 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1655 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1656 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1657 * cgen-bitset.h: New file.
1659 2005-09-30 Catherine Moore <clm@cm00re.com>
1663 2005-10-24 Jan Beulich <jbeulich@novell.com>
1665 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1668 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1670 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1671 Add FLAG_STRICT to pa10 ftest opcode.
1673 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1675 * hppa.h (pa_opcodes): Remove lha entries.
1677 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1679 * hppa.h (FLAG_STRICT): Revise comment.
1680 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1681 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1684 2005-09-30 Catherine Moore <clm@cm00re.com>
1688 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1690 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1692 2005-09-06 Chao-ying Fu <fu@mips.com>
1694 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1695 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1697 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1698 (INSN_ASE_MASK): Update to include INSN_MT.
1699 (INSN_MT): New define for MT ASE.
1701 2005-08-25 Chao-ying Fu <fu@mips.com>
1703 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1704 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1705 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1706 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1707 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1708 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1710 (INSN_DSP): New define for DSP ASE.
1712 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1716 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1718 * ppc.h (PPC_OPCODE_E300): Define.
1720 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1722 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1724 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1727 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1730 2005-07-27 Jan Beulich <jbeulich@novell.com>
1732 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1733 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1734 Add movq-s as 64-bit variants of movd-s.
1736 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1738 * hppa.h: Fix punctuation in comment.
1740 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1741 implicit space-register addressing. Set space-register bits on opcodes
1742 using implicit space-register addressing. Add various missing pa20
1743 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1744 space-register addressing. Use "fE" instead of "fe" in various
1747 2005-07-18 Jan Beulich <jbeulich@novell.com>
1749 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1751 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1753 * i386.h (i386_optab): Support Intel VMX Instructions.
1755 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1757 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1759 2005-07-05 Jan Beulich <jbeulich@novell.com>
1761 * i386.h (i386_optab): Add new insns.
1763 2005-07-01 Nick Clifton <nickc@redhat.com>
1765 * sparc.h: Add typedefs to structure declarations.
1767 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1770 * i386.h (i386_optab): Update comments for 64bit addressing on
1771 mov. Allow 64bit addressing for mov and movq.
1773 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1775 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1776 respectively, in various floating-point load and store patterns.
1778 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1780 * hppa.h (FLAG_STRICT): Correct comment.
1781 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1782 PA 2.0 mneumonics when equivalent. Entries with cache control
1783 completers now require PA 1.1. Adjust whitespace.
1785 2005-05-19 Anton Blanchard <anton@samba.org>
1787 * ppc.h (PPC_OPCODE_POWER5): Define.
1789 2005-05-10 Nick Clifton <nickc@redhat.com>
1791 * Update the address and phone number of the FSF organization in
1792 the GPL notices in the following files:
1793 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1794 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1795 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1796 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1797 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1798 tic54x.h, tic80.h, v850.h, vax.h
1800 2005-05-09 Jan Beulich <jbeulich@novell.com>
1802 * i386.h (i386_optab): Add ht and hnt.
1804 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1806 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1807 Add xcrypt-ctr. Provide aliases without hyphens.
1809 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1811 Moved from ../ChangeLog
1813 2005-04-12 Paul Brook <paul@codesourcery.com>
1814 * m88k.h: Rename psr macros to avoid conflicts.
1816 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1817 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1818 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1819 and ARM_ARCH_V6ZKT2.
1821 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1822 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1823 Remove redundant instruction types.
1824 (struct argument): X_op - new field.
1825 (struct cst4_entry): Remove.
1826 (no_op_insn): Declare.
1828 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1829 * crx.h (enum argtype): Rename types, remove unused types.
1831 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1832 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1833 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1834 (enum operand_type): Rearrange operands, edit comments.
1835 replace us<N> with ui<N> for unsigned immediate.
1836 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1837 displacements (respectively).
1838 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1839 (instruction type): Add NO_TYPE_INS.
1840 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1841 (operand_entry): New field - 'flags'.
1842 (operand flags): New.
1844 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1845 * crx.h (operand_type): Remove redundant types i3, i4,
1847 Add new unsigned immediate types us3, us4, us5, us16.
1849 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1851 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1852 adjust them accordingly.
1854 2005-04-01 Jan Beulich <jbeulich@novell.com>
1856 * i386.h (i386_optab): Add rdtscp.
1858 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1860 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1861 between memory and segment register. Allow movq for moving between
1862 general-purpose register and segment register.
1864 2005-02-09 Jan Beulich <jbeulich@novell.com>
1867 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1868 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1871 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1873 * m68k.h (m68008, m68ec030, m68882): Remove.
1875 (cpu_m68k, cpu_cf): New.
1876 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1877 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1879 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1881 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1882 * cgen.h (enum cgen_parse_operand_type): Add
1883 CGEN_PARSE_OPERAND_SYMBOLIC.
1885 2005-01-21 Fred Fish <fnf@specifixinc.com>
1887 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1888 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1889 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1891 2005-01-19 Fred Fish <fnf@specifixinc.com>
1893 * mips.h (struct mips_opcode): Add new pinfo2 member.
1894 (INSN_ALIAS): New define for opcode table entries that are
1895 specific instances of another entry, such as 'move' for an 'or'
1896 with a zero operand.
1897 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1898 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1900 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1902 * mips.h (CPU_RM9000): Define.
1903 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1905 2004-11-25 Jan Beulich <jbeulich@novell.com>
1907 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1908 to/from test registers are illegal in 64-bit mode. Add missing
1909 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1910 (previously one had to explicitly encode a rex64 prefix). Re-enable
1911 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1912 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1914 2004-11-23 Jan Beulich <jbeulich@novell.com>
1916 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1917 available only with SSE2. Change the MMX additions introduced by SSE
1918 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1919 instructions by their now designated identifier (since combining i686
1920 and 3DNow! does not really imply 3DNow!A).
1922 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1924 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1925 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1927 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1928 Vineet Sharma <vineets@noida.hcltech.com>
1930 * maxq.h: New file: Disassembly information for the maxq port.
1932 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1934 * i386.h (i386_optab): Put back "movzb".
1936 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1938 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1939 comments. Remove member cris_ver_sim. Add members
1940 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1941 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1942 (struct cris_support_reg, struct cris_cond15): New types.
1943 (cris_conds15): Declare.
1944 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1945 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1946 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1947 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1948 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1949 SIZE_FIELD_UNSIGNED.
1951 2004-11-04 Jan Beulich <jbeulich@novell.com>
1953 * i386.h (sldx_Suf): Remove.
1954 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1955 (q_FP): Define, implying no REX64.
1956 (x_FP, sl_FP): Imply FloatMF.
1957 (i386_optab): Split reg and mem forms of moving from segment registers
1958 so that the memory forms can ignore the 16-/32-bit operand size
1959 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1960 all non-floating-point instructions. Unite 32- and 64-bit forms of
1961 movsx, movzx, and movd. Adjust floating point operations for the above
1962 changes to the *FP macros. Add DefaultSize to floating point control
1963 insns operating on larger memory ranges. Remove left over comments
1964 hinting at certain insns being Intel-syntax ones where the ones
1965 actually meant are already gone.
1967 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1969 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1972 2004-09-30 Paul Brook <paul@codesourcery.com>
1974 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1975 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1977 2004-09-11 Theodore A. Roth <troth@openavr.org>
1979 * avr.h: Add support for
1980 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1982 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1984 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1986 2004-08-24 Dmitry Diky <diwil@spec.ru>
1988 * msp430.h (msp430_opc): Add new instructions.
1989 (msp430_rcodes): Declare new instructions.
1990 (msp430_hcodes): Likewise..
1992 2004-08-13 Nick Clifton <nickc@redhat.com>
1995 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1998 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2000 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2002 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2004 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2006 2004-07-21 Jan Beulich <jbeulich@novell.com>
2008 * i386.h: Adjust instruction descriptions to better match the
2011 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2013 * arm.h: Remove all old content. Replace with architecture defines
2014 from gas/config/tc-arm.c.
2016 2004-07-09 Andreas Schwab <schwab@suse.de>
2018 * m68k.h: Fix comment.
2020 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2024 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2026 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2028 2004-05-24 Peter Barada <peter@the-baradas.com>
2030 * m68k.h: Add 'size' to m68k_opcode.
2032 2004-05-05 Peter Barada <peter@the-baradas.com>
2034 * m68k.h: Switch from ColdFire chip name to core variant.
2036 2004-04-22 Peter Barada <peter@the-baradas.com>
2038 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2039 descriptions for new EMAC cases.
2040 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2041 handle Motorola MAC syntax.
2042 Allow disassembly of ColdFire V4e object files.
2044 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2046 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2048 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2050 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2052 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2054 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2056 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2058 * i386.h (i386_optab): Added xstore/xcrypt insns.
2060 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2062 * h8300.h (32bit ldc/stc): Add relaxing support.
2064 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2066 * h8300.h (BITOP): Pass MEMRELAX flag.
2068 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2070 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2073 For older changes see ChangeLog-9103
2075 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2077 Copying and distribution of this file, with or without modification,
2078 are permitted in any medium without royalty provided the copyright
2079 notice and this notice are preserved.
2085 version-control: never