1 2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
3 * i386.h (REX_MODE64): Renamed to ...
5 (REX_EXTX): Renamed to ...
7 (REX_EXTY): Renamed to ...
9 (REX_EXTZ): Renamed to ...
12 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
14 * i386.h: Add entries from config/tc-i386.h and move tables
15 to opcodes/i386-opc.h.
17 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
19 * i386.h (FloatDR): Removed.
20 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
22 2007-03-01 Alan Modra <amodra@bigpond.net.au>
24 * spu-insns.h: Add soma double-float insns.
26 2007-02-20 Thiemo Seufer <ths@mips.com>
27 Chao-Ying Fu <fu@mips.com>
29 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
30 (INSN_DSPR2): Add flag for DSP R2 instructions.
31 (M_BALIGN): New macro.
33 2007-02-14 Alan Modra <amodra@bigpond.net.au>
35 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
36 and Seg3ShortFrom with Shortform.
38 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
41 * i386.h (i386_optab): Put the real "test" before the pseudo
44 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
46 * m68k.h (m68010up): OR fido_a.
48 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
50 * m68k.h (fido_a): New.
52 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
54 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
55 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
58 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
60 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
62 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
64 * score-inst.h (enum score_insn_type): Add Insn_internal.
66 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
67 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
68 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
69 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
70 Alan Modra <amodra@bigpond.net.au>
72 * spu-insns.h: New file.
75 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
77 * ppc.h (PPC_OPCODE_CELL): Define.
79 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
81 * i386.h : Modify opcode to support for the change in POPCNT opcode
82 in amdfam10 architecture.
84 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
86 * i386.h: Replace CpuMNI with CpuSSSE3.
88 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
89 Joseph Myers <joseph@codesourcery.com>
90 Ian Lance Taylor <ian@wasabisystems.com>
91 Ben Elliston <bje@wasabisystems.com>
93 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
95 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
97 * score-datadep.h: New file.
98 * score-inst.h: New file.
100 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
102 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
103 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
106 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
107 Michael Meissner <michael.meissner@amd.com>
109 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
111 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
113 * i386.h (i386_optab): Add "nop" with memory reference.
115 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
117 * i386.h (i386_optab): Update comment for 64bit NOP.
119 2006-06-06 Ben Elliston <bje@au.ibm.com>
120 Anton Blanchard <anton@samba.org>
122 * ppc.h (PPC_OPCODE_POWER6): Define.
125 2006-06-05 Thiemo Seufer <ths@mips.com>
127 * mips.h: Improve description of MT flags.
129 2006-05-25 Richard Sandiford <richard@codesourcery.com>
131 * m68k.h (mcf_mask): Define.
133 2006-05-05 Thiemo Seufer <ths@mips.com>
134 David Ung <davidu@mips.com>
136 * mips.h (enum): Add macro M_CACHE_AB.
138 2006-05-04 Thiemo Seufer <ths@mips.com>
139 Nigel Stephens <nigel@mips.com>
140 David Ung <davidu@mips.com>
142 * mips.h: Add INSN_SMARTMIPS define.
144 2006-04-30 Thiemo Seufer <ths@mips.com>
145 David Ung <davidu@mips.com>
147 * mips.h: Defines udi bits and masks. Add description of
148 characters which may appear in the args field of udi
151 2006-04-26 Thiemo Seufer <ths@networkno.de>
153 * mips.h: Improve comments describing the bitfield instruction
156 2006-04-26 Julian Brown <julian@codesourcery.com>
158 * arm.h (FPU_VFP_EXT_V3): Define constant.
159 (FPU_NEON_EXT_V1): Likewise.
160 (FPU_VFP_HARD): Update.
161 (FPU_VFP_V3): Define macro.
162 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
164 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
166 * avr.h (AVR_ISA_PWMx): New.
168 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
170 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
171 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
172 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
173 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
174 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
176 2006-03-10 Paul Brook <paul@codesourcery.com>
178 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
180 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
182 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
183 first. Correct mask of bb "B" opcode.
185 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
187 * i386.h (i386_optab): Support Intel Merom New Instructions.
189 2006-02-24 Paul Brook <paul@codesourcery.com>
191 * arm.h: Add V7 feature bits.
193 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
195 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
197 2006-01-31 Paul Brook <paul@codesourcery.com>
198 Richard Earnshaw <rearnsha@arm.com>
200 * arm.h: Use ARM_CPU_FEATURE.
201 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
202 (arm_feature_set): Change to a structure.
203 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
204 ARM_FEATURE): New macros.
206 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
208 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
209 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
210 (ADD_PC_INCR_OPCODE): Don't define.
212 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
215 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
217 2005-11-14 David Ung <davidu@mips.com>
219 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
220 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
221 save/restore encoding of the args field.
223 2005-10-28 Dave Brolley <brolley@redhat.com>
225 Contribute the following changes:
226 2005-02-16 Dave Brolley <brolley@redhat.com>
228 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
229 cgen_isa_mask_* to cgen_bitset_*.
232 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
234 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
235 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
236 (CGEN_CPU_TABLE): Make isas a ponter.
238 2003-09-29 Dave Brolley <brolley@redhat.com>
240 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
241 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
242 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
244 2002-12-13 Dave Brolley <brolley@redhat.com>
246 * cgen.h (symcat.h): #include it.
247 (cgen-bitset.h): #include it.
248 (CGEN_ATTR_VALUE_TYPE): Now a union.
249 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
250 (CGEN_ATTR_ENTRY): 'value' now unsigned.
251 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
252 * cgen-bitset.h: New file.
254 2005-09-30 Catherine Moore <clm@cm00re.com>
258 2005-10-24 Jan Beulich <jbeulich@novell.com>
260 * ia64.h (enum ia64_opnd): Move memory operand out of set of
263 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
265 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
266 Add FLAG_STRICT to pa10 ftest opcode.
268 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
270 * hppa.h (pa_opcodes): Remove lha entries.
272 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
274 * hppa.h (FLAG_STRICT): Revise comment.
275 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
276 before corresponding pa11 opcodes. Add strict pa10 register-immediate
279 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
281 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
283 2005-09-06 Chao-ying Fu <fu@mips.com>
285 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
286 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
288 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
289 (INSN_ASE_MASK): Update to include INSN_MT.
290 (INSN_MT): New define for MT ASE.
292 2005-08-25 Chao-ying Fu <fu@mips.com>
294 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
295 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
296 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
297 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
298 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
299 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
301 (INSN_DSP): New define for DSP ASE.
303 2005-08-18 Alan Modra <amodra@bigpond.net.au>
307 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
309 * ppc.h (PPC_OPCODE_E300): Define.
311 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
313 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
315 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
318 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
321 2005-07-27 Jan Beulich <jbeulich@novell.com>
323 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
324 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
325 Add movq-s as 64-bit variants of movd-s.
327 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
329 * hppa.h: Fix punctuation in comment.
331 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
332 implicit space-register addressing. Set space-register bits on opcodes
333 using implicit space-register addressing. Add various missing pa20
334 long-immediate opcodes. Remove various opcodes using implicit 3-bit
335 space-register addressing. Use "fE" instead of "fe" in various
338 2005-07-18 Jan Beulich <jbeulich@novell.com>
340 * i386.h (i386_optab): Operands of aam and aad are unsigned.
342 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
344 * i386.h (i386_optab): Support Intel VMX Instructions.
346 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
348 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
350 2005-07-05 Jan Beulich <jbeulich@novell.com>
352 * i386.h (i386_optab): Add new insns.
354 2005-07-01 Nick Clifton <nickc@redhat.com>
356 * sparc.h: Add typedefs to structure declarations.
358 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
361 * i386.h (i386_optab): Update comments for 64bit addressing on
362 mov. Allow 64bit addressing for mov and movq.
364 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
366 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
367 respectively, in various floating-point load and store patterns.
369 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
371 * hppa.h (FLAG_STRICT): Correct comment.
372 (pa_opcodes): Update load and store entries to allow both PA 1.X and
373 PA 2.0 mneumonics when equivalent. Entries with cache control
374 completers now require PA 1.1. Adjust whitespace.
376 2005-05-19 Anton Blanchard <anton@samba.org>
378 * ppc.h (PPC_OPCODE_POWER5): Define.
380 2005-05-10 Nick Clifton <nickc@redhat.com>
382 * Update the address and phone number of the FSF organization in
383 the GPL notices in the following files:
384 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
385 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
386 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
387 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
388 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
389 tic54x.h, tic80.h, v850.h, vax.h
391 2005-05-09 Jan Beulich <jbeulich@novell.com>
393 * i386.h (i386_optab): Add ht and hnt.
395 2005-04-18 Mark Kettenis <kettenis@gnu.org>
397 * i386.h: Insert hyphens into selected VIA PadLock extensions.
398 Add xcrypt-ctr. Provide aliases without hyphens.
400 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
402 Moved from ../ChangeLog
404 2005-04-12 Paul Brook <paul@codesourcery.com>
405 * m88k.h: Rename psr macros to avoid conflicts.
407 2005-03-12 Zack Weinberg <zack@codesourcery.com>
408 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
409 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
412 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
413 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
414 Remove redundant instruction types.
415 (struct argument): X_op - new field.
416 (struct cst4_entry): Remove.
417 (no_op_insn): Declare.
419 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
420 * crx.h (enum argtype): Rename types, remove unused types.
422 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
423 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
424 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
425 (enum operand_type): Rearrange operands, edit comments.
426 replace us<N> with ui<N> for unsigned immediate.
427 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
428 displacements (respectively).
429 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
430 (instruction type): Add NO_TYPE_INS.
431 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
432 (operand_entry): New field - 'flags'.
433 (operand flags): New.
435 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
436 * crx.h (operand_type): Remove redundant types i3, i4,
438 Add new unsigned immediate types us3, us4, us5, us16.
440 2005-04-12 Mark Kettenis <kettenis@gnu.org>
442 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
443 adjust them accordingly.
445 2005-04-01 Jan Beulich <jbeulich@novell.com>
447 * i386.h (i386_optab): Add rdtscp.
449 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
451 * i386.h (i386_optab): Don't allow the `l' suffix for moving
452 between memory and segment register. Allow movq for moving between
453 general-purpose register and segment register.
455 2005-02-09 Jan Beulich <jbeulich@novell.com>
458 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
459 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
462 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
464 * m68k.h (m68008, m68ec030, m68882): Remove.
466 (cpu_m68k, cpu_cf): New.
467 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
468 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
470 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
472 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
473 * cgen.h (enum cgen_parse_operand_type): Add
474 CGEN_PARSE_OPERAND_SYMBOLIC.
476 2005-01-21 Fred Fish <fnf@specifixinc.com>
478 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
479 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
480 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
482 2005-01-19 Fred Fish <fnf@specifixinc.com>
484 * mips.h (struct mips_opcode): Add new pinfo2 member.
485 (INSN_ALIAS): New define for opcode table entries that are
486 specific instances of another entry, such as 'move' for an 'or'
488 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
489 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
491 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
493 * mips.h (CPU_RM9000): Define.
494 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
496 2004-11-25 Jan Beulich <jbeulich@novell.com>
498 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
499 to/from test registers are illegal in 64-bit mode. Add missing
500 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
501 (previously one had to explicitly encode a rex64 prefix). Re-enable
502 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
503 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
505 2004-11-23 Jan Beulich <jbeulich@novell.com>
507 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
508 available only with SSE2. Change the MMX additions introduced by SSE
509 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
510 instructions by their now designated identifier (since combining i686
511 and 3DNow! does not really imply 3DNow!A).
513 2004-11-19 Alan Modra <amodra@bigpond.net.au>
515 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
516 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
518 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
519 Vineet Sharma <vineets@noida.hcltech.com>
521 * maxq.h: New file: Disassembly information for the maxq port.
523 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
525 * i386.h (i386_optab): Put back "movzb".
527 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
529 * cris.h (enum cris_insn_version_usage): Tweak formatting and
530 comments. Remove member cris_ver_sim. Add members
531 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
532 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
533 (struct cris_support_reg, struct cris_cond15): New types.
534 (cris_conds15): Declare.
535 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
536 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
537 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
538 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
539 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
542 2004-11-04 Jan Beulich <jbeulich@novell.com>
544 * i386.h (sldx_Suf): Remove.
545 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
546 (q_FP): Define, implying no REX64.
547 (x_FP, sl_FP): Imply FloatMF.
548 (i386_optab): Split reg and mem forms of moving from segment registers
549 so that the memory forms can ignore the 16-/32-bit operand size
550 distinction. Adjust a few others for Intel mode. Remove *FP uses from
551 all non-floating-point instructions. Unite 32- and 64-bit forms of
552 movsx, movzx, and movd. Adjust floating point operations for the above
553 changes to the *FP macros. Add DefaultSize to floating point control
554 insns operating on larger memory ranges. Remove left over comments
555 hinting at certain insns being Intel-syntax ones where the ones
556 actually meant are already gone.
558 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
560 * crx.h: Add COPS_REG_INS - Coprocessor Special register
563 2004-09-30 Paul Brook <paul@codesourcery.com>
565 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
566 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
568 2004-09-11 Theodore A. Roth <troth@openavr.org>
570 * avr.h: Add support for
571 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
573 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
575 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
577 2004-08-24 Dmitry Diky <diwil@spec.ru>
579 * msp430.h (msp430_opc): Add new instructions.
580 (msp430_rcodes): Declare new instructions.
581 (msp430_hcodes): Likewise..
583 2004-08-13 Nick Clifton <nickc@redhat.com>
586 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
589 2004-08-30 Michal Ludvig <mludvig@suse.cz>
591 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
593 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
595 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
597 2004-07-21 Jan Beulich <jbeulich@novell.com>
599 * i386.h: Adjust instruction descriptions to better match the
602 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
604 * arm.h: Remove all old content. Replace with architecture defines
605 from gas/config/tc-arm.c.
607 2004-07-09 Andreas Schwab <schwab@suse.de>
609 * m68k.h: Fix comment.
611 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
615 2004-06-24 Alan Modra <amodra@bigpond.net.au>
617 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
619 2004-05-24 Peter Barada <peter@the-baradas.com>
621 * m68k.h: Add 'size' to m68k_opcode.
623 2004-05-05 Peter Barada <peter@the-baradas.com>
625 * m68k.h: Switch from ColdFire chip name to core variant.
627 2004-04-22 Peter Barada <peter@the-baradas.com>
629 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
630 descriptions for new EMAC cases.
631 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
632 handle Motorola MAC syntax.
633 Allow disassembly of ColdFire V4e object files.
635 2004-03-16 Alan Modra <amodra@bigpond.net.au>
637 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
639 2004-03-12 Jakub Jelinek <jakub@redhat.com>
641 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
643 2004-03-12 Michal Ludvig <mludvig@suse.cz>
645 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
647 2004-03-12 Michal Ludvig <mludvig@suse.cz>
649 * i386.h (i386_optab): Added xstore/xcrypt insns.
651 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
653 * h8300.h (32bit ldc/stc): Add relaxing support.
655 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
657 * h8300.h (BITOP): Pass MEMRELAX flag.
659 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
661 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
664 For older changes see ChangeLog-9103
670 version-control: never