include/opcode/ChangeLog

   1 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
   4         Use "source" rather than "destination" for microMIPS "G".
   5
   6 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
   7
   8         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
   9         values.
  10
  11 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  12
  13         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  14
  15 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  16             Maciej W. Rozycki  <macro@codesourcery.com>
  17             Chao-Ying Fu  <fu@mips.com>
  18
  19         * mips.h (OP_SH_EVAOFFSET): Define.
  20         (OP_MASK_EVAOFFSET): Define.
  21         (INSN_ASE_MASK): Delete.
  22         (ASE_EVA): Define.
  23         (M_CACHEE_AB, M_CACHEE_OB): New.
  24         (M_LBE_OB, M_LBE_AB): New.
  25         (M_LBUE_OB, M_LBUE_AB): New.
  26         (M_LHE_OB, M_LHE_AB): New.
  27         (M_LHUE_OB, M_LHUE_AB): New.
  28         (M_LLE_AB, M_LLE_OB): New.
  29         (M_LWE_OB, M_LWE_AB): New.
  30         (M_LWLE_AB, M_LWLE_OB): New.
  31         (M_LWRE_AB, M_LWRE_OB): New.
  32         (M_PREFE_AB, M_PREFE_OB): New.
  33         (M_SCE_AB, M_SCE_OB): New.
  34         (M_SBE_OB, M_SBE_AB): New.
  35         (M_SHE_OB, M_SHE_AB): New.
  36         (M_SWE_OB, M_SWE_AB): New.
  37         (M_SWLE_AB, M_SWLE_OB): New.
  38         (M_SWRE_AB, M_SWRE_OB): New.
  39         (MICROMIPSOP_SH_EVAOFFSET): Define.
  40         (MICROMIPSOP_MASK_EVAOFFSET): Define.
  41
  42 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
  43
  44         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
  45
  46 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
  47
  48         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
  49
  50 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  51
  52         * mips.h (OP_MASK_CODE10): Correct definition.
  53         (OP_SH_CODE10): Likewise.
  54         Add a comment that "+J" is used now for OP_*CODE10.
  55         (INSN_ASE_MASK): Update.
  56         (INSN_VIRT): New macro.
  57         (INSN_VIRT64): New macro
  58
  59 2013-05-02  Nick Clifton  <nickc@redhat.com>
  60
  61         * msp430.h: Add patterns for MSP430X instructions.
  62
  63 2013-04-06  David S. Miller  <davem@davemloft.net>
  64
  65         * sparc.h (F_PREFERRED): Define.
  66         (F_PREF_ALIAS): Define.
  67
  68 2013-04-03  Nick Clifton  <nickc@redhat.com>
  69
  70         * v850.h (V850_INVERSE_PCREL): Define.
  71
  72 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  73
  74         PR binutils/15068
  75         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
  76
  77 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  78
  79         PR binutils/15068
  80         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
  81         Add 16-bit opcodes.
  82         * tic6xc-opcode-table.h: Add 16-bit insns.
  83         * tic6x.h: Add support for 16-bit insns.
  84
  85 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
  86
  87         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
  88         and mov.b/w/l Rs,@(d:32,ERd).
  89
  90 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  91
  92         PR gas/15082
  93         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
  94         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
  95         tic6x_operand_xregpair operand coding type.
  96         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
  97         opcode field, usu ORXREGD1324 for the src2 operand and remove the
  98         TIC6X_FLAG_NO_CROSS.
  99
 100 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 101
 102         PR gas/15095
 103         * tic6x.h (enum tic6x_coding_method): Add
 104         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 105         separately the msb and lsb of a register pair.  This is needed to
 106         encode the opcodes in the same way as TI assembler does.
 107         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 108         and rsqrdp opcodes to use the new field coding types.
 109
 110 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 111
 112         * arm.h (CRC_EXT_ARMV8): New constant.
 113         (ARCH_CRC_ARMV8): New macro.
 114
 115 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 116
 117         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 118
 119 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 120             Andrew Jenner <andrew@codesourcery.com>
 121
 122         Based on patches from Altera Corporation.
 123
 124         * nios2.h: New file.
 125
 126 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 127
 128         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 129
 130 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 131
 132         PR gas/15069
 133         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 134
 135 2013-01-24  Nick Clifton  <nickc@redhat.com>
 136
 137         * v850.h: Add e3v5 support.
 138
 139 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 140
 141         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 142
 143 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 144
 145         * ppc.h (PPC_OPCODE_POWER8): New define.
 146         (PPC_OPCODE_HTM): Likewise.
 147
 148 2013-01-10  Will Newton <will.newton@imgtec.com>
 149
 150         * metag.h: New file.
 151
 152 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 153
 154         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 155         (match_opcode): Rename to cr16_match_opcode.
 156
 157 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 158
 159         * mips.h: Add support for r5900 instructions including lq and sq.
 160
 161 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 162
 163         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 164         (make_instruction,match_opcode): Added function prototypes.
 165         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 166
 167 2012-11-23  Alan Modra  <amodra@gmail.com>
 168
 169         * ppc.h (ppc_parse_cpu): Update prototype.
 170
 171 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 172
 173         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 174         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 175
 176 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 177
 178         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 179
 180 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 181
 182         * ia64.h (ia64_opnd): Add new operand types.
 183
 184 2012-08-21  David S. Miller  <davem@davemloft.net>
 185
 186         * sparc.h (F3F4): New macro.
 187
 188 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 189             Laurent Desnogues  <laurent.desnogues@arm.com>
 190             Jim MacArthur  <jim.macarthur@arm.com>
 191             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 192             Nigel Stephens  <nigel.stephens@arm.com>
 193             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 194             Richard Earnshaw  <rearnsha@arm.com>
 195             Sofiane Naci  <sofiane.naci@arm.com>
 196             Tejas Belagod  <tejas.belagod@arm.com>
 197             Yufeng Zhang  <yufeng.zhang@arm.com>
 198
 199         * aarch64.h: New file.
 200
 201 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 202             Maciej W. Rozycki  <macro@codesourcery.com>
 203
 204         * mips.h (mips_opcode): Add the exclusions field.
 205         (OPCODE_IS_MEMBER): Remove macro.
 206         (cpu_is_member): New inline function.
 207         (opcode_is_member): Likewise.
 208
 209 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 210             Catherine Moore  <clm@codesourcery.com>
 211             Maciej W. Rozycki  <macro@codesourcery.com>
 212
 213         * mips.h: Document microMIPS DSP ASE usage.
 214         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 215         microMIPS DSP ASE support.
 216         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 217         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 218         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 219         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 220         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 221         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 222         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 223
 224 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 225
 226         * mips.h: Fix a typo in description.
 227
 228 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 229
 230         * avr.h: (AVR_ISA_XCH): New define.
 231         (AVR_ISA_XMEGA): Use it.
 232         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 233
 234 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 235
 236         * m68hc11.h: Add XGate definitions.
 237         (struct m68hc11_opcode): Add xg_mask field.
 238
 239 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 240             Maciej W. Rozycki  <macro@codesourcery.com>
 241             Rhonda Wittels  <rhonda@codesourcery.com>
 242
 243         * ppc.h (PPC_OPCODE_VLE): New definition.
 244         (PPC_OP_SA): New macro.
 245         (PPC_OP_SE_VLE): New macro.
 246         (PPC_OP): Use a variable shift amount.
 247         (powerpc_operand): Update comments.
 248         (PPC_OPSHIFT_INV): New macro.
 249         (PPC_OPERAND_CR): Replace with...
 250         (PPC_OPERAND_CR_BIT): ...this and
 251         (PPC_OPERAND_CR_REG): ...this.
 252
 253
 254 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 255
 256         * xgate.h: Header file for XGATE assembler.
 257
 258 2012-04-27  David S. Miller  <davem@davemloft.net>
 259
 260         * sparc.h: Document new arg code' )' for crypto RS3
 261         immediates.
 262
 263         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 264         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 265         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 266         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 267         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 268         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 269         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 270         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 271         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 272         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 273         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 274
 275 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 276
 277         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 278
 279 2012-02-27  Alan Modra  <amodra@gmail.com>
 280
 281         * crx.h (cst4_map): Update declaration.
 282
 283 2012-02-25  Walter Lee  <walt@tilera.com>
 284
 285         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 286         TILEGX_OPC_LD_TLS.
 287         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 288         TILEPRO_OPC_LW_TLS_SN.
 289
 290 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 293         (XRELEASE_PREFIX_OPCODE): Likewise.
 294
 295 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 296             Adam Nemet  <anemet@caviumnetworks.com>
 297
 298         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 299         (INSN_OCTEON2): New macro.
 300         (CPU_OCTEON2): New macro.
 301         (OPCODE_IS_MEMBER): Add Octeon2.
 302
 303 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 304
 305         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 306         (INSN_OCTEONP): New macro.
 307         (CPU_OCTEONP): New macro.
 308         (OPCODE_IS_MEMBER): Add Octeon+.
 309         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 310
 311 2011-11-01  DJ Delorie  <dj@redhat.com>
 312
 313         * rl78.h: New file.
 314
 315 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 316
 317         * mips.h: Fix a typo in description.
 318
 319 2011-09-21  David S. Miller  <davem@davemloft.net>
 320
 321         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 322         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 323         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 324         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 325
 326 2011-08-09  Chao-ying Fu  <fu@mips.com>
 327             Maciej W. Rozycki  <macro@codesourcery.com>
 328
 329         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 330         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 331         (INSN_ASE_MASK): Add the MCU bit.
 332         (INSN_MCU): New macro.
 333         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 334         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 335
 336 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 337
 338         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 339         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 340         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 341         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 342         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 343         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 344         (INSN2_READ_GPR_MMN): Likewise.
 345         (INSN2_READ_FPR_D): Change the bit used.
 346         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 347         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 348         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 349         (INSN2_COND_BRANCH): Likewise.
 350         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 351         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 352         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 353         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 354         (INSN2_MOD_GPR_MN): Likewise.
 355
 356 2011-08-05  David S. Miller  <davem@davemloft.net>
 357
 358         * sparc.h: Document new format codes '4', '5', and '('.
 359         (OPF_LOW4, RS3): New macros.
 360
 361 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 362
 363         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 364         order of flags documented.
 365
 366 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 367
 368         * mips.h: Clarify the description of microMIPS instruction
 369         manipulation macros.
 370         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 371
 372 2011-07-24  Chao-ying Fu  <fu@mips.com>
 373             Maciej W. Rozycki  <macro@codesourcery.com>
 374
 375         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 376         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 377         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 378         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 379         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 380         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 381         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 382         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 383         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 384         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 385         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 386         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 387         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 388         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 389         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 390         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 391         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 392         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 393         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 394         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 395         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 396         (INSN_WRITE_GPR_S): New macro.
 397         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 398         (INSN2_READ_FPR_D): Likewise.
 399         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 400         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 401         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 402         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 403         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 404         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 405         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 406         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 407         (CPU_MICROMIPS): New macro.
 408         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 409         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 410         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 411         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 412         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 413         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 414         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 415         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 416         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 417         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 418         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 419         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 420         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 421         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 422         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 423         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 424         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 425         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 426         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 427         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 428         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 429         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 430         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 431         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 432         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 433         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 434         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 435         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 436         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 437         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 438         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 439         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 440         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 441         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 442         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 443         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 444         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 445         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 446         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 447         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 448         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 449         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 450         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 451         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 452         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 453         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 454         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 455         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 456         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 457         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 458         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 459         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 460         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 461         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 462         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 463         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 464         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 465         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 466         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 467         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 468         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 469         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 470         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 471         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 472         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 473         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 474         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 475         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 476         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 477         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 478         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 479         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 480         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 481         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 482         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 483         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 484         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 485         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 486         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 487         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 488         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 489         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 490         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 491         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 492         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 493         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 494         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 495         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 496         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 497         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 498         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 499         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 500         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 501         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 502         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 503         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 504         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 505         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 506         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 507         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 508         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 509         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 510         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 511         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 512         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 513         (micromips_opcodes): New declaration.
 514         (bfd_micromips_num_opcodes): Likewise.
 515
 516 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 517
 518         * mips.h (INSN_TRAP): Rename to...
 519         (INSN_NO_DELAY_SLOT): ... this.
 520         (INSN_SYNC): Remove macro.
 521
 522 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 523
 524         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 525         a duplicate of AVR_ISA_SPM.
 526
 527 2011-07-01  Nick Clifton  <nickc@redhat.com>
 528
 529         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 530
 531 2011-06-18  Robin Getz  <robin.getz@analog.com>
 532
 533         * bfin.h (is_macmod_signed): New func
 534
 535 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 536
 537         * bfin.h (is_macmod_pmove): Add missing space before func args.
 538         (is_macmod_hmove): Likewise.
 539
 540 2011-06-13  Walter Lee  <walt@tilera.com>
 541
 542         * tilegx.h: New file.
 543         * tilepro.h: New file.
 544
 545 2011-05-31  Paul Brook  <paul@codesourcery.com>
 546
 547         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 548
 549 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 550
 551         * s390.h: Replace S390_OPERAND_REG_EVEN with
 552         S390_OPERAND_REG_PAIR.
 553
 554 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 555
 556         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 557
 558 2011-04-18  Julian Brown  <julian@codesourcery.com>
 559
 560         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 561
 562 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 563
 564         PR gas/12296
 565         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 566
 567 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 568
 569         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 570         New instruction set flags.
 571         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 572
 573 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 574
 575         * mips.h (M_PREF_AB): New enum value.
 576
 577 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 578
 579         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 580         M_IU): Define.
 581         (is_macmod_pmove, is_macmod_hmove): New functions.
 582
 583 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 584
 585         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 586
 587 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 588
 589         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 590         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 591
 592 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 593
 594         PR gas/11395
 595         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 596         "bb" entries.
 597
 598 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 599
 600         PR gas/11395
 601         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 602
 603 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 604
 605         * mips.h: Update commentary after last commit.
 606
 607 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 608
 609         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 610         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 611         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 612
 613 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 614
 615         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 616
 617 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 618
 619         * mips.h: Fix previous commit.
 620
 621 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 622
 623         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 624         (INSN_LOONGSON_3A): Clear bit 31.
 625
 626 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 627
 628         PR gas/12198
 629         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 630         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 631         (ARM_ARCH_V6M_ONLY): New define.
 632
 633 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 634
 635         * mips.h (INSN_LOONGSON_3A): Defined.
 636         (CPU_LOONGSON_3A): Defined.
 637         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 638
 639 2010-10-09  Matt Rice  <ratmice@gmail.com>
 640
 641         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 642         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 643
 644 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 645
 646         * arm.h (ARM_EXT_VIRT): New define.
 647         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 648         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 649         Extensions.
 650
 651 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 652
 653         * arm.h (ARM_AEXT_ADIV): New define.
 654         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 655
 656 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 657
 658         * arm.h (ARM_EXT_OS): New define.
 659         (ARM_AEXT_V6SM): Likewise.
 660         (ARM_ARCH_V6SM): Likewise.
 661
 662 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 663
 664         * arm.h (ARM_EXT_MP): Add.
 665         (ARM_ARCH_V7A_MP): Likewise.
 666
 667 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 668
 669         * bfin.h: Declare pseudoChr structs/defines.
 670
 671 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 672
 673         * bfin.h: Strip trailing whitespace.
 674
 675 2010-07-29  DJ Delorie  <dj@redhat.com>
 676
 677         * rx.h (RX_Operand_Type): Add TwoReg.
 678         (RX_Opcode_ID): Remove ediv and ediv2.
 679
 680 2010-07-27  DJ Delorie  <dj@redhat.com>
 681
 682         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 683
 684 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 685             Ina Pandit  <ina.pandit@kpitcummins.com>
 686
 687         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 688         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 689         PROCESSOR_V850E2_ALL.
 690         Remove PROCESSOR_V850EA support.
 691         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 692         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 693         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 694         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 695         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 696         V850_OPERAND_PERCENT.
 697         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 698         V850_NOT_R0.
 699         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 700         and V850E_PUSH_POP
 701
 702 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 703
 704         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 705         (MIPS16_INSN_BRANCH): Rename to...
 706         (MIPS16_INSN_COND_BRANCH): ... this.
 707
 708 2010-07-03  Alan Modra  <amodra@gmail.com>
 709
 710         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 711         Renumber other PPC_OPCODE defines.
 712
 713 2010-07-03  Alan Modra  <amodra@gmail.com>
 714
 715         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 716
 717 2010-06-29  Alan Modra  <amodra@gmail.com>
 718
 719         * maxq.h: Delete file.
 720
 721 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 722
 723         * ppc.h (PPC_OPCODE_E500): Define.
 724
 725 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 726
 727         * opcode/mips.h (INSN_MIPS16): Remove.
 728
 729 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 730
 731         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 732
 733 2010-04-15  Nick Clifton  <nickc@redhat.com>
 734
 735         * alpha.h: Update copyright notice to use GPLv3.
 736         * arc.h: Likewise.
 737         * arm.h: Likewise.
 738         * avr.h: Likewise.
 739         * bfin.h: Likewise.
 740         * cgen.h: Likewise.
 741         * convex.h: Likewise.
 742         * cr16.h: Likewise.
 743         * cris.h: Likewise.
 744         * crx.h: Likewise.
 745         * d10v.h: Likewise.
 746         * d30v.h: Likewise.
 747         * dlx.h: Likewise.
 748         * h8300.h: Likewise.
 749         * hppa.h: Likewise.
 750         * i370.h: Likewise.
 751         * i386.h: Likewise.
 752         * i860.h: Likewise.
 753         * i960.h: Likewise.
 754         * ia64.h: Likewise.
 755         * m68hc11.h: Likewise.
 756         * m68k.h: Likewise.
 757         * m88k.h: Likewise.
 758         * maxq.h: Likewise.
 759         * mips.h: Likewise.
 760         * mmix.h: Likewise.
 761         * mn10200.h: Likewise.
 762         * mn10300.h: Likewise.
 763         * msp430.h: Likewise.
 764         * np1.h: Likewise.
 765         * ns32k.h: Likewise.
 766         * or32.h: Likewise.
 767         * pdp11.h: Likewise.
 768         * pj.h: Likewise.
 769         * pn.h: Likewise.
 770         * ppc.h: Likewise.
 771         * pyr.h: Likewise.
 772         * rx.h: Likewise.
 773         * s390.h: Likewise.
 774         * score-datadep.h: Likewise.
 775         * score-inst.h: Likewise.
 776         * sparc.h: Likewise.
 777         * spu-insns.h: Likewise.
 778         * spu.h: Likewise.
 779         * tic30.h: Likewise.
 780         * tic4x.h: Likewise.
 781         * tic54x.h: Likewise.
 782         * tic80.h: Likewise.
 783         * v850.h: Likewise.
 784         * vax.h: Likewise.
 785
 786 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 787
 788         * tic6x-control-registers.h, tic6x-insn-formats.h,
 789         tic6x-opcode-table.h, tic6x.h: New.
 790
 791 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 792
 793         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 794
 795 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 796
 797         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 798
 799 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 800
 801         * ia64.h (ia64_find_opcode): Remove argument name.
 802         (ia64_find_next_opcode): Likewise.
 803         (ia64_dis_opcode): Likewise.
 804         (ia64_free_opcode): Likewise.
 805         (ia64_find_dependency): Likewise.
 806
 807 2009-11-22  Doug Evans  <dje@sebabeach.org>
 808
 809         * cgen.h: Include bfd_stdint.h.
 810         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 811
 812 2009-11-18  Paul Brook  <paul@codesourcery.com>
 813
 814         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 815
 816 2009-11-17  Paul Brook  <paul@codesourcery.com>
 817         Daniel Jacobowitz  <dan@codesourcery.com>
 818
 819         * arm.h (ARM_EXT_V6_DSP): Define.
 820         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 821         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 822
 823 2009-11-04  DJ Delorie  <dj@redhat.com>
 824
 825         * rx.h (rx_decode_opcode) (mvtipl): Add.
 826         (mvtcp, mvfcp, opecp): Remove.
 827
 828 2009-11-02  Paul Brook  <paul@codesourcery.com>
 829
 830         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 831         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 832         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 833         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 834         FPU_ARCH_NEON_VFP_V4): Define.
 835
 836 2009-10-23  Doug Evans  <dje@sebabeach.org>
 837
 838         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 839         * cgen.h: Update.  Improve multi-inclusion macro name.
 840
 841 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 842
 843         * ppc.h (PPC_OPCODE_476): Define.
 844
 845 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 846
 847         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 848
 849 2009-09-29  DJ Delorie  <dj@redhat.com>
 850
 851         * rx.h: New file.
 852
 853 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 854
 855         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 856
 857 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 858
 859         * ppc.h (PPC_OPCODE_PPCA2): New.
 860
 861 2009-09-05  Martin Thuresson  <martin@mtme.org>
 862
 863         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 864
 865 2009-08-29  Martin Thuresson  <martin@mtme.org>
 866
 867         * tic30.h (template): Rename type template to
 868         insn_template. Updated code to use new name.
 869         * tic54x.h (template): Rename type template to
 870         insn_template.
 871
 872 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 873
 874         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 875
 876 2009-06-11  Anthony Green  <green@moxielogic.com>
 877
 878         * moxie.h (MOXIE_F3_PCREL): Define.
 879         (moxie_form3_opc_info): Grow.
 880
 881 2009-06-06  Anthony Green  <green@moxielogic.com>
 882
 883         * moxie.h (MOXIE_F1_M): Define.
 884
 885 2009-04-15  Anthony Green  <green@moxielogic.com>
 886
 887         * moxie.h: Created.
 888
 889 2009-04-06  DJ Delorie  <dj@redhat.com>
 890
 891         * h8300.h: Add relaxation attributes to MOVA opcodes.
 892
 893 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 894
 895         * ppc.h (ppc_parse_cpu): Declare.
 896
 897 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 898
 899         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 900         and _IMM11 for mbitclr and mbitset.
 901         * score-datadep.h: Update dependency information.
 902
 903 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 904
 905         * ppc.h (PPC_OPCODE_POWER7): New.
 906
 907 2009-02-06  Doug Evans  <dje@google.com>
 908
 909         * i386.h: Add comment regarding sse* insns and prefixes.
 910
 911 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 912
 913         * mips.h (INSN_XLR): Define.
 914         (INSN_CHIP_MASK): Update.
 915         (CPU_XLR): Define.
 916         (OPCODE_IS_MEMBER): Update.
 917         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 918
 919 2009-01-28  Doug Evans  <dje@google.com>
 920
 921         * opcode/i386.h: Add multiple inclusion protection.
 922         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 923         (EDI_REG_NUM): New macros.
 924         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 925         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 926         (REX_PREFIX_P): New macro.
 927
 928 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 929
 930         * ppc.h (struct powerpc_opcode): New field "deprecated".
 931         (PPC_OPCODE_NOPOWER4): Delete.
 932
 933 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 934
 935         * mips.h: Define CPU_R14000, CPU_R16000.
 936         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 937
 938 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 939
 940         * arm.h (FPU_NEON_FP16): New.
 941         (FPU_ARCH_NEON_FP16): New.
 942
 943 2008-11-06  Chao-ying Fu  <fu@mips.com>
 944
 945         * mips.h: Doucument '1' for 5-bit sync type.
 946
 947 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 950         IA64_RS_CR.
 951
 952 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 953
 954         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 955
 956 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 957
 958         * ppc.h (PPC_OPCODE_405): Define.
 959         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 960
 961 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 962
 963         * ppc.h (ppc_cpu_t): New typedef.
 964         (struct powerpc_opcode <flags>): Use it.
 965         (struct powerpc_operand <insert, extract>): Likewise.
 966         (struct powerpc_macro <flags>): Likewise.
 967
 968 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 969
 970         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 971         Update comment before MIPS16 field descriptors to mention MIPS16.
 972         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 973         BBIT.
 974         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 975         New bit masks and shift counts for cins and exts.
 976
 977         * mips.h: Document new field descriptors +Q.
 978         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 979
 980 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 981
 982         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 983         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 984
 985 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 986
 987         * ppc.h: (PPC_OPCODE_E500MC): New.
 988
 989 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 990
 991         * i386.h (MAX_OPERANDS): Set to 5.
 992         (MAX_MNEM_SIZE): Changed to 20.
 993
 994 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 995
 996         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 997
 998 2008-03-09  Paul Brook  <paul@codesourcery.com>
 999
1000         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1001
1002 2008-03-04  Paul Brook  <paul@codesourcery.com>
1003
1004         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1005         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1006         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1007
1008 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1009             Nick Clifton  <nickc@redhat.com>
1010
1011         PR 3134
1012         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1013         with a 32-bit displacement but without the top bit of the 4th byte
1014         set.
1015
1016 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1017
1018         * cr16.h (cr16_num_optab): Declared.
1019
1020 2008-02-14  Hakan Ardo  <hakan@debian.org>
1021
1022         PR gas/2626
1023         * avr.h (AVR_ISA_2xxe): Define.
1024
1025 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1026
1027         * mips.h: Update copyright.
1028         (INSN_CHIP_MASK): New macro.
1029         (INSN_OCTEON): New macro.
1030         (CPU_OCTEON): New macro.
1031         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1032
1033 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1034
1035         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1036
1037 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1038
1039         * avr.h (AVR_ISA_USB162): Add new opcode set.
1040         (AVR_ISA_AVR3): Likewise.
1041
1042 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1043
1044         * mips.h (INSN_LOONGSON_2E): New.
1045         (INSN_LOONGSON_2F): New.
1046         (CPU_LOONGSON_2E): New.
1047         (CPU_LOONGSON_2F): New.
1048         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1049
1050 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1051
1052         * mips.h (INSN_ISA*): Redefine certain values as an
1053         enumeration.  Update comments.
1054         (mips_isa_table): New.
1055         (ISA_MIPS*): Redefine to match enumeration.
1056         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1057         values.
1058
1059 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1060
1061         * ppc.h (PPC_OPCODE_PPCPS): New.
1062
1063 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1064
1065         * m68k.h: Document j K & E.
1066
1067 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1068
1069         * cr16.h: New file for CR16 target.
1070
1071 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1072
1073         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1074
1075 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1076
1077         * m68k.h (mcfisa_c): New.
1078         (mcfusp, mcf_mask): Adjust.
1079
1080 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1081
1082         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1083         (num_powerpc_operands): Declare.
1084         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1085         (PPC_OPERAND_PLUS1): Define.
1086
1087 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1088
1089         * i386.h (REX_MODE64): Renamed to ...
1090         (REX_W): This.
1091         (REX_EXTX): Renamed to ...
1092         (REX_R): This.
1093         (REX_EXTY): Renamed to ...
1094         (REX_X): This.
1095         (REX_EXTZ): Renamed to ...
1096         (REX_B): This.
1097
1098 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1099
1100         * i386.h: Add entries from config/tc-i386.h and move tables
1101         to opcodes/i386-opc.h.
1102
1103 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * i386.h (FloatDR): Removed.
1106         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1107
1108 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1109
1110         * spu-insns.h: Add soma double-float insns.
1111
1112 2007-02-20  Thiemo Seufer  <ths@mips.com>
1113             Chao-Ying Fu  <fu@mips.com>
1114
1115         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1116         (INSN_DSPR2): Add flag for DSP R2 instructions.
1117         (M_BALIGN): New macro.
1118
1119 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1120
1121         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1122         and Seg3ShortFrom with Shortform.
1123
1124 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1125
1126         PR gas/4027
1127         * i386.h (i386_optab): Put the real "test" before the pseudo
1128         one.
1129
1130 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1131
1132         * m68k.h (m68010up): OR fido_a.
1133
1134 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1135
1136         * m68k.h (fido_a): New.
1137
1138 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1139
1140         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1141         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1142         values.
1143
1144 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1145
1146         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1147
1148 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1149
1150         * score-inst.h (enum score_insn_type): Add Insn_internal.
1151
1152 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1153             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1154             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1155             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1156             Alan Modra  <amodra@bigpond.net.au>
1157
1158         * spu-insns.h: New file.
1159         * spu.h: New file.
1160
1161 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1162
1163         * ppc.h (PPC_OPCODE_CELL): Define.
1164
1165 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1166
1167         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1168         in amdfam10 architecture.
1169
1170 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         * i386.h: Replace CpuMNI with CpuSSSE3.
1173
1174 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1175             Joseph Myers  <joseph@codesourcery.com>
1176             Ian Lance Taylor  <ian@wasabisystems.com>
1177             Ben Elliston  <bje@wasabisystems.com>
1178
1179         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1180
1181 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1182
1183         * score-datadep.h: New file.
1184         * score-inst.h: New file.
1185
1186 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1187
1188         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1189         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1190         movdq2q and movq2dq.
1191
1192 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1193            Michael Meissner             <michael.meissner@amd.com>
1194
1195         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1196
1197 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1198
1199         * i386.h (i386_optab): Add "nop" with memory reference.
1200
1201 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1202
1203         * i386.h (i386_optab): Update comment for 64bit NOP.
1204
1205 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1206             Anton Blanchard  <anton@samba.org>
1207
1208         * ppc.h (PPC_OPCODE_POWER6): Define.
1209         Adjust whitespace.
1210
1211 2006-06-05  Thiemo Seufer  <ths@mips.com>
1212
1213         * mips.h: Improve description of MT flags.
1214
1215 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1216
1217         * m68k.h (mcf_mask): Define.
1218
1219 2006-05-05  Thiemo Seufer  <ths@mips.com>
1220             David Ung  <davidu@mips.com>
1221
1222         * mips.h (enum): Add macro M_CACHE_AB.
1223
1224 2006-05-04  Thiemo Seufer  <ths@mips.com>
1225             Nigel Stephens  <nigel@mips.com>
1226             David Ung  <davidu@mips.com>
1227
1228         * mips.h: Add INSN_SMARTMIPS define.
1229
1230 2006-04-30  Thiemo Seufer  <ths@mips.com>
1231             David Ung  <davidu@mips.com>
1232
1233         * mips.h: Defines udi bits and masks.  Add description of
1234         characters which may appear in the args field of udi
1235         instructions.
1236
1237 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1238
1239         * mips.h: Improve comments describing the bitfield instruction
1240         fields.
1241
1242 2006-04-26  Julian Brown  <julian@codesourcery.com>
1243
1244         * arm.h (FPU_VFP_EXT_V3): Define constant.
1245         (FPU_NEON_EXT_V1): Likewise.
1246         (FPU_VFP_HARD): Update.
1247         (FPU_VFP_V3): Define macro.
1248         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1249
1250 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1251
1252         * avr.h (AVR_ISA_PWMx): New.
1253
1254 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1255
1256         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1257         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1258         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1259         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1260         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1261
1262 2006-03-10  Paul Brook  <paul@codesourcery.com>
1263
1264         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1265
1266 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1267
1268         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1269         first.  Correct mask of bb "B" opcode.
1270
1271 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1272
1273         * i386.h (i386_optab): Support Intel Merom New Instructions.
1274
1275 2006-02-24  Paul Brook  <paul@codesourcery.com>
1276
1277         * arm.h: Add V7 feature bits.
1278
1279 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1280
1281         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1282
1283 2006-01-31  Paul Brook  <paul@codesourcery.com>
1284         Richard Earnshaw <rearnsha@arm.com>
1285
1286         * arm.h: Use ARM_CPU_FEATURE.
1287         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1288         (arm_feature_set): Change to a structure.
1289         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1290         ARM_FEATURE): New macros.
1291
1292 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1293
1294         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1295         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1296         (ADD_PC_INCR_OPCODE): Don't define.
1297
1298 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1299
1300         PR gas/1874
1301         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1302
1303 2005-11-14  David Ung  <davidu@mips.com>
1304
1305         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1306         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1307         save/restore encoding of the args field.
1308
1309 2005-10-28  Dave Brolley  <brolley@redhat.com>
1310
1311         Contribute the following changes:
1312         2005-02-16  Dave Brolley  <brolley@redhat.com>
1313
1314         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1315         cgen_isa_mask_* to cgen_bitset_*.
1316         * cgen.h: Likewise.
1317
1318         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1319
1320         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1321         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1322         (CGEN_CPU_TABLE): Make isas a ponter.
1323
1324         2003-09-29  Dave Brolley  <brolley@redhat.com>
1325
1326         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1327         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1328         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1329
1330         2002-12-13  Dave Brolley  <brolley@redhat.com>
1331
1332         * cgen.h (symcat.h): #include it.
1333         (cgen-bitset.h): #include it.
1334         (CGEN_ATTR_VALUE_TYPE): Now a union.
1335         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1336         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1337         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1338         * cgen-bitset.h: New file.
1339
1340 2005-09-30  Catherine Moore  <clm@cm00re.com>
1341
1342         * bfin.h: New file.
1343
1344 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1345
1346         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1347         indirect operands.
1348
1349 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1350
1351         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1352         Add FLAG_STRICT to pa10 ftest opcode.
1353
1354 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1355
1356         * hppa.h (pa_opcodes): Remove lha entries.
1357
1358 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1359
1360         * hppa.h (FLAG_STRICT): Revise comment.
1361         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1362         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1363         entries for "fdc".
1364
1365 2005-09-30  Catherine Moore  <clm@cm00re.com>
1366
1367         * bfin.h: New file.
1368
1369 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1370
1371         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1372
1373 2005-09-06  Chao-ying Fu  <fu@mips.com>
1374
1375         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1376         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1377         define.
1378         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1379         (INSN_ASE_MASK): Update to include INSN_MT.
1380         (INSN_MT): New define for MT ASE.
1381
1382 2005-08-25  Chao-ying Fu  <fu@mips.com>
1383
1384         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1385         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1386         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1387         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1388         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1389         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1390         instructions.
1391         (INSN_DSP): New define for DSP ASE.
1392
1393 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1394
1395         * a29k.h: Delete.
1396
1397 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1398
1399         * ppc.h (PPC_OPCODE_E300): Define.
1400
1401 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1402
1403         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1404
1405 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1406
1407         PR gas/336
1408         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1409         and pitlb.
1410
1411 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1412
1413         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1414         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1415         Add movq-s as 64-bit variants of movd-s.
1416
1417 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1418
1419         * hppa.h: Fix punctuation in comment.
1420
1421         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1422         implicit space-register addressing.  Set space-register bits on opcodes
1423         using implicit space-register addressing.  Add various missing pa20
1424         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1425         space-register addressing.  Use "fE" instead of "fe" in various
1426         fstw opcodes.
1427
1428 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1429
1430         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1431
1432 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1433
1434         * i386.h (i386_optab): Support Intel VMX Instructions.
1435
1436 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1437
1438         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1439
1440 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1441
1442         * i386.h (i386_optab): Add new insns.
1443
1444 2005-07-01  Nick Clifton  <nickc@redhat.com>
1445
1446         * sparc.h: Add typedefs to structure declarations.
1447
1448 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1449
1450         PR 1013
1451         * i386.h (i386_optab): Update comments for 64bit addressing on
1452         mov. Allow 64bit addressing for mov and movq.
1453
1454 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1455
1456         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1457         respectively, in various floating-point load and store patterns.
1458
1459 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1460
1461         * hppa.h (FLAG_STRICT): Correct comment.
1462         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1463         PA 2.0 mneumonics when equivalent.  Entries with cache control
1464         completers now require PA 1.1.  Adjust whitespace.
1465
1466 2005-05-19  Anton Blanchard  <anton@samba.org>
1467
1468         * ppc.h (PPC_OPCODE_POWER5): Define.
1469
1470 2005-05-10  Nick Clifton  <nickc@redhat.com>
1471
1472         * Update the address and phone number of the FSF organization in
1473         the GPL notices in the following files:
1474         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1475         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1476         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1477         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1478         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1479         tic54x.h, tic80.h, v850.h, vax.h
1480
1481 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1482
1483         * i386.h (i386_optab): Add ht and hnt.
1484
1485 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1486
1487         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1488         Add xcrypt-ctr.  Provide aliases without hyphens.
1489
1490 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1491
1492         Moved from ../ChangeLog
1493
1494         2005-04-12  Paul Brook  <paul@codesourcery.com>
1495         * m88k.h: Rename psr macros to avoid conflicts.
1496
1497         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1498         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1499         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1500         and ARM_ARCH_V6ZKT2.
1501
1502         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1503         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1504         Remove redundant instruction types.
1505         (struct argument): X_op - new field.
1506         (struct cst4_entry): Remove.
1507         (no_op_insn): Declare.
1508
1509         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1510         * crx.h (enum argtype): Rename types, remove unused types.
1511
1512         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1513         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1514         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1515         (enum operand_type): Rearrange operands, edit comments.
1516         replace us<N> with ui<N> for unsigned immediate.
1517         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1518         displacements (respectively).
1519         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1520         (instruction type): Add NO_TYPE_INS.
1521         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1522         (operand_entry): New field - 'flags'.
1523         (operand flags): New.
1524
1525         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1526         * crx.h (operand_type): Remove redundant types i3, i4,
1527         i5, i8, i12.
1528         Add new unsigned immediate types us3, us4, us5, us16.
1529
1530 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1531
1532         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1533         adjust them accordingly.
1534
1535 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1536
1537         * i386.h (i386_optab): Add rdtscp.
1538
1539 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1540
1541         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1542         between memory and segment register. Allow movq for moving between
1543         general-purpose register and segment register.
1544
1545 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1546
1547         PR gas/707
1548         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1549         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1550         fnstsw.
1551
1552 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1553
1554         * m68k.h (m68008, m68ec030, m68882): Remove.
1555         (m68k_mask): New.
1556         (cpu_m68k, cpu_cf): New.
1557         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1558         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1559
1560 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1561
1562         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1563         * cgen.h (enum cgen_parse_operand_type): Add
1564         CGEN_PARSE_OPERAND_SYMBOLIC.
1565
1566 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1567
1568         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1569         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1570         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1571
1572 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1573
1574         * mips.h (struct mips_opcode): Add new pinfo2 member.
1575         (INSN_ALIAS): New define for opcode table entries that are
1576         specific instances of another entry, such as 'move' for an 'or'
1577         with a zero operand.
1578         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1579         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1580
1581 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1582
1583         * mips.h (CPU_RM9000): Define.
1584         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1585
1586 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1587
1588         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1589         to/from test registers are illegal in 64-bit mode. Add missing
1590         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1591         (previously one had to explicitly encode a rex64 prefix). Re-enable
1592         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1593         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1594
1595 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1596
1597         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1598         available only with SSE2. Change the MMX additions introduced by SSE
1599         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1600         instructions by their now designated identifier (since combining i686
1601         and 3DNow! does not really imply 3DNow!A).
1602
1603 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1604
1605         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1606         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1607
1608 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1609             Vineet Sharma      <vineets@noida.hcltech.com>
1610
1611         * maxq.h: New file: Disassembly information for the maxq port.
1612
1613 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1614
1615         * i386.h (i386_optab): Put back "movzb".
1616
1617 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1618
1619         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1620         comments.  Remove member cris_ver_sim.  Add members
1621         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1622         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1623         (struct cris_support_reg, struct cris_cond15): New types.
1624         (cris_conds15): Declare.
1625         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1626         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1627         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1628         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1629         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1630         SIZE_FIELD_UNSIGNED.
1631
1632 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1633
1634         * i386.h (sldx_Suf): Remove.
1635         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1636         (q_FP): Define, implying no REX64.
1637         (x_FP, sl_FP): Imply FloatMF.
1638         (i386_optab): Split reg and mem forms of moving from segment registers
1639         so that the memory forms can ignore the 16-/32-bit operand size
1640         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1641         all non-floating-point instructions. Unite 32- and 64-bit forms of
1642         movsx, movzx, and movd. Adjust floating point operations for the above
1643         changes to the *FP macros. Add DefaultSize to floating point control
1644         insns operating on larger memory ranges. Remove left over comments
1645         hinting at certain insns being Intel-syntax ones where the ones
1646         actually meant are already gone.
1647
1648 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1649
1650         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1651         instruction type.
1652
1653 2004-09-30  Paul Brook  <paul@codesourcery.com>
1654
1655         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1656         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1657
1658 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1659
1660         * avr.h: Add support for
1661         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1662
1663 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1664
1665         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1666
1667 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1668
1669         * msp430.h (msp430_opc): Add new instructions.
1670         (msp430_rcodes): Declare new instructions.
1671         (msp430_hcodes): Likewise..
1672
1673 2004-08-13  Nick Clifton  <nickc@redhat.com>
1674
1675         PR/301
1676         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1677         processors.
1678
1679 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1680
1681         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1682
1683 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1684
1685         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1686
1687 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1688
1689         * i386.h: Adjust instruction descriptions to better match the
1690         specification.
1691
1692 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1693
1694         * arm.h: Remove all old content.  Replace with architecture defines
1695         from gas/config/tc-arm.c.
1696
1697 2004-07-09  Andreas Schwab  <schwab@suse.de>
1698
1699         * m68k.h: Fix comment.
1700
1701 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1702
1703         * crx.h: New file.
1704
1705 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1706
1707         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1708
1709 2004-05-24  Peter Barada  <peter@the-baradas.com>
1710
1711         * m68k.h: Add 'size' to m68k_opcode.
1712
1713 2004-05-05  Peter Barada  <peter@the-baradas.com>
1714
1715         * m68k.h: Switch from ColdFire chip name to core variant.
1716
1717 2004-04-22  Peter Barada  <peter@the-baradas.com>
1718
1719         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1720         descriptions for new EMAC cases.
1721         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1722         handle Motorola MAC syntax.
1723         Allow disassembly of ColdFire V4e object files.
1724
1725 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1726
1727         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1728
1729 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1730
1731         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1732
1733 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1734
1735         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1736
1737 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1738
1739         * i386.h (i386_optab): Added xstore/xcrypt insns.
1740
1741 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1742
1743         * h8300.h (32bit ldc/stc): Add relaxing support.
1744
1745 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1746
1747         * h8300.h (BITOP): Pass MEMRELAX flag.
1748
1749 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1750
1751         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1752         except for the H8S.
1753
1754 For older changes see ChangeLog-9103
1755 \f
1756 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1757
1758 Copying and distribution of this file, with or without modification,
1759 are permitted in any medium without royalty provided the copyright
1760 notice and this notice are preserved.
1761
1762 Local Variables:
1763 mode: change-log
1764 left-margin: 8
1765 fill-column: 74
1766 version-control: never
1767 End: