1 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
2 Cesar Philippidis <cesar@codesourcery.com>
4 * nios2.h (enum iw_format_type): Add R2 formats.
5 (enum overflow_type): Add signed_immed12_overflow and
6 enumeration_overflow for R2.
7 (struct nios2_opcode): Document new argument letters for R2.
8 (REG_3BIT, REG_LDWM, REG_POP): Define.
9 (includes): Include nios2r2.h.
10 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
11 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
12 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
13 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
14 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
15 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
17 * nios2r2.h: New file.
19 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
21 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
22 (ppc_optional_operand_value): New inline function.
24 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
26 * aarch64.h (AARCH64_V8_1): New.
28 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
30 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
31 (ARM_ARCH_V8_1A): New.
32 (ARM_ARCH_V8_1A_FP): New.
33 (ARM_ARCH_V8_1A_SIMD): New.
34 (ARM_ARCH_V8_1A_CRYPTOV1): New.
35 (ARM_FEATURE_CORE): New.
37 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
39 * arm.h (ARM_EXT2_PAN): New.
40 (ARM_FEATURE_CORE_HIGH): New.
42 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
44 * arm.h (ARM_FEATURE_ALL): New.
46 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
48 * aarch64.h (AARCH64_FEATURE_RDMA): New.
50 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
52 * aarch64.h (AARCH64_FEATURE_LOR): New.
54 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
56 * aarch64.h (AARCH64_FEATURE_PAN): New.
57 (aarch64_sys_reg_supported_p): Declare.
58 (aarch64_pstatefield_supported_p): Declare.
60 2015-04-30 DJ Delorie <dj@redhat.com>
62 * rl78.h (RL78_Dis_Isa): New.
63 (rl78_decode_opcode): Add ISA parameter.
65 2015-03-24 Terry Guo <terry.guo@arm.com>
67 * arm.h (arm_feature_set): Extended to provide more available bits.
68 (ARM_ANY): Updated to follow above new definition.
69 (ARM_CPU_HAS_FEATURE): Likewise.
70 (ARM_CPU_IS_ANY): Likewise.
71 (ARM_MERGE_FEATURE_SETS): Likewise.
72 (ARM_CLEAR_FEATURE): Likewise.
73 (ARM_FEATURE): Likewise.
74 (ARM_FEATURE_COPY): New macro.
75 (ARM_FEATURE_EQUAL): Likewise.
76 (ARM_FEATURE_ZERO): Likewise.
77 (ARM_FEATURE_CORE_EQUAL): Likewise.
78 (ARM_FEATURE_LOW): Likewise.
79 (ARM_FEATURE_CORE_LOW): Likewise.
80 (ARM_FEATURE_CORE_COPROC): Likewise.
82 2015-02-19 Pedro Alves <palves@redhat.com>
84 * cgen.h [__cplusplus]: Wrap in extern "C".
85 * msp430-decode.h [__cplusplus]: Likewise.
86 * nios2.h [__cplusplus]: Likewise.
87 * rl78.h [__cplusplus]: Likewise.
88 * rx.h [__cplusplus]: Likewise.
89 * tilegx.h [__cplusplus]: Likewise.
91 2015-01-28 James Bowman <james.bowman@ftdichip.com>
95 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
97 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
99 2015-01-01 Alan Modra <amodra@gmail.com>
101 Update year range in copyright notice of all files.
103 2014-12-27 Anthony Green <green@moxielogic.com>
105 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
106 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
108 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
110 * visium.h: New file.
112 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
114 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
115 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
116 (NIOS2_INSN_OPTARG): Renumber.
118 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
120 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
121 declaration. Fix obsolete comment.
123 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
125 * nios2.h (enum iw_format_type): New.
126 (struct nios2_opcode): Update comments. Add size and format fields.
127 (NIOS2_INSN_OPTARG): New.
128 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
129 (struct nios2_reg): Add regtype field.
130 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
131 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
132 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
133 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
134 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
135 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
136 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
137 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
138 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
139 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
140 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
141 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
142 (OP_MASK_OP, OP_SH_OP): Delete.
143 (OP_MASK_IOP, OP_SH_IOP): Delete.
144 (OP_MASK_IRD, OP_SH_IRD): Delete.
145 (OP_MASK_IRT, OP_SH_IRT): Delete.
146 (OP_MASK_IRS, OP_SH_IRS): Delete.
147 (OP_MASK_ROP, OP_SH_ROP): Delete.
148 (OP_MASK_RRD, OP_SH_RRD): Delete.
149 (OP_MASK_RRT, OP_SH_RRT): Delete.
150 (OP_MASK_RRS, OP_SH_RRS): Delete.
151 (OP_MASK_JOP, OP_SH_JOP): Delete.
152 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
153 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
154 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
155 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
156 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
157 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
158 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
159 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
160 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
161 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
162 (OP_MASK_<insn>, OP_MASK): Delete.
163 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
164 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
165 Include nios2r1.h to define new instruction opcode constants
167 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
168 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
169 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
170 (NUMOPCODES, NUMREGISTERS): Delete.
171 * nios2r1.h: New file.
173 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
175 * sparc.h (HWCAP2_VIS3B): Documentation improved.
177 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
179 * sparc.h (sparc_opcode): new field `hwcaps2'.
180 (HWCAP2_FJATHPLUS): New define.
181 (HWCAP2_VIS3B): Likewise.
182 (HWCAP2_ADP): Likewise.
183 (HWCAP2_SPARC5): Likewise.
184 (HWCAP2_MWAIT): Likewise.
185 (HWCAP2_XMPMUL): Likewise.
186 (HWCAP2_XMONT): Likewise.
187 (HWCAP2_NSEC): Likewise.
188 (HWCAP2_FJATHHPC): Likewise.
189 (HWCAP2_FJDES): Likewise.
190 (HWCAP2_FJAES): Likewise.
191 Document the new operand kind `{', corresponding to the mcdper
192 ancillary state register.
193 Document the new operand kind }, which represents frsd floating
194 point registers (double precision) which must be the same than
195 frs1 in its containing instruction.
197 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
199 * nds32.h: Add new opcode declaration.
201 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
202 Matthew Fortune <matthew.fortune@imgtec.com>
204 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
205 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
206 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
207 +I, +O, +R, +:, +\, +", +;
208 (mips_check_prev_operand): New struct.
209 (INSN2_FORBIDDEN_SLOT): New define.
210 (INSN_ISA32R6): New define.
211 (INSN_ISA64R6): New define.
212 (INSN_UPTO32R6): New define.
213 (INSN_UPTO64R6): New define.
214 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
215 (ISA_MIPS32R6): New define.
216 (ISA_MIPS64R6): New define.
217 (CPU_MIPS32R6): New define.
218 (CPU_MIPS64R6): New define.
219 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
221 2014-09-03 Jiong Wang <jiong.wang@arm.com>
223 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
224 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
225 (aarch64_insn_class): Add lse_atomic.
226 (F_LSE_SZ): New field added.
227 (opcode_has_special_coder): Recognize F_LSE_SZ.
229 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
231 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
234 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
236 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
237 (INSN_LOAD_COPROC): New define.
238 (INSN_COPROC_MOVE_DELAY): Rename to...
239 (INSN_COPROC_MOVE): New define.
241 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
242 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
243 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
244 Soundararajan <Sounderarajan.D@atmel.com>
246 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
247 (AVR_ISA_2xxxa): Define ISA without LPM.
248 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
249 Add doc for contraint used in 16 bit lds/sts.
250 Adjust ISA group for icall, ijmp, pop and push.
251 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
253 2014-05-19 Nick Clifton <nickc@redhat.com>
255 * msp430.h (struct msp430_operand_s): Add vshift field.
257 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
259 * mips.h (INSN_ISA_MASK): Updated.
260 (INSN_ISA32R3): New define.
261 (INSN_ISA32R5): New define.
262 (INSN_ISA64R3): New define.
263 (INSN_ISA64R5): New define.
264 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
265 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
266 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
268 (INSN_UPTO32R3): New define.
269 (INSN_UPTO32R5): New define.
270 (INSN_UPTO64R3): New define.
271 (INSN_UPTO64R5): New define.
272 (ISA_MIPS32R3): New define.
273 (ISA_MIPS32R5): New define.
274 (ISA_MIPS64R3): New define.
275 (ISA_MIPS64R5): New define.
276 (CPU_MIPS32R3): New define.
277 (CPU_MIPS32R5): New define.
278 (CPU_MIPS64R3): New define.
279 (CPU_MIPS64R5): New define.
281 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
283 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
285 2014-04-22 Christian Svensson <blue@cmd.nu>
289 2014-03-05 Alan Modra <amodra@gmail.com>
291 Update copyright years.
293 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
295 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
298 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
299 Wei-Cheng Wang <cole945@gmail.com>
301 * nds32.h: New file for Andes NDS32.
303 2013-12-07 Mike Frysinger <vapier@gentoo.org>
305 * bfin.h: Remove +x file mode.
307 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
309 * aarch64.h (aarch64_pstatefields): Change element type to
312 2013-11-18 Renlin Li <Renlin.Li@arm.com>
314 * arm.h (ARM_AEXT_V7VE): New define.
315 (ARM_ARCH_V7VE): New define.
316 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
318 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
322 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
324 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
325 (aarch64_sys_reg_writeonly_p): Ditto.
327 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
329 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
330 (aarch64_sys_reg_writeonly_p): Ditto.
332 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
334 * aarch64.h (aarch64_sys_reg): New typedef.
335 (aarch64_sys_regs): Change to define with the new type.
336 (aarch64_sys_reg_deprecated_p): Declare.
338 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
340 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
341 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
343 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
345 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
346 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
347 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
348 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
349 For MIPS, update extension character sequences after +.
350 (ASE_MSA): New define.
351 (ASE_MSA64): New define.
352 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
353 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
354 For microMIPS, update extension character sequences after +.
356 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
361 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
363 * mips.h: Remove references to "+I" and imm2_expr.
365 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
367 * mips.h (M_DEXT, M_DINS): Delete.
369 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
371 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
372 (mips_optional_operand_p): New function.
374 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
375 Richard Sandiford <rdsandiford@googlemail.com>
377 * mips.h: Document new VU0 operand characters.
378 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
379 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
380 (OP_REG_R5900_ACC): New mips_reg_operand_types.
381 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
382 (mips_vu0_channel_mask): Declare.
384 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
386 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
387 (mips_int_operand_min, mips_int_operand_max): New functions.
388 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
390 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
392 * mips.h (mips_decode_reg_operand): New function.
393 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
394 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
395 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
397 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
398 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
399 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
400 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
401 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
402 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
403 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
404 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
405 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
406 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
407 macros to cover the gaps.
408 (INSN2_MOD_SP): Replace with...
409 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
410 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
411 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
412 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
413 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
416 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
418 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
419 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
420 (MIPS16_INSN_COND_BRANCH): Delete.
422 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
423 Kirill Yukhin <kirill.yukhin@intel.com>
424 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
426 * i386.h (BND_PREFIX_OPCODE): New.
428 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
430 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
431 OP_SAVE_RESTORE_LIST.
432 (decode_mips16_operand): Declare.
434 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
436 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
437 (mips_operand, mips_int_operand, mips_mapped_int_operand)
438 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
439 (mips_pcrel_operand): New structures.
440 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
441 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
442 (decode_mips_operand, decode_micromips_operand): Declare.
444 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
446 * mips.h: Document MIPS16 "I" opcode.
448 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
450 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
451 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
452 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
453 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
454 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
455 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
456 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
457 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
458 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
459 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
460 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
461 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
462 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
464 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
465 (M_USD_AB): ...these.
467 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
469 * mips.h: Remove documentation of "[" and "]". Update documentation
470 of "k" and the MDMX formats.
472 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
474 * mips.h: Update documentation of "+s" and "+S".
476 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
478 * mips.h: Document "+i".
480 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
482 * mips.h: Remove "mi" documentation. Update "mh" documentation.
483 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
485 (INSN2_WRITE_GPR_MHI): Rename to...
486 (INSN2_WRITE_GPR_MH): ...this.
488 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
490 * mips.h: Remove documentation of "+D" and "+T".
492 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
494 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
495 Use "source" rather than "destination" for microMIPS "G".
497 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
499 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
502 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
504 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
506 2013-06-17 Catherine Moore <clm@codesourcery.com>
507 Maciej W. Rozycki <macro@codesourcery.com>
508 Chao-Ying Fu <fu@mips.com>
510 * mips.h (OP_SH_EVAOFFSET): Define.
511 (OP_MASK_EVAOFFSET): Define.
512 (INSN_ASE_MASK): Delete.
514 (M_CACHEE_AB, M_CACHEE_OB): New.
515 (M_LBE_OB, M_LBE_AB): New.
516 (M_LBUE_OB, M_LBUE_AB): New.
517 (M_LHE_OB, M_LHE_AB): New.
518 (M_LHUE_OB, M_LHUE_AB): New.
519 (M_LLE_AB, M_LLE_OB): New.
520 (M_LWE_OB, M_LWE_AB): New.
521 (M_LWLE_AB, M_LWLE_OB): New.
522 (M_LWRE_AB, M_LWRE_OB): New.
523 (M_PREFE_AB, M_PREFE_OB): New.
524 (M_SCE_AB, M_SCE_OB): New.
525 (M_SBE_OB, M_SBE_AB): New.
526 (M_SHE_OB, M_SHE_AB): New.
527 (M_SWE_OB, M_SWE_AB): New.
528 (M_SWLE_AB, M_SWLE_OB): New.
529 (M_SWRE_AB, M_SWRE_OB): New.
530 (MICROMIPSOP_SH_EVAOFFSET): Define.
531 (MICROMIPSOP_MASK_EVAOFFSET): Define.
533 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
535 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
537 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
539 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
541 2013-05-09 Andrew Pinski <apinski@cavium.com>
543 * mips.h (OP_MASK_CODE10): Correct definition.
544 (OP_SH_CODE10): Likewise.
545 Add a comment that "+J" is used now for OP_*CODE10.
546 (INSN_ASE_MASK): Update.
547 (INSN_VIRT): New macro.
548 (INSN_VIRT64): New macro
550 2013-05-02 Nick Clifton <nickc@redhat.com>
552 * msp430.h: Add patterns for MSP430X instructions.
554 2013-04-06 David S. Miller <davem@davemloft.net>
556 * sparc.h (F_PREFERRED): Define.
557 (F_PREF_ALIAS): Define.
559 2013-04-03 Nick Clifton <nickc@redhat.com>
561 * v850.h (V850_INVERSE_PCREL): Define.
563 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
566 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
568 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
571 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
573 * tic6xc-opcode-table.h: Add 16-bit insns.
574 * tic6x.h: Add support for 16-bit insns.
576 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
578 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
579 and mov.b/w/l Rs,@(d:32,ERd).
581 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
584 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
585 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
586 tic6x_operand_xregpair operand coding type.
587 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
588 opcode field, usu ORXREGD1324 for the src2 operand and remove the
591 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
594 * tic6x.h (enum tic6x_coding_method): Add
595 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
596 separately the msb and lsb of a register pair. This is needed to
597 encode the opcodes in the same way as TI assembler does.
598 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
599 and rsqrdp opcodes to use the new field coding types.
601 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
603 * arm.h (CRC_EXT_ARMV8): New constant.
604 (ARCH_CRC_ARMV8): New macro.
606 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
608 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
610 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
611 Andrew Jenner <andrew@codesourcery.com>
613 Based on patches from Altera Corporation.
617 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
619 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
621 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
624 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
626 2013-01-24 Nick Clifton <nickc@redhat.com>
628 * v850.h: Add e3v5 support.
630 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
632 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
634 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
636 * ppc.h (PPC_OPCODE_POWER8): New define.
637 (PPC_OPCODE_HTM): Likewise.
639 2013-01-10 Will Newton <will.newton@imgtec.com>
643 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
645 * cr16.h (make_instruction): Rename to cr16_make_instruction.
646 (match_opcode): Rename to cr16_match_opcode.
648 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
650 * mips.h: Add support for r5900 instructions including lq and sq.
652 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
654 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
655 (make_instruction,match_opcode): Added function prototypes.
656 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
658 2012-11-23 Alan Modra <amodra@gmail.com>
660 * ppc.h (ppc_parse_cpu): Update prototype.
662 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
664 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
665 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
667 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
669 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
671 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
673 * ia64.h (ia64_opnd): Add new operand types.
675 2012-08-21 David S. Miller <davem@davemloft.net>
677 * sparc.h (F3F4): New macro.
679 2012-08-13 Ian Bolton <ian.bolton@arm.com>
680 Laurent Desnogues <laurent.desnogues@arm.com>
681 Jim MacArthur <jim.macarthur@arm.com>
682 Marcus Shawcroft <marcus.shawcroft@arm.com>
683 Nigel Stephens <nigel.stephens@arm.com>
684 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
685 Richard Earnshaw <rearnsha@arm.com>
686 Sofiane Naci <sofiane.naci@arm.com>
687 Tejas Belagod <tejas.belagod@arm.com>
688 Yufeng Zhang <yufeng.zhang@arm.com>
690 * aarch64.h: New file.
692 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
693 Maciej W. Rozycki <macro@codesourcery.com>
695 * mips.h (mips_opcode): Add the exclusions field.
696 (OPCODE_IS_MEMBER): Remove macro.
697 (cpu_is_member): New inline function.
698 (opcode_is_member): Likewise.
700 2012-07-31 Chao-Ying Fu <fu@mips.com>
701 Catherine Moore <clm@codesourcery.com>
702 Maciej W. Rozycki <macro@codesourcery.com>
704 * mips.h: Document microMIPS DSP ASE usage.
705 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
706 microMIPS DSP ASE support.
707 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
708 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
709 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
710 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
711 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
712 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
713 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
715 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
717 * mips.h: Fix a typo in description.
719 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
721 * avr.h: (AVR_ISA_XCH): New define.
722 (AVR_ISA_XMEGA): Use it.
723 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
725 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
727 * m68hc11.h: Add XGate definitions.
728 (struct m68hc11_opcode): Add xg_mask field.
730 2012-05-14 Catherine Moore <clm@codesourcery.com>
731 Maciej W. Rozycki <macro@codesourcery.com>
732 Rhonda Wittels <rhonda@codesourcery.com>
734 * ppc.h (PPC_OPCODE_VLE): New definition.
735 (PPC_OP_SA): New macro.
736 (PPC_OP_SE_VLE): New macro.
737 (PPC_OP): Use a variable shift amount.
738 (powerpc_operand): Update comments.
739 (PPC_OPSHIFT_INV): New macro.
740 (PPC_OPERAND_CR): Replace with...
741 (PPC_OPERAND_CR_BIT): ...this and
742 (PPC_OPERAND_CR_REG): ...this.
745 2012-05-03 Sean Keys <skeys@ipdatasys.com>
747 * xgate.h: Header file for XGATE assembler.
749 2012-04-27 David S. Miller <davem@davemloft.net>
751 * sparc.h: Document new arg code' )' for crypto RS3
754 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
755 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
756 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
757 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
758 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
759 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
760 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
761 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
762 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
763 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
764 HWCAP_CBCOND, HWCAP_CRC32): New defines.
766 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
768 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
770 2012-02-27 Alan Modra <amodra@gmail.com>
772 * crx.h (cst4_map): Update declaration.
774 2012-02-25 Walter Lee <walt@tilera.com>
776 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
778 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
779 TILEPRO_OPC_LW_TLS_SN.
781 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
783 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
784 (XRELEASE_PREFIX_OPCODE): Likewise.
786 2011-12-08 Andrew Pinski <apinski@cavium.com>
787 Adam Nemet <anemet@caviumnetworks.com>
789 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
790 (INSN_OCTEON2): New macro.
791 (CPU_OCTEON2): New macro.
792 (OPCODE_IS_MEMBER): Add Octeon2.
794 2011-11-29 Andrew Pinski <apinski@cavium.com>
796 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
797 (INSN_OCTEONP): New macro.
798 (CPU_OCTEONP): New macro.
799 (OPCODE_IS_MEMBER): Add Octeon+.
800 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
802 2011-11-01 DJ Delorie <dj@redhat.com>
806 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
808 * mips.h: Fix a typo in description.
810 2011-09-21 David S. Miller <davem@davemloft.net>
812 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
813 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
814 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
815 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
817 2011-08-09 Chao-ying Fu <fu@mips.com>
818 Maciej W. Rozycki <macro@codesourcery.com>
820 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
821 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
822 (INSN_ASE_MASK): Add the MCU bit.
823 (INSN_MCU): New macro.
824 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
825 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
827 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
829 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
830 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
831 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
832 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
833 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
834 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
835 (INSN2_READ_GPR_MMN): Likewise.
836 (INSN2_READ_FPR_D): Change the bit used.
837 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
838 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
839 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
840 (INSN2_COND_BRANCH): Likewise.
841 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
842 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
843 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
844 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
845 (INSN2_MOD_GPR_MN): Likewise.
847 2011-08-05 David S. Miller <davem@davemloft.net>
849 * sparc.h: Document new format codes '4', '5', and '('.
850 (OPF_LOW4, RS3): New macros.
852 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
854 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
855 order of flags documented.
857 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
859 * mips.h: Clarify the description of microMIPS instruction
861 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
863 2011-07-24 Chao-ying Fu <fu@mips.com>
864 Maciej W. Rozycki <macro@codesourcery.com>
866 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
867 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
868 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
869 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
870 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
871 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
872 (OP_MASK_RS3, OP_SH_RS3): Likewise.
873 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
874 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
875 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
876 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
877 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
878 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
879 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
880 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
881 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
882 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
883 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
884 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
885 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
886 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
887 (INSN_WRITE_GPR_S): New macro.
888 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
889 (INSN2_READ_FPR_D): Likewise.
890 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
891 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
892 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
893 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
894 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
895 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
896 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
897 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
898 (CPU_MICROMIPS): New macro.
899 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
900 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
901 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
902 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
903 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
904 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
905 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
906 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
907 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
908 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
909 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
910 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
911 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
912 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
913 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
914 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
915 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
916 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
917 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
918 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
919 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
920 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
921 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
922 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
923 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
924 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
925 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
926 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
927 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
928 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
929 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
930 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
931 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
932 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
933 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
934 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
935 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
936 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
937 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
938 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
939 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
940 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
941 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
942 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
943 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
944 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
945 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
946 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
947 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
948 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
949 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
950 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
951 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
952 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
953 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
954 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
955 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
956 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
957 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
958 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
959 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
960 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
961 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
962 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
963 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
964 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
965 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
966 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
967 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
968 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
969 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
970 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
971 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
972 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
973 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
974 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
975 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
976 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
977 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
978 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
979 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
980 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
981 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
982 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
983 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
984 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
985 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
986 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
987 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
988 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
989 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
990 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
991 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
992 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
993 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
994 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
995 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
996 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
997 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
998 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
999 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1000 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1001 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1002 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1003 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1004 (micromips_opcodes): New declaration.
1005 (bfd_micromips_num_opcodes): Likewise.
1007 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1009 * mips.h (INSN_TRAP): Rename to...
1010 (INSN_NO_DELAY_SLOT): ... this.
1011 (INSN_SYNC): Remove macro.
1013 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1015 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1016 a duplicate of AVR_ISA_SPM.
1018 2011-07-01 Nick Clifton <nickc@redhat.com>
1020 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1022 2011-06-18 Robin Getz <robin.getz@analog.com>
1024 * bfin.h (is_macmod_signed): New func
1026 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1028 * bfin.h (is_macmod_pmove): Add missing space before func args.
1029 (is_macmod_hmove): Likewise.
1031 2011-06-13 Walter Lee <walt@tilera.com>
1033 * tilegx.h: New file.
1034 * tilepro.h: New file.
1036 2011-05-31 Paul Brook <paul@codesourcery.com>
1038 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1040 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1042 * s390.h: Replace S390_OPERAND_REG_EVEN with
1043 S390_OPERAND_REG_PAIR.
1045 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1047 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1049 2011-04-18 Julian Brown <julian@codesourcery.com>
1051 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1053 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1056 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1058 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1060 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1061 New instruction set flags.
1062 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1064 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1066 * mips.h (M_PREF_AB): New enum value.
1068 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1070 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1072 (is_macmod_pmove, is_macmod_hmove): New functions.
1074 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1076 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1078 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1080 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1081 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1083 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1086 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1089 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1092 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1094 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1096 * mips.h: Update commentary after last commit.
1098 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1100 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1101 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1102 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1104 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1106 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1108 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1110 * mips.h: Fix previous commit.
1112 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1114 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1115 (INSN_LOONGSON_3A): Clear bit 31.
1117 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1120 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1121 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1122 (ARM_ARCH_V6M_ONLY): New define.
1124 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1126 * mips.h (INSN_LOONGSON_3A): Defined.
1127 (CPU_LOONGSON_3A): Defined.
1128 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1130 2010-10-09 Matt Rice <ratmice@gmail.com>
1132 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1133 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1135 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1137 * arm.h (ARM_EXT_VIRT): New define.
1138 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1139 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1142 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1144 * arm.h (ARM_AEXT_ADIV): New define.
1145 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1147 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1149 * arm.h (ARM_EXT_OS): New define.
1150 (ARM_AEXT_V6SM): Likewise.
1151 (ARM_ARCH_V6SM): Likewise.
1153 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1155 * arm.h (ARM_EXT_MP): Add.
1156 (ARM_ARCH_V7A_MP): Likewise.
1158 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1160 * bfin.h: Declare pseudoChr structs/defines.
1162 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1164 * bfin.h: Strip trailing whitespace.
1166 2010-07-29 DJ Delorie <dj@redhat.com>
1168 * rx.h (RX_Operand_Type): Add TwoReg.
1169 (RX_Opcode_ID): Remove ediv and ediv2.
1171 2010-07-27 DJ Delorie <dj@redhat.com>
1173 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1175 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1176 Ina Pandit <ina.pandit@kpitcummins.com>
1178 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1179 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1180 PROCESSOR_V850E2_ALL.
1181 Remove PROCESSOR_V850EA support.
1182 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1183 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1184 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1185 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1186 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1187 V850_OPERAND_PERCENT.
1188 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1190 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1193 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1195 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1196 (MIPS16_INSN_BRANCH): Rename to...
1197 (MIPS16_INSN_COND_BRANCH): ... this.
1199 2010-07-03 Alan Modra <amodra@gmail.com>
1201 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1202 Renumber other PPC_OPCODE defines.
1204 2010-07-03 Alan Modra <amodra@gmail.com>
1206 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1208 2010-06-29 Alan Modra <amodra@gmail.com>
1210 * maxq.h: Delete file.
1212 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1214 * ppc.h (PPC_OPCODE_E500): Define.
1216 2010-05-26 Catherine Moore <clm@codesourcery.com>
1218 * opcode/mips.h (INSN_MIPS16): Remove.
1220 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1222 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1224 2010-04-15 Nick Clifton <nickc@redhat.com>
1226 * alpha.h: Update copyright notice to use GPLv3.
1232 * convex.h: Likewise.
1239 * h8300.h: Likewise.
1246 * m68hc11.h: Likewise.
1252 * mn10200.h: Likewise.
1253 * mn10300.h: Likewise.
1254 * msp430.h: Likewise.
1256 * ns32k.h: Likewise.
1258 * pdp11.h: Likewise.
1265 * score-datadep.h: Likewise.
1266 * score-inst.h: Likewise.
1267 * sparc.h: Likewise.
1268 * spu-insns.h: Likewise.
1270 * tic30.h: Likewise.
1271 * tic4x.h: Likewise.
1272 * tic54x.h: Likewise.
1273 * tic80.h: Likewise.
1277 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1279 * tic6x-control-registers.h, tic6x-insn-formats.h,
1280 tic6x-opcode-table.h, tic6x.h: New.
1282 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1284 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1286 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1288 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1290 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1292 * ia64.h (ia64_find_opcode): Remove argument name.
1293 (ia64_find_next_opcode): Likewise.
1294 (ia64_dis_opcode): Likewise.
1295 (ia64_free_opcode): Likewise.
1296 (ia64_find_dependency): Likewise.
1298 2009-11-22 Doug Evans <dje@sebabeach.org>
1300 * cgen.h: Include bfd_stdint.h.
1301 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1303 2009-11-18 Paul Brook <paul@codesourcery.com>
1305 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1307 2009-11-17 Paul Brook <paul@codesourcery.com>
1308 Daniel Jacobowitz <dan@codesourcery.com>
1310 * arm.h (ARM_EXT_V6_DSP): Define.
1311 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1312 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1314 2009-11-04 DJ Delorie <dj@redhat.com>
1316 * rx.h (rx_decode_opcode) (mvtipl): Add.
1317 (mvtcp, mvfcp, opecp): Remove.
1319 2009-11-02 Paul Brook <paul@codesourcery.com>
1321 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1322 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1323 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1324 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1325 FPU_ARCH_NEON_VFP_V4): Define.
1327 2009-10-23 Doug Evans <dje@sebabeach.org>
1329 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1330 * cgen.h: Update. Improve multi-inclusion macro name.
1332 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1334 * ppc.h (PPC_OPCODE_476): Define.
1336 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1338 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1340 2009-09-29 DJ Delorie <dj@redhat.com>
1344 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1346 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1348 2009-09-21 Ben Elliston <bje@au.ibm.com>
1350 * ppc.h (PPC_OPCODE_PPCA2): New.
1352 2009-09-05 Martin Thuresson <martin@mtme.org>
1354 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1356 2009-08-29 Martin Thuresson <martin@mtme.org>
1358 * tic30.h (template): Rename type template to
1359 insn_template. Updated code to use new name.
1360 * tic54x.h (template): Rename type template to
1363 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1365 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1367 2009-06-11 Anthony Green <green@moxielogic.com>
1369 * moxie.h (MOXIE_F3_PCREL): Define.
1370 (moxie_form3_opc_info): Grow.
1372 2009-06-06 Anthony Green <green@moxielogic.com>
1374 * moxie.h (MOXIE_F1_M): Define.
1376 2009-04-15 Anthony Green <green@moxielogic.com>
1380 2009-04-06 DJ Delorie <dj@redhat.com>
1382 * h8300.h: Add relaxation attributes to MOVA opcodes.
1384 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1386 * ppc.h (ppc_parse_cpu): Declare.
1388 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1390 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1391 and _IMM11 for mbitclr and mbitset.
1392 * score-datadep.h: Update dependency information.
1394 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1396 * ppc.h (PPC_OPCODE_POWER7): New.
1398 2009-02-06 Doug Evans <dje@google.com>
1400 * i386.h: Add comment regarding sse* insns and prefixes.
1402 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1404 * mips.h (INSN_XLR): Define.
1405 (INSN_CHIP_MASK): Update.
1407 (OPCODE_IS_MEMBER): Update.
1408 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1410 2009-01-28 Doug Evans <dje@google.com>
1412 * opcode/i386.h: Add multiple inclusion protection.
1413 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1414 (EDI_REG_NUM): New macros.
1415 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1416 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1417 (REX_PREFIX_P): New macro.
1419 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1421 * ppc.h (struct powerpc_opcode): New field "deprecated".
1422 (PPC_OPCODE_NOPOWER4): Delete.
1424 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1426 * mips.h: Define CPU_R14000, CPU_R16000.
1427 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1429 2008-11-18 Catherine Moore <clm@codesourcery.com>
1431 * arm.h (FPU_NEON_FP16): New.
1432 (FPU_ARCH_NEON_FP16): New.
1434 2008-11-06 Chao-ying Fu <fu@mips.com>
1436 * mips.h: Doucument '1' for 5-bit sync type.
1438 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1440 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1443 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1445 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1447 2008-07-30 Michael J. Eager <eager@eagercon.com>
1449 * ppc.h (PPC_OPCODE_405): Define.
1450 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1452 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1454 * ppc.h (ppc_cpu_t): New typedef.
1455 (struct powerpc_opcode <flags>): Use it.
1456 (struct powerpc_operand <insert, extract>): Likewise.
1457 (struct powerpc_macro <flags>): Likewise.
1459 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1461 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1462 Update comment before MIPS16 field descriptors to mention MIPS16.
1463 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1465 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1466 New bit masks and shift counts for cins and exts.
1468 * mips.h: Document new field descriptors +Q.
1469 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1471 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1473 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1474 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1476 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1478 * ppc.h: (PPC_OPCODE_E500MC): New.
1480 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1482 * i386.h (MAX_OPERANDS): Set to 5.
1483 (MAX_MNEM_SIZE): Changed to 20.
1485 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1487 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1489 2008-03-09 Paul Brook <paul@codesourcery.com>
1491 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1493 2008-03-04 Paul Brook <paul@codesourcery.com>
1495 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1496 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1497 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1499 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1500 Nick Clifton <nickc@redhat.com>
1503 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1504 with a 32-bit displacement but without the top bit of the 4th byte
1507 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1509 * cr16.h (cr16_num_optab): Declared.
1511 2008-02-14 Hakan Ardo <hakan@debian.org>
1514 * avr.h (AVR_ISA_2xxe): Define.
1516 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1518 * mips.h: Update copyright.
1519 (INSN_CHIP_MASK): New macro.
1520 (INSN_OCTEON): New macro.
1521 (CPU_OCTEON): New macro.
1522 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1524 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1526 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1528 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1530 * avr.h (AVR_ISA_USB162): Add new opcode set.
1531 (AVR_ISA_AVR3): Likewise.
1533 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1535 * mips.h (INSN_LOONGSON_2E): New.
1536 (INSN_LOONGSON_2F): New.
1537 (CPU_LOONGSON_2E): New.
1538 (CPU_LOONGSON_2F): New.
1539 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1541 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1543 * mips.h (INSN_ISA*): Redefine certain values as an
1544 enumeration. Update comments.
1545 (mips_isa_table): New.
1546 (ISA_MIPS*): Redefine to match enumeration.
1547 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1550 2007-08-08 Ben Elliston <bje@au.ibm.com>
1552 * ppc.h (PPC_OPCODE_PPCPS): New.
1554 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1556 * m68k.h: Document j K & E.
1558 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1560 * cr16.h: New file for CR16 target.
1562 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1564 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1566 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1568 * m68k.h (mcfisa_c): New.
1569 (mcfusp, mcf_mask): Adjust.
1571 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1573 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1574 (num_powerpc_operands): Declare.
1575 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1576 (PPC_OPERAND_PLUS1): Define.
1578 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1580 * i386.h (REX_MODE64): Renamed to ...
1582 (REX_EXTX): Renamed to ...
1584 (REX_EXTY): Renamed to ...
1586 (REX_EXTZ): Renamed to ...
1589 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1591 * i386.h: Add entries from config/tc-i386.h and move tables
1592 to opcodes/i386-opc.h.
1594 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1596 * i386.h (FloatDR): Removed.
1597 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1599 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1601 * spu-insns.h: Add soma double-float insns.
1603 2007-02-20 Thiemo Seufer <ths@mips.com>
1604 Chao-Ying Fu <fu@mips.com>
1606 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1607 (INSN_DSPR2): Add flag for DSP R2 instructions.
1608 (M_BALIGN): New macro.
1610 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1612 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1613 and Seg3ShortFrom with Shortform.
1615 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1618 * i386.h (i386_optab): Put the real "test" before the pseudo
1621 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1623 * m68k.h (m68010up): OR fido_a.
1625 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1627 * m68k.h (fido_a): New.
1629 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1631 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1632 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1635 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1637 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1639 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1641 * score-inst.h (enum score_insn_type): Add Insn_internal.
1643 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1644 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1645 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1646 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1647 Alan Modra <amodra@bigpond.net.au>
1649 * spu-insns.h: New file.
1652 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1654 * ppc.h (PPC_OPCODE_CELL): Define.
1656 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1658 * i386.h : Modify opcode to support for the change in POPCNT opcode
1659 in amdfam10 architecture.
1661 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1663 * i386.h: Replace CpuMNI with CpuSSSE3.
1665 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1666 Joseph Myers <joseph@codesourcery.com>
1667 Ian Lance Taylor <ian@wasabisystems.com>
1668 Ben Elliston <bje@wasabisystems.com>
1670 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1672 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1674 * score-datadep.h: New file.
1675 * score-inst.h: New file.
1677 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1679 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1680 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1681 movdq2q and movq2dq.
1683 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1684 Michael Meissner <michael.meissner@amd.com>
1686 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1688 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386.h (i386_optab): Add "nop" with memory reference.
1692 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1694 * i386.h (i386_optab): Update comment for 64bit NOP.
1696 2006-06-06 Ben Elliston <bje@au.ibm.com>
1697 Anton Blanchard <anton@samba.org>
1699 * ppc.h (PPC_OPCODE_POWER6): Define.
1702 2006-06-05 Thiemo Seufer <ths@mips.com>
1704 * mips.h: Improve description of MT flags.
1706 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1708 * m68k.h (mcf_mask): Define.
1710 2006-05-05 Thiemo Seufer <ths@mips.com>
1711 David Ung <davidu@mips.com>
1713 * mips.h (enum): Add macro M_CACHE_AB.
1715 2006-05-04 Thiemo Seufer <ths@mips.com>
1716 Nigel Stephens <nigel@mips.com>
1717 David Ung <davidu@mips.com>
1719 * mips.h: Add INSN_SMARTMIPS define.
1721 2006-04-30 Thiemo Seufer <ths@mips.com>
1722 David Ung <davidu@mips.com>
1724 * mips.h: Defines udi bits and masks. Add description of
1725 characters which may appear in the args field of udi
1728 2006-04-26 Thiemo Seufer <ths@networkno.de>
1730 * mips.h: Improve comments describing the bitfield instruction
1733 2006-04-26 Julian Brown <julian@codesourcery.com>
1735 * arm.h (FPU_VFP_EXT_V3): Define constant.
1736 (FPU_NEON_EXT_V1): Likewise.
1737 (FPU_VFP_HARD): Update.
1738 (FPU_VFP_V3): Define macro.
1739 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1741 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1743 * avr.h (AVR_ISA_PWMx): New.
1745 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1747 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1748 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1749 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1750 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1751 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1753 2006-03-10 Paul Brook <paul@codesourcery.com>
1755 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1757 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1759 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1760 first. Correct mask of bb "B" opcode.
1762 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1764 * i386.h (i386_optab): Support Intel Merom New Instructions.
1766 2006-02-24 Paul Brook <paul@codesourcery.com>
1768 * arm.h: Add V7 feature bits.
1770 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1772 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1774 2006-01-31 Paul Brook <paul@codesourcery.com>
1775 Richard Earnshaw <rearnsha@arm.com>
1777 * arm.h: Use ARM_CPU_FEATURE.
1778 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1779 (arm_feature_set): Change to a structure.
1780 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1781 ARM_FEATURE): New macros.
1783 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1785 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1786 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1787 (ADD_PC_INCR_OPCODE): Don't define.
1789 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1792 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1794 2005-11-14 David Ung <davidu@mips.com>
1796 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1797 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1798 save/restore encoding of the args field.
1800 2005-10-28 Dave Brolley <brolley@redhat.com>
1802 Contribute the following changes:
1803 2005-02-16 Dave Brolley <brolley@redhat.com>
1805 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1806 cgen_isa_mask_* to cgen_bitset_*.
1809 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1811 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1812 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1813 (CGEN_CPU_TABLE): Make isas a ponter.
1815 2003-09-29 Dave Brolley <brolley@redhat.com>
1817 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1818 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1819 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1821 2002-12-13 Dave Brolley <brolley@redhat.com>
1823 * cgen.h (symcat.h): #include it.
1824 (cgen-bitset.h): #include it.
1825 (CGEN_ATTR_VALUE_TYPE): Now a union.
1826 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1827 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1828 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1829 * cgen-bitset.h: New file.
1831 2005-09-30 Catherine Moore <clm@cm00re.com>
1835 2005-10-24 Jan Beulich <jbeulich@novell.com>
1837 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1840 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1842 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1843 Add FLAG_STRICT to pa10 ftest opcode.
1845 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1847 * hppa.h (pa_opcodes): Remove lha entries.
1849 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1851 * hppa.h (FLAG_STRICT): Revise comment.
1852 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1853 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1856 2005-09-30 Catherine Moore <clm@cm00re.com>
1860 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1862 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1864 2005-09-06 Chao-ying Fu <fu@mips.com>
1866 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1867 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1869 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1870 (INSN_ASE_MASK): Update to include INSN_MT.
1871 (INSN_MT): New define for MT ASE.
1873 2005-08-25 Chao-ying Fu <fu@mips.com>
1875 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1876 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1877 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1878 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1879 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1880 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1882 (INSN_DSP): New define for DSP ASE.
1884 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1888 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1890 * ppc.h (PPC_OPCODE_E300): Define.
1892 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1894 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1896 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1899 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1902 2005-07-27 Jan Beulich <jbeulich@novell.com>
1904 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1905 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1906 Add movq-s as 64-bit variants of movd-s.
1908 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1910 * hppa.h: Fix punctuation in comment.
1912 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1913 implicit space-register addressing. Set space-register bits on opcodes
1914 using implicit space-register addressing. Add various missing pa20
1915 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1916 space-register addressing. Use "fE" instead of "fe" in various
1919 2005-07-18 Jan Beulich <jbeulich@novell.com>
1921 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1923 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1925 * i386.h (i386_optab): Support Intel VMX Instructions.
1927 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1929 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1931 2005-07-05 Jan Beulich <jbeulich@novell.com>
1933 * i386.h (i386_optab): Add new insns.
1935 2005-07-01 Nick Clifton <nickc@redhat.com>
1937 * sparc.h: Add typedefs to structure declarations.
1939 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1942 * i386.h (i386_optab): Update comments for 64bit addressing on
1943 mov. Allow 64bit addressing for mov and movq.
1945 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1947 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1948 respectively, in various floating-point load and store patterns.
1950 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1952 * hppa.h (FLAG_STRICT): Correct comment.
1953 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1954 PA 2.0 mneumonics when equivalent. Entries with cache control
1955 completers now require PA 1.1. Adjust whitespace.
1957 2005-05-19 Anton Blanchard <anton@samba.org>
1959 * ppc.h (PPC_OPCODE_POWER5): Define.
1961 2005-05-10 Nick Clifton <nickc@redhat.com>
1963 * Update the address and phone number of the FSF organization in
1964 the GPL notices in the following files:
1965 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1966 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1967 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1968 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1969 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1970 tic54x.h, tic80.h, v850.h, vax.h
1972 2005-05-09 Jan Beulich <jbeulich@novell.com>
1974 * i386.h (i386_optab): Add ht and hnt.
1976 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1978 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1979 Add xcrypt-ctr. Provide aliases without hyphens.
1981 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1983 Moved from ../ChangeLog
1985 2005-04-12 Paul Brook <paul@codesourcery.com>
1986 * m88k.h: Rename psr macros to avoid conflicts.
1988 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1989 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1990 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1991 and ARM_ARCH_V6ZKT2.
1993 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1994 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1995 Remove redundant instruction types.
1996 (struct argument): X_op - new field.
1997 (struct cst4_entry): Remove.
1998 (no_op_insn): Declare.
2000 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2001 * crx.h (enum argtype): Rename types, remove unused types.
2003 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2004 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2005 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2006 (enum operand_type): Rearrange operands, edit comments.
2007 replace us<N> with ui<N> for unsigned immediate.
2008 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2009 displacements (respectively).
2010 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2011 (instruction type): Add NO_TYPE_INS.
2012 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2013 (operand_entry): New field - 'flags'.
2014 (operand flags): New.
2016 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2017 * crx.h (operand_type): Remove redundant types i3, i4,
2019 Add new unsigned immediate types us3, us4, us5, us16.
2021 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2023 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2024 adjust them accordingly.
2026 2005-04-01 Jan Beulich <jbeulich@novell.com>
2028 * i386.h (i386_optab): Add rdtscp.
2030 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2032 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2033 between memory and segment register. Allow movq for moving between
2034 general-purpose register and segment register.
2036 2005-02-09 Jan Beulich <jbeulich@novell.com>
2039 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2040 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2043 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2045 * m68k.h (m68008, m68ec030, m68882): Remove.
2047 (cpu_m68k, cpu_cf): New.
2048 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2049 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2051 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2053 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2054 * cgen.h (enum cgen_parse_operand_type): Add
2055 CGEN_PARSE_OPERAND_SYMBOLIC.
2057 2005-01-21 Fred Fish <fnf@specifixinc.com>
2059 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2060 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2061 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2063 2005-01-19 Fred Fish <fnf@specifixinc.com>
2065 * mips.h (struct mips_opcode): Add new pinfo2 member.
2066 (INSN_ALIAS): New define for opcode table entries that are
2067 specific instances of another entry, such as 'move' for an 'or'
2068 with a zero operand.
2069 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2070 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2072 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2074 * mips.h (CPU_RM9000): Define.
2075 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2077 2004-11-25 Jan Beulich <jbeulich@novell.com>
2079 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2080 to/from test registers are illegal in 64-bit mode. Add missing
2081 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2082 (previously one had to explicitly encode a rex64 prefix). Re-enable
2083 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2084 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2086 2004-11-23 Jan Beulich <jbeulich@novell.com>
2088 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2089 available only with SSE2. Change the MMX additions introduced by SSE
2090 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2091 instructions by their now designated identifier (since combining i686
2092 and 3DNow! does not really imply 3DNow!A).
2094 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2096 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2097 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2099 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2100 Vineet Sharma <vineets@noida.hcltech.com>
2102 * maxq.h: New file: Disassembly information for the maxq port.
2104 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2106 * i386.h (i386_optab): Put back "movzb".
2108 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2110 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2111 comments. Remove member cris_ver_sim. Add members
2112 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2113 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2114 (struct cris_support_reg, struct cris_cond15): New types.
2115 (cris_conds15): Declare.
2116 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2117 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2118 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2119 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2120 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2121 SIZE_FIELD_UNSIGNED.
2123 2004-11-04 Jan Beulich <jbeulich@novell.com>
2125 * i386.h (sldx_Suf): Remove.
2126 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2127 (q_FP): Define, implying no REX64.
2128 (x_FP, sl_FP): Imply FloatMF.
2129 (i386_optab): Split reg and mem forms of moving from segment registers
2130 so that the memory forms can ignore the 16-/32-bit operand size
2131 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2132 all non-floating-point instructions. Unite 32- and 64-bit forms of
2133 movsx, movzx, and movd. Adjust floating point operations for the above
2134 changes to the *FP macros. Add DefaultSize to floating point control
2135 insns operating on larger memory ranges. Remove left over comments
2136 hinting at certain insns being Intel-syntax ones where the ones
2137 actually meant are already gone.
2139 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2141 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2144 2004-09-30 Paul Brook <paul@codesourcery.com>
2146 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2147 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2149 2004-09-11 Theodore A. Roth <troth@openavr.org>
2151 * avr.h: Add support for
2152 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2154 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2156 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2158 2004-08-24 Dmitry Diky <diwil@spec.ru>
2160 * msp430.h (msp430_opc): Add new instructions.
2161 (msp430_rcodes): Declare new instructions.
2162 (msp430_hcodes): Likewise..
2164 2004-08-13 Nick Clifton <nickc@redhat.com>
2167 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2170 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2172 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2174 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2176 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2178 2004-07-21 Jan Beulich <jbeulich@novell.com>
2180 * i386.h: Adjust instruction descriptions to better match the
2183 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2185 * arm.h: Remove all old content. Replace with architecture defines
2186 from gas/config/tc-arm.c.
2188 2004-07-09 Andreas Schwab <schwab@suse.de>
2190 * m68k.h: Fix comment.
2192 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2196 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2198 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2200 2004-05-24 Peter Barada <peter@the-baradas.com>
2202 * m68k.h: Add 'size' to m68k_opcode.
2204 2004-05-05 Peter Barada <peter@the-baradas.com>
2206 * m68k.h: Switch from ColdFire chip name to core variant.
2208 2004-04-22 Peter Barada <peter@the-baradas.com>
2210 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2211 descriptions for new EMAC cases.
2212 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2213 handle Motorola MAC syntax.
2214 Allow disassembly of ColdFire V4e object files.
2216 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2218 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2220 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2222 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2224 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2226 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2228 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2230 * i386.h (i386_optab): Added xstore/xcrypt insns.
2232 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2234 * h8300.h (32bit ldc/stc): Add relaxing support.
2236 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2238 * h8300.h (BITOP): Pass MEMRELAX flag.
2240 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2242 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2245 For older changes see ChangeLog-9103
2247 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2249 Copying and distribution of this file, with or without modification,
2250 are permitted in any medium without royalty provided the copyright
2251 notice and this notice are preserved.
2257 version-control: never
projects / deliverable / binutils-gdb.git / blob