include/opcode/ChangeLog

   1 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
   4         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
   5         (MIPS16_INSN_COND_BRANCH): Delete.
   6
   7 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
   8             Kirill Yukhin  <kirill.yukhin@intel.com>
   9             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
  10
  11         * i386.h (BND_PREFIX_OPCODE): New.
  12
  13 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  14
  15         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
  16         OP_SAVE_RESTORE_LIST.
  17         (decode_mips16_operand): Declare.
  18
  19 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  20
  21         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
  22         (mips_operand, mips_int_operand, mips_mapped_int_operand)
  23         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
  24         (mips_pcrel_operand): New structures.
  25         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
  26         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
  27         (decode_mips_operand, decode_micromips_operand): Declare.
  28
  29 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  30
  31         * mips.h: Document MIPS16 "I" opcode.
  32
  33 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  34
  35         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
  36         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
  37         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
  38         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
  39         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
  40         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
  41         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
  42         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
  43         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
  44         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
  45         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
  46         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
  47         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
  48         Rename to...
  49         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
  50         (M_USD_AB): ...these.
  51
  52 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  53
  54         * mips.h: Remove documentation of "[" and "]".  Update documentation
  55         of "k" and the MDMX formats.
  56
  57 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  58
  59         * mips.h: Update documentation of "+s" and "+S".
  60
  61 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  62
  63         * mips.h: Document "+i".
  64
  65 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  66
  67         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
  68         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
  69         Delete.
  70         (INSN2_WRITE_GPR_MHI): Rename to...
  71         (INSN2_WRITE_GPR_MH): ...this.
  72
  73 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  74
  75         * mips.h: Remove documentation of "+D" and "+T".
  76
  77 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
  78
  79         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
  80         Use "source" rather than "destination" for microMIPS "G".
  81
  82 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  83
  84         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
  85         values.
  86
  87 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  88
  89         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  90
  91 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  92             Maciej W. Rozycki  <macro@codesourcery.com>
  93             Chao-Ying Fu  <fu@mips.com>
  94
  95         * mips.h (OP_SH_EVAOFFSET): Define.
  96         (OP_MASK_EVAOFFSET): Define.
  97         (INSN_ASE_MASK): Delete.
  98         (ASE_EVA): Define.
  99         (M_CACHEE_AB, M_CACHEE_OB): New.
 100         (M_LBE_OB, M_LBE_AB): New.
 101         (M_LBUE_OB, M_LBUE_AB): New.
 102         (M_LHE_OB, M_LHE_AB): New.
 103         (M_LHUE_OB, M_LHUE_AB): New.
 104         (M_LLE_AB, M_LLE_OB): New.
 105         (M_LWE_OB, M_LWE_AB): New.
 106         (M_LWLE_AB, M_LWLE_OB): New.
 107         (M_LWRE_AB, M_LWRE_OB): New.
 108         (M_PREFE_AB, M_PREFE_OB): New.
 109         (M_SCE_AB, M_SCE_OB): New.
 110         (M_SBE_OB, M_SBE_AB): New.
 111         (M_SHE_OB, M_SHE_AB): New.
 112         (M_SWE_OB, M_SWE_AB): New.
 113         (M_SWLE_AB, M_SWLE_OB): New.
 114         (M_SWRE_AB, M_SWRE_OB): New.
 115         (MICROMIPSOP_SH_EVAOFFSET): Define.
 116         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 117
 118 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 119
 120         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 121
 122 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 123
 124         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 125
 126 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 127
 128         * mips.h (OP_MASK_CODE10): Correct definition.
 129         (OP_SH_CODE10): Likewise.
 130         Add a comment that "+J" is used now for OP_*CODE10.
 131         (INSN_ASE_MASK): Update.
 132         (INSN_VIRT): New macro.
 133         (INSN_VIRT64): New macro
 134
 135 2013-05-02  Nick Clifton  <nickc@redhat.com>
 136
 137         * msp430.h: Add patterns for MSP430X instructions.
 138
 139 2013-04-06  David S. Miller  <davem@davemloft.net>
 140
 141         * sparc.h (F_PREFERRED): Define.
 142         (F_PREF_ALIAS): Define.
 143
 144 2013-04-03  Nick Clifton  <nickc@redhat.com>
 145
 146         * v850.h (V850_INVERSE_PCREL): Define.
 147
 148 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 149
 150         PR binutils/15068
 151         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 152
 153 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 154
 155         PR binutils/15068
 156         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 157         Add 16-bit opcodes.
 158         * tic6xc-opcode-table.h: Add 16-bit insns.
 159         * tic6x.h: Add support for 16-bit insns.
 160
 161 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 162
 163         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 164         and mov.b/w/l Rs,@(d:32,ERd).
 165
 166 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 167
 168         PR gas/15082
 169         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 170         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 171         tic6x_operand_xregpair operand coding type.
 172         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 173         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 174         TIC6X_FLAG_NO_CROSS.
 175
 176 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 177
 178         PR gas/15095
 179         * tic6x.h (enum tic6x_coding_method): Add
 180         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 181         separately the msb and lsb of a register pair.  This is needed to
 182         encode the opcodes in the same way as TI assembler does.
 183         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 184         and rsqrdp opcodes to use the new field coding types.
 185
 186 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 187
 188         * arm.h (CRC_EXT_ARMV8): New constant.
 189         (ARCH_CRC_ARMV8): New macro.
 190
 191 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 192
 193         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 194
 195 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 196             Andrew Jenner <andrew@codesourcery.com>
 197
 198         Based on patches from Altera Corporation.
 199
 200         * nios2.h: New file.
 201
 202 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 203
 204         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 205
 206 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 207
 208         PR gas/15069
 209         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 210
 211 2013-01-24  Nick Clifton  <nickc@redhat.com>
 212
 213         * v850.h: Add e3v5 support.
 214
 215 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 216
 217         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 218
 219 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 220
 221         * ppc.h (PPC_OPCODE_POWER8): New define.
 222         (PPC_OPCODE_HTM): Likewise.
 223
 224 2013-01-10  Will Newton <will.newton@imgtec.com>
 225
 226         * metag.h: New file.
 227
 228 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 229
 230         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 231         (match_opcode): Rename to cr16_match_opcode.
 232
 233 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 234
 235         * mips.h: Add support for r5900 instructions including lq and sq.
 236
 237 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 238
 239         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 240         (make_instruction,match_opcode): Added function prototypes.
 241         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 242
 243 2012-11-23  Alan Modra  <amodra@gmail.com>
 244
 245         * ppc.h (ppc_parse_cpu): Update prototype.
 246
 247 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 248
 249         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 250         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 251
 252 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 253
 254         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 255
 256 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 257
 258         * ia64.h (ia64_opnd): Add new operand types.
 259
 260 2012-08-21  David S. Miller  <davem@davemloft.net>
 261
 262         * sparc.h (F3F4): New macro.
 263
 264 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 265             Laurent Desnogues  <laurent.desnogues@arm.com>
 266             Jim MacArthur  <jim.macarthur@arm.com>
 267             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 268             Nigel Stephens  <nigel.stephens@arm.com>
 269             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 270             Richard Earnshaw  <rearnsha@arm.com>
 271             Sofiane Naci  <sofiane.naci@arm.com>
 272             Tejas Belagod  <tejas.belagod@arm.com>
 273             Yufeng Zhang  <yufeng.zhang@arm.com>
 274
 275         * aarch64.h: New file.
 276
 277 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 278             Maciej W. Rozycki  <macro@codesourcery.com>
 279
 280         * mips.h (mips_opcode): Add the exclusions field.
 281         (OPCODE_IS_MEMBER): Remove macro.
 282         (cpu_is_member): New inline function.
 283         (opcode_is_member): Likewise.
 284
 285 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 286             Catherine Moore  <clm@codesourcery.com>
 287             Maciej W. Rozycki  <macro@codesourcery.com>
 288
 289         * mips.h: Document microMIPS DSP ASE usage.
 290         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 291         microMIPS DSP ASE support.
 292         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 293         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 294         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 295         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 296         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 297         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 298         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 299
 300 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 301
 302         * mips.h: Fix a typo in description.
 303
 304 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 305
 306         * avr.h: (AVR_ISA_XCH): New define.
 307         (AVR_ISA_XMEGA): Use it.
 308         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 309
 310 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 311
 312         * m68hc11.h: Add XGate definitions.
 313         (struct m68hc11_opcode): Add xg_mask field.
 314
 315 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 316             Maciej W. Rozycki  <macro@codesourcery.com>
 317             Rhonda Wittels  <rhonda@codesourcery.com>
 318
 319         * ppc.h (PPC_OPCODE_VLE): New definition.
 320         (PPC_OP_SA): New macro.
 321         (PPC_OP_SE_VLE): New macro.
 322         (PPC_OP): Use a variable shift amount.
 323         (powerpc_operand): Update comments.
 324         (PPC_OPSHIFT_INV): New macro.
 325         (PPC_OPERAND_CR): Replace with...
 326         (PPC_OPERAND_CR_BIT): ...this and
 327         (PPC_OPERAND_CR_REG): ...this.
 328
 329
 330 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 331
 332         * xgate.h: Header file for XGATE assembler.
 333
 334 2012-04-27  David S. Miller  <davem@davemloft.net>
 335
 336         * sparc.h: Document new arg code' )' for crypto RS3
 337         immediates.
 338
 339         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 340         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 341         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 342         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 343         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 344         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 345         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 346         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 347         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 348         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 349         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 350
 351 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 352
 353         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 354
 355 2012-02-27  Alan Modra  <amodra@gmail.com>
 356
 357         * crx.h (cst4_map): Update declaration.
 358
 359 2012-02-25  Walter Lee  <walt@tilera.com>
 360
 361         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 362         TILEGX_OPC_LD_TLS.
 363         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 364         TILEPRO_OPC_LW_TLS_SN.
 365
 366 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 369         (XRELEASE_PREFIX_OPCODE): Likewise.
 370
 371 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 372             Adam Nemet  <anemet@caviumnetworks.com>
 373
 374         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 375         (INSN_OCTEON2): New macro.
 376         (CPU_OCTEON2): New macro.
 377         (OPCODE_IS_MEMBER): Add Octeon2.
 378
 379 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 380
 381         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 382         (INSN_OCTEONP): New macro.
 383         (CPU_OCTEONP): New macro.
 384         (OPCODE_IS_MEMBER): Add Octeon+.
 385         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 386
 387 2011-11-01  DJ Delorie  <dj@redhat.com>
 388
 389         * rl78.h: New file.
 390
 391 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 392
 393         * mips.h: Fix a typo in description.
 394
 395 2011-09-21  David S. Miller  <davem@davemloft.net>
 396
 397         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 398         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 399         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 400         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 401
 402 2011-08-09  Chao-ying Fu  <fu@mips.com>
 403             Maciej W. Rozycki  <macro@codesourcery.com>
 404
 405         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 406         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 407         (INSN_ASE_MASK): Add the MCU bit.
 408         (INSN_MCU): New macro.
 409         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 410         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 411
 412 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 413
 414         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 415         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 416         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 417         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 418         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 419         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 420         (INSN2_READ_GPR_MMN): Likewise.
 421         (INSN2_READ_FPR_D): Change the bit used.
 422         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 423         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 424         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 425         (INSN2_COND_BRANCH): Likewise.
 426         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 427         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 428         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 429         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 430         (INSN2_MOD_GPR_MN): Likewise.
 431
 432 2011-08-05  David S. Miller  <davem@davemloft.net>
 433
 434         * sparc.h: Document new format codes '4', '5', and '('.
 435         (OPF_LOW4, RS3): New macros.
 436
 437 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 438
 439         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 440         order of flags documented.
 441
 442 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 443
 444         * mips.h: Clarify the description of microMIPS instruction
 445         manipulation macros.
 446         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 447
 448 2011-07-24  Chao-ying Fu  <fu@mips.com>
 449             Maciej W. Rozycki  <macro@codesourcery.com>
 450
 451         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 452         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 453         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 454         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 455         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 456         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 457         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 458         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 459         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 460         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 461         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 462         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 463         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 464         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 465         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 466         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 467         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 468         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 469         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 470         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 471         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 472         (INSN_WRITE_GPR_S): New macro.
 473         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 474         (INSN2_READ_FPR_D): Likewise.
 475         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 476         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 477         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 478         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 479         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 480         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 481         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 482         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 483         (CPU_MICROMIPS): New macro.
 484         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 485         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 486         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 487         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 488         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 489         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 490         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 491         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 492         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 493         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 494         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 495         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 496         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 497         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 498         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 499         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 500         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 501         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 502         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 503         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 504         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 505         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 506         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 507         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 508         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 509         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 510         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 511         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 512         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 513         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 514         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 515         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 516         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 517         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 518         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 519         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 520         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 521         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 522         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 523         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 524         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 525         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 526         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 527         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 528         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 529         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 530         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 531         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 532         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 533         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 534         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 535         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 536         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 537         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 538         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 539         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 540         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 541         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 542         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 543         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 544         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 545         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 546         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 547         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 548         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 549         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 550         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 551         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 552         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 553         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 554         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 555         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 556         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 557         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 558         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 559         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 560         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 561         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 562         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 563         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 564         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 565         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 566         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 567         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 568         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 569         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 570         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 571         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 572         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 573         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 574         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 575         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 576         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 577         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 578         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 579         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 580         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 581         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 582         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 583         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 584         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 585         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 586         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 587         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 588         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 589         (micromips_opcodes): New declaration.
 590         (bfd_micromips_num_opcodes): Likewise.
 591
 592 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 593
 594         * mips.h (INSN_TRAP): Rename to...
 595         (INSN_NO_DELAY_SLOT): ... this.
 596         (INSN_SYNC): Remove macro.
 597
 598 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 599
 600         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 601         a duplicate of AVR_ISA_SPM.
 602
 603 2011-07-01  Nick Clifton  <nickc@redhat.com>
 604
 605         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 606
 607 2011-06-18  Robin Getz  <robin.getz@analog.com>
 608
 609         * bfin.h (is_macmod_signed): New func
 610
 611 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 612
 613         * bfin.h (is_macmod_pmove): Add missing space before func args.
 614         (is_macmod_hmove): Likewise.
 615
 616 2011-06-13  Walter Lee  <walt@tilera.com>
 617
 618         * tilegx.h: New file.
 619         * tilepro.h: New file.
 620
 621 2011-05-31  Paul Brook  <paul@codesourcery.com>
 622
 623         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 624
 625 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 626
 627         * s390.h: Replace S390_OPERAND_REG_EVEN with
 628         S390_OPERAND_REG_PAIR.
 629
 630 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 631
 632         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 633
 634 2011-04-18  Julian Brown  <julian@codesourcery.com>
 635
 636         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 637
 638 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 639
 640         PR gas/12296
 641         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 642
 643 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 644
 645         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 646         New instruction set flags.
 647         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 648
 649 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 650
 651         * mips.h (M_PREF_AB): New enum value.
 652
 653 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 654
 655         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 656         M_IU): Define.
 657         (is_macmod_pmove, is_macmod_hmove): New functions.
 658
 659 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 660
 661         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 662
 663 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 664
 665         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 666         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 667
 668 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 669
 670         PR gas/11395
 671         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 672         "bb" entries.
 673
 674 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 675
 676         PR gas/11395
 677         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 678
 679 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 680
 681         * mips.h: Update commentary after last commit.
 682
 683 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 684
 685         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 686         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 687         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 688
 689 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 690
 691         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 692
 693 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 694
 695         * mips.h: Fix previous commit.
 696
 697 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 698
 699         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 700         (INSN_LOONGSON_3A): Clear bit 31.
 701
 702 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 703
 704         PR gas/12198
 705         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 706         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 707         (ARM_ARCH_V6M_ONLY): New define.
 708
 709 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 710
 711         * mips.h (INSN_LOONGSON_3A): Defined.
 712         (CPU_LOONGSON_3A): Defined.
 713         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 714
 715 2010-10-09  Matt Rice  <ratmice@gmail.com>
 716
 717         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 718         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 719
 720 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 721
 722         * arm.h (ARM_EXT_VIRT): New define.
 723         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 724         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 725         Extensions.
 726
 727 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 728
 729         * arm.h (ARM_AEXT_ADIV): New define.
 730         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 731
 732 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 733
 734         * arm.h (ARM_EXT_OS): New define.
 735         (ARM_AEXT_V6SM): Likewise.
 736         (ARM_ARCH_V6SM): Likewise.
 737
 738 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 739
 740         * arm.h (ARM_EXT_MP): Add.
 741         (ARM_ARCH_V7A_MP): Likewise.
 742
 743 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 744
 745         * bfin.h: Declare pseudoChr structs/defines.
 746
 747 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 748
 749         * bfin.h: Strip trailing whitespace.
 750
 751 2010-07-29  DJ Delorie  <dj@redhat.com>
 752
 753         * rx.h (RX_Operand_Type): Add TwoReg.
 754         (RX_Opcode_ID): Remove ediv and ediv2.
 755
 756 2010-07-27  DJ Delorie  <dj@redhat.com>
 757
 758         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 759
 760 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 761             Ina Pandit  <ina.pandit@kpitcummins.com>
 762
 763         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 764         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 765         PROCESSOR_V850E2_ALL.
 766         Remove PROCESSOR_V850EA support.
 767         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 768         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 769         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 770         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 771         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 772         V850_OPERAND_PERCENT.
 773         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 774         V850_NOT_R0.
 775         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 776         and V850E_PUSH_POP
 777
 778 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 779
 780         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 781         (MIPS16_INSN_BRANCH): Rename to...
 782         (MIPS16_INSN_COND_BRANCH): ... this.
 783
 784 2010-07-03  Alan Modra  <amodra@gmail.com>
 785
 786         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 787         Renumber other PPC_OPCODE defines.
 788
 789 2010-07-03  Alan Modra  <amodra@gmail.com>
 790
 791         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 792
 793 2010-06-29  Alan Modra  <amodra@gmail.com>
 794
 795         * maxq.h: Delete file.
 796
 797 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 798
 799         * ppc.h (PPC_OPCODE_E500): Define.
 800
 801 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 802
 803         * opcode/mips.h (INSN_MIPS16): Remove.
 804
 805 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 806
 807         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 808
 809 2010-04-15  Nick Clifton  <nickc@redhat.com>
 810
 811         * alpha.h: Update copyright notice to use GPLv3.
 812         * arc.h: Likewise.
 813         * arm.h: Likewise.
 814         * avr.h: Likewise.
 815         * bfin.h: Likewise.
 816         * cgen.h: Likewise.
 817         * convex.h: Likewise.
 818         * cr16.h: Likewise.
 819         * cris.h: Likewise.
 820         * crx.h: Likewise.
 821         * d10v.h: Likewise.
 822         * d30v.h: Likewise.
 823         * dlx.h: Likewise.
 824         * h8300.h: Likewise.
 825         * hppa.h: Likewise.
 826         * i370.h: Likewise.
 827         * i386.h: Likewise.
 828         * i860.h: Likewise.
 829         * i960.h: Likewise.
 830         * ia64.h: Likewise.
 831         * m68hc11.h: Likewise.
 832         * m68k.h: Likewise.
 833         * m88k.h: Likewise.
 834         * maxq.h: Likewise.
 835         * mips.h: Likewise.
 836         * mmix.h: Likewise.
 837         * mn10200.h: Likewise.
 838         * mn10300.h: Likewise.
 839         * msp430.h: Likewise.
 840         * np1.h: Likewise.
 841         * ns32k.h: Likewise.
 842         * or32.h: Likewise.
 843         * pdp11.h: Likewise.
 844         * pj.h: Likewise.
 845         * pn.h: Likewise.
 846         * ppc.h: Likewise.
 847         * pyr.h: Likewise.
 848         * rx.h: Likewise.
 849         * s390.h: Likewise.
 850         * score-datadep.h: Likewise.
 851         * score-inst.h: Likewise.
 852         * sparc.h: Likewise.
 853         * spu-insns.h: Likewise.
 854         * spu.h: Likewise.
 855         * tic30.h: Likewise.
 856         * tic4x.h: Likewise.
 857         * tic54x.h: Likewise.
 858         * tic80.h: Likewise.
 859         * v850.h: Likewise.
 860         * vax.h: Likewise.
 861
 862 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 863
 864         * tic6x-control-registers.h, tic6x-insn-formats.h,
 865         tic6x-opcode-table.h, tic6x.h: New.
 866
 867 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 868
 869         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 870
 871 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 872
 873         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 874
 875 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         * ia64.h (ia64_find_opcode): Remove argument name.
 878         (ia64_find_next_opcode): Likewise.
 879         (ia64_dis_opcode): Likewise.
 880         (ia64_free_opcode): Likewise.
 881         (ia64_find_dependency): Likewise.
 882
 883 2009-11-22  Doug Evans  <dje@sebabeach.org>
 884
 885         * cgen.h: Include bfd_stdint.h.
 886         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 887
 888 2009-11-18  Paul Brook  <paul@codesourcery.com>
 889
 890         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 891
 892 2009-11-17  Paul Brook  <paul@codesourcery.com>
 893         Daniel Jacobowitz  <dan@codesourcery.com>
 894
 895         * arm.h (ARM_EXT_V6_DSP): Define.
 896         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 897         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 898
 899 2009-11-04  DJ Delorie  <dj@redhat.com>
 900
 901         * rx.h (rx_decode_opcode) (mvtipl): Add.
 902         (mvtcp, mvfcp, opecp): Remove.
 903
 904 2009-11-02  Paul Brook  <paul@codesourcery.com>
 905
 906         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 907         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 908         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 909         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 910         FPU_ARCH_NEON_VFP_V4): Define.
 911
 912 2009-10-23  Doug Evans  <dje@sebabeach.org>
 913
 914         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 915         * cgen.h: Update.  Improve multi-inclusion macro name.
 916
 917 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 918
 919         * ppc.h (PPC_OPCODE_476): Define.
 920
 921 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 922
 923         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 924
 925 2009-09-29  DJ Delorie  <dj@redhat.com>
 926
 927         * rx.h: New file.
 928
 929 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 930
 931         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 932
 933 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 934
 935         * ppc.h (PPC_OPCODE_PPCA2): New.
 936
 937 2009-09-05  Martin Thuresson  <martin@mtme.org>
 938
 939         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 940
 941 2009-08-29  Martin Thuresson  <martin@mtme.org>
 942
 943         * tic30.h (template): Rename type template to
 944         insn_template. Updated code to use new name.
 945         * tic54x.h (template): Rename type template to
 946         insn_template.
 947
 948 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 949
 950         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 951
 952 2009-06-11  Anthony Green  <green@moxielogic.com>
 953
 954         * moxie.h (MOXIE_F3_PCREL): Define.
 955         (moxie_form3_opc_info): Grow.
 956
 957 2009-06-06  Anthony Green  <green@moxielogic.com>
 958
 959         * moxie.h (MOXIE_F1_M): Define.
 960
 961 2009-04-15  Anthony Green  <green@moxielogic.com>
 962
 963         * moxie.h: Created.
 964
 965 2009-04-06  DJ Delorie  <dj@redhat.com>
 966
 967         * h8300.h: Add relaxation attributes to MOVA opcodes.
 968
 969 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 970
 971         * ppc.h (ppc_parse_cpu): Declare.
 972
 973 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 974
 975         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 976         and _IMM11 for mbitclr and mbitset.
 977         * score-datadep.h: Update dependency information.
 978
 979 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 980
 981         * ppc.h (PPC_OPCODE_POWER7): New.
 982
 983 2009-02-06  Doug Evans  <dje@google.com>
 984
 985         * i386.h: Add comment regarding sse* insns and prefixes.
 986
 987 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 988
 989         * mips.h (INSN_XLR): Define.
 990         (INSN_CHIP_MASK): Update.
 991         (CPU_XLR): Define.
 992         (OPCODE_IS_MEMBER): Update.
 993         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 994
 995 2009-01-28  Doug Evans  <dje@google.com>
 996
 997         * opcode/i386.h: Add multiple inclusion protection.
 998         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 999         (EDI_REG_NUM): New macros.
1000         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1001         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1002         (REX_PREFIX_P): New macro.
1003
1004 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1005
1006         * ppc.h (struct powerpc_opcode): New field "deprecated".
1007         (PPC_OPCODE_NOPOWER4): Delete.
1008
1009 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1010
1011         * mips.h: Define CPU_R14000, CPU_R16000.
1012         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1013
1014 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1015
1016         * arm.h (FPU_NEON_FP16): New.
1017         (FPU_ARCH_NEON_FP16): New.
1018
1019 2008-11-06  Chao-ying Fu  <fu@mips.com>
1020
1021         * mips.h: Doucument '1' for 5-bit sync type.
1022
1023 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1026         IA64_RS_CR.
1027
1028 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1029
1030         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1031
1032 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1033
1034         * ppc.h (PPC_OPCODE_405): Define.
1035         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1036
1037 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1038
1039         * ppc.h (ppc_cpu_t): New typedef.
1040         (struct powerpc_opcode <flags>): Use it.
1041         (struct powerpc_operand <insert, extract>): Likewise.
1042         (struct powerpc_macro <flags>): Likewise.
1043
1044 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1045
1046         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1047         Update comment before MIPS16 field descriptors to mention MIPS16.
1048         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1049         BBIT.
1050         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1051         New bit masks and shift counts for cins and exts.
1052
1053         * mips.h: Document new field descriptors +Q.
1054         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1055
1056 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1057
1058         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1059         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1060
1061 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1062
1063         * ppc.h: (PPC_OPCODE_E500MC): New.
1064
1065 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1066
1067         * i386.h (MAX_OPERANDS): Set to 5.
1068         (MAX_MNEM_SIZE): Changed to 20.
1069
1070 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1071
1072         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1073
1074 2008-03-09  Paul Brook  <paul@codesourcery.com>
1075
1076         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1077
1078 2008-03-04  Paul Brook  <paul@codesourcery.com>
1079
1080         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1081         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1082         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1083
1084 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1085             Nick Clifton  <nickc@redhat.com>
1086
1087         PR 3134
1088         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1089         with a 32-bit displacement but without the top bit of the 4th byte
1090         set.
1091
1092 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1093
1094         * cr16.h (cr16_num_optab): Declared.
1095
1096 2008-02-14  Hakan Ardo  <hakan@debian.org>
1097
1098         PR gas/2626
1099         * avr.h (AVR_ISA_2xxe): Define.
1100
1101 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1102
1103         * mips.h: Update copyright.
1104         (INSN_CHIP_MASK): New macro.
1105         (INSN_OCTEON): New macro.
1106         (CPU_OCTEON): New macro.
1107         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1108
1109 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1110
1111         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1112
1113 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1114
1115         * avr.h (AVR_ISA_USB162): Add new opcode set.
1116         (AVR_ISA_AVR3): Likewise.
1117
1118 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1119
1120         * mips.h (INSN_LOONGSON_2E): New.
1121         (INSN_LOONGSON_2F): New.
1122         (CPU_LOONGSON_2E): New.
1123         (CPU_LOONGSON_2F): New.
1124         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1125
1126 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1127
1128         * mips.h (INSN_ISA*): Redefine certain values as an
1129         enumeration.  Update comments.
1130         (mips_isa_table): New.
1131         (ISA_MIPS*): Redefine to match enumeration.
1132         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1133         values.
1134
1135 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1136
1137         * ppc.h (PPC_OPCODE_PPCPS): New.
1138
1139 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1140
1141         * m68k.h: Document j K & E.
1142
1143 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1144
1145         * cr16.h: New file for CR16 target.
1146
1147 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1148
1149         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1150
1151 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1152
1153         * m68k.h (mcfisa_c): New.
1154         (mcfusp, mcf_mask): Adjust.
1155
1156 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1157
1158         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1159         (num_powerpc_operands): Declare.
1160         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1161         (PPC_OPERAND_PLUS1): Define.
1162
1163 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1164
1165         * i386.h (REX_MODE64): Renamed to ...
1166         (REX_W): This.
1167         (REX_EXTX): Renamed to ...
1168         (REX_R): This.
1169         (REX_EXTY): Renamed to ...
1170         (REX_X): This.
1171         (REX_EXTZ): Renamed to ...
1172         (REX_B): This.
1173
1174 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * i386.h: Add entries from config/tc-i386.h and move tables
1177         to opcodes/i386-opc.h.
1178
1179 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1180
1181         * i386.h (FloatDR): Removed.
1182         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1183
1184 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1185
1186         * spu-insns.h: Add soma double-float insns.
1187
1188 2007-02-20  Thiemo Seufer  <ths@mips.com>
1189             Chao-Ying Fu  <fu@mips.com>
1190
1191         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1192         (INSN_DSPR2): Add flag for DSP R2 instructions.
1193         (M_BALIGN): New macro.
1194
1195 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1196
1197         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1198         and Seg3ShortFrom with Shortform.
1199
1200 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1201
1202         PR gas/4027
1203         * i386.h (i386_optab): Put the real "test" before the pseudo
1204         one.
1205
1206 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1207
1208         * m68k.h (m68010up): OR fido_a.
1209
1210 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1211
1212         * m68k.h (fido_a): New.
1213
1214 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1215
1216         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1217         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1218         values.
1219
1220 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1221
1222         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1223
1224 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1225
1226         * score-inst.h (enum score_insn_type): Add Insn_internal.
1227
1228 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1229             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1230             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1231             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1232             Alan Modra  <amodra@bigpond.net.au>
1233
1234         * spu-insns.h: New file.
1235         * spu.h: New file.
1236
1237 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1238
1239         * ppc.h (PPC_OPCODE_CELL): Define.
1240
1241 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1242
1243         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1244         in amdfam10 architecture.
1245
1246 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1247
1248         * i386.h: Replace CpuMNI with CpuSSSE3.
1249
1250 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1251             Joseph Myers  <joseph@codesourcery.com>
1252             Ian Lance Taylor  <ian@wasabisystems.com>
1253             Ben Elliston  <bje@wasabisystems.com>
1254
1255         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1256
1257 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1258
1259         * score-datadep.h: New file.
1260         * score-inst.h: New file.
1261
1262 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1263
1264         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1265         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1266         movdq2q and movq2dq.
1267
1268 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1269            Michael Meissner             <michael.meissner@amd.com>
1270
1271         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1272
1273 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1274
1275         * i386.h (i386_optab): Add "nop" with memory reference.
1276
1277 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1278
1279         * i386.h (i386_optab): Update comment for 64bit NOP.
1280
1281 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1282             Anton Blanchard  <anton@samba.org>
1283
1284         * ppc.h (PPC_OPCODE_POWER6): Define.
1285         Adjust whitespace.
1286
1287 2006-06-05  Thiemo Seufer  <ths@mips.com>
1288
1289         * mips.h: Improve description of MT flags.
1290
1291 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1292
1293         * m68k.h (mcf_mask): Define.
1294
1295 2006-05-05  Thiemo Seufer  <ths@mips.com>
1296             David Ung  <davidu@mips.com>
1297
1298         * mips.h (enum): Add macro M_CACHE_AB.
1299
1300 2006-05-04  Thiemo Seufer  <ths@mips.com>
1301             Nigel Stephens  <nigel@mips.com>
1302             David Ung  <davidu@mips.com>
1303
1304         * mips.h: Add INSN_SMARTMIPS define.
1305
1306 2006-04-30  Thiemo Seufer  <ths@mips.com>
1307             David Ung  <davidu@mips.com>
1308
1309         * mips.h: Defines udi bits and masks.  Add description of
1310         characters which may appear in the args field of udi
1311         instructions.
1312
1313 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1314
1315         * mips.h: Improve comments describing the bitfield instruction
1316         fields.
1317
1318 2006-04-26  Julian Brown  <julian@codesourcery.com>
1319
1320         * arm.h (FPU_VFP_EXT_V3): Define constant.
1321         (FPU_NEON_EXT_V1): Likewise.
1322         (FPU_VFP_HARD): Update.
1323         (FPU_VFP_V3): Define macro.
1324         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1325
1326 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1327
1328         * avr.h (AVR_ISA_PWMx): New.
1329
1330 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1331
1332         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1333         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1334         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1335         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1336         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1337
1338 2006-03-10  Paul Brook  <paul@codesourcery.com>
1339
1340         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1341
1342 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1343
1344         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1345         first.  Correct mask of bb "B" opcode.
1346
1347 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1348
1349         * i386.h (i386_optab): Support Intel Merom New Instructions.
1350
1351 2006-02-24  Paul Brook  <paul@codesourcery.com>
1352
1353         * arm.h: Add V7 feature bits.
1354
1355 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1356
1357         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1358
1359 2006-01-31  Paul Brook  <paul@codesourcery.com>
1360         Richard Earnshaw <rearnsha@arm.com>
1361
1362         * arm.h: Use ARM_CPU_FEATURE.
1363         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1364         (arm_feature_set): Change to a structure.
1365         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1366         ARM_FEATURE): New macros.
1367
1368 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1369
1370         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1371         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1372         (ADD_PC_INCR_OPCODE): Don't define.
1373
1374 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1375
1376         PR gas/1874
1377         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1378
1379 2005-11-14  David Ung  <davidu@mips.com>
1380
1381         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1382         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1383         save/restore encoding of the args field.
1384
1385 2005-10-28  Dave Brolley  <brolley@redhat.com>
1386
1387         Contribute the following changes:
1388         2005-02-16  Dave Brolley  <brolley@redhat.com>
1389
1390         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1391         cgen_isa_mask_* to cgen_bitset_*.
1392         * cgen.h: Likewise.
1393
1394         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1395
1396         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1397         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1398         (CGEN_CPU_TABLE): Make isas a ponter.
1399
1400         2003-09-29  Dave Brolley  <brolley@redhat.com>
1401
1402         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1403         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1404         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1405
1406         2002-12-13  Dave Brolley  <brolley@redhat.com>
1407
1408         * cgen.h (symcat.h): #include it.
1409         (cgen-bitset.h): #include it.
1410         (CGEN_ATTR_VALUE_TYPE): Now a union.
1411         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1412         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1413         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1414         * cgen-bitset.h: New file.
1415
1416 2005-09-30  Catherine Moore  <clm@cm00re.com>
1417
1418         * bfin.h: New file.
1419
1420 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1421
1422         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1423         indirect operands.
1424
1425 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1426
1427         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1428         Add FLAG_STRICT to pa10 ftest opcode.
1429
1430 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1431
1432         * hppa.h (pa_opcodes): Remove lha entries.
1433
1434 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1435
1436         * hppa.h (FLAG_STRICT): Revise comment.
1437         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1438         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1439         entries for "fdc".
1440
1441 2005-09-30  Catherine Moore  <clm@cm00re.com>
1442
1443         * bfin.h: New file.
1444
1445 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1446
1447         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1448
1449 2005-09-06  Chao-ying Fu  <fu@mips.com>
1450
1451         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1452         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1453         define.
1454         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1455         (INSN_ASE_MASK): Update to include INSN_MT.
1456         (INSN_MT): New define for MT ASE.
1457
1458 2005-08-25  Chao-ying Fu  <fu@mips.com>
1459
1460         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1461         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1462         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1463         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1464         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1465         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1466         instructions.
1467         (INSN_DSP): New define for DSP ASE.
1468
1469 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1470
1471         * a29k.h: Delete.
1472
1473 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1474
1475         * ppc.h (PPC_OPCODE_E300): Define.
1476
1477 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1478
1479         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1480
1481 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1482
1483         PR gas/336
1484         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1485         and pitlb.
1486
1487 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1488
1489         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1490         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1491         Add movq-s as 64-bit variants of movd-s.
1492
1493 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1494
1495         * hppa.h: Fix punctuation in comment.
1496
1497         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1498         implicit space-register addressing.  Set space-register bits on opcodes
1499         using implicit space-register addressing.  Add various missing pa20
1500         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1501         space-register addressing.  Use "fE" instead of "fe" in various
1502         fstw opcodes.
1503
1504 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1505
1506         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1507
1508 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1509
1510         * i386.h (i386_optab): Support Intel VMX Instructions.
1511
1512 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1513
1514         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1515
1516 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1517
1518         * i386.h (i386_optab): Add new insns.
1519
1520 2005-07-01  Nick Clifton  <nickc@redhat.com>
1521
1522         * sparc.h: Add typedefs to structure declarations.
1523
1524 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1525
1526         PR 1013
1527         * i386.h (i386_optab): Update comments for 64bit addressing on
1528         mov. Allow 64bit addressing for mov and movq.
1529
1530 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1531
1532         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1533         respectively, in various floating-point load and store patterns.
1534
1535 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1536
1537         * hppa.h (FLAG_STRICT): Correct comment.
1538         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1539         PA 2.0 mneumonics when equivalent.  Entries with cache control
1540         completers now require PA 1.1.  Adjust whitespace.
1541
1542 2005-05-19  Anton Blanchard  <anton@samba.org>
1543
1544         * ppc.h (PPC_OPCODE_POWER5): Define.
1545
1546 2005-05-10  Nick Clifton  <nickc@redhat.com>
1547
1548         * Update the address and phone number of the FSF organization in
1549         the GPL notices in the following files:
1550         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1551         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1552         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1553         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1554         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1555         tic54x.h, tic80.h, v850.h, vax.h
1556
1557 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1558
1559         * i386.h (i386_optab): Add ht and hnt.
1560
1561 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1562
1563         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1564         Add xcrypt-ctr.  Provide aliases without hyphens.
1565
1566 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1567
1568         Moved from ../ChangeLog
1569
1570         2005-04-12  Paul Brook  <paul@codesourcery.com>
1571         * m88k.h: Rename psr macros to avoid conflicts.
1572
1573         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1574         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1575         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1576         and ARM_ARCH_V6ZKT2.
1577
1578         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1579         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1580         Remove redundant instruction types.
1581         (struct argument): X_op - new field.
1582         (struct cst4_entry): Remove.
1583         (no_op_insn): Declare.
1584
1585         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1586         * crx.h (enum argtype): Rename types, remove unused types.
1587
1588         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1589         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1590         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1591         (enum operand_type): Rearrange operands, edit comments.
1592         replace us<N> with ui<N> for unsigned immediate.
1593         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1594         displacements (respectively).
1595         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1596         (instruction type): Add NO_TYPE_INS.
1597         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1598         (operand_entry): New field - 'flags'.
1599         (operand flags): New.
1600
1601         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1602         * crx.h (operand_type): Remove redundant types i3, i4,
1603         i5, i8, i12.
1604         Add new unsigned immediate types us3, us4, us5, us16.
1605
1606 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1607
1608         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1609         adjust them accordingly.
1610
1611 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1612
1613         * i386.h (i386_optab): Add rdtscp.
1614
1615 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1616
1617         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1618         between memory and segment register. Allow movq for moving between
1619         general-purpose register and segment register.
1620
1621 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1622
1623         PR gas/707
1624         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1625         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1626         fnstsw.
1627
1628 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1629
1630         * m68k.h (m68008, m68ec030, m68882): Remove.
1631         (m68k_mask): New.
1632         (cpu_m68k, cpu_cf): New.
1633         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1634         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1635
1636 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1637
1638         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1639         * cgen.h (enum cgen_parse_operand_type): Add
1640         CGEN_PARSE_OPERAND_SYMBOLIC.
1641
1642 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1643
1644         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1645         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1646         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1647
1648 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1649
1650         * mips.h (struct mips_opcode): Add new pinfo2 member.
1651         (INSN_ALIAS): New define for opcode table entries that are
1652         specific instances of another entry, such as 'move' for an 'or'
1653         with a zero operand.
1654         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1655         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1656
1657 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1658
1659         * mips.h (CPU_RM9000): Define.
1660         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1661
1662 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1663
1664         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1665         to/from test registers are illegal in 64-bit mode. Add missing
1666         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1667         (previously one had to explicitly encode a rex64 prefix). Re-enable
1668         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1669         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1670
1671 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1672
1673         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1674         available only with SSE2. Change the MMX additions introduced by SSE
1675         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1676         instructions by their now designated identifier (since combining i686
1677         and 3DNow! does not really imply 3DNow!A).
1678
1679 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1680
1681         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1682         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1683
1684 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1685             Vineet Sharma      <vineets@noida.hcltech.com>
1686
1687         * maxq.h: New file: Disassembly information for the maxq port.
1688
1689 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1690
1691         * i386.h (i386_optab): Put back "movzb".
1692
1693 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1694
1695         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1696         comments.  Remove member cris_ver_sim.  Add members
1697         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1698         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1699         (struct cris_support_reg, struct cris_cond15): New types.
1700         (cris_conds15): Declare.
1701         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1702         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1703         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1704         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1705         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1706         SIZE_FIELD_UNSIGNED.
1707
1708 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1709
1710         * i386.h (sldx_Suf): Remove.
1711         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1712         (q_FP): Define, implying no REX64.
1713         (x_FP, sl_FP): Imply FloatMF.
1714         (i386_optab): Split reg and mem forms of moving from segment registers
1715         so that the memory forms can ignore the 16-/32-bit operand size
1716         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1717         all non-floating-point instructions. Unite 32- and 64-bit forms of
1718         movsx, movzx, and movd. Adjust floating point operations for the above
1719         changes to the *FP macros. Add DefaultSize to floating point control
1720         insns operating on larger memory ranges. Remove left over comments
1721         hinting at certain insns being Intel-syntax ones where the ones
1722         actually meant are already gone.
1723
1724 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1725
1726         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1727         instruction type.
1728
1729 2004-09-30  Paul Brook  <paul@codesourcery.com>
1730
1731         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1732         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1733
1734 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1735
1736         * avr.h: Add support for
1737         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1738
1739 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1740
1741         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1742
1743 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1744
1745         * msp430.h (msp430_opc): Add new instructions.
1746         (msp430_rcodes): Declare new instructions.
1747         (msp430_hcodes): Likewise..
1748
1749 2004-08-13  Nick Clifton  <nickc@redhat.com>
1750
1751         PR/301
1752         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1753         processors.
1754
1755 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1756
1757         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1758
1759 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1760
1761         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1762
1763 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1764
1765         * i386.h: Adjust instruction descriptions to better match the
1766         specification.
1767
1768 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1769
1770         * arm.h: Remove all old content.  Replace with architecture defines
1771         from gas/config/tc-arm.c.
1772
1773 2004-07-09  Andreas Schwab  <schwab@suse.de>
1774
1775         * m68k.h: Fix comment.
1776
1777 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1778
1779         * crx.h: New file.
1780
1781 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1782
1783         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1784
1785 2004-05-24  Peter Barada  <peter@the-baradas.com>
1786
1787         * m68k.h: Add 'size' to m68k_opcode.
1788
1789 2004-05-05  Peter Barada  <peter@the-baradas.com>
1790
1791         * m68k.h: Switch from ColdFire chip name to core variant.
1792
1793 2004-04-22  Peter Barada  <peter@the-baradas.com>
1794
1795         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1796         descriptions for new EMAC cases.
1797         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1798         handle Motorola MAC syntax.
1799         Allow disassembly of ColdFire V4e object files.
1800
1801 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1802
1803         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1804
1805 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1806
1807         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1808
1809 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1810
1811         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1812
1813 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1814
1815         * i386.h (i386_optab): Added xstore/xcrypt insns.
1816
1817 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1818
1819         * h8300.h (32bit ldc/stc): Add relaxing support.
1820
1821 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1822
1823         * h8300.h (BITOP): Pass MEMRELAX flag.
1824
1825 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1826
1827         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1828         except for the H8S.
1829
1830 For older changes see ChangeLog-9103
1831 \f
1832 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1833
1834 Copying and distribution of this file, with or without modification,
1835 are permitted in any medium without royalty provided the copyright
1836 notice and this notice are preserved.
1837
1838 Local Variables:
1839 mode: change-log
1840 left-margin: 8
1841 fill-column: 74
1842 version-control: never
1843 End: