include/opcode/ChangeLog

   1 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
   2
   3         * spu-insns.h: Add soma double-float insns.
   4
   5 2007-02-20  Thiemo Seufer  <ths@mips.com>
   6             Chao-Ying Fu  <fu@mips.com>
   7
   8         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
   9         (INSN_DSPR2): Add flag for DSP R2 instructions.
  10         (M_BALIGN): New macro.
  11
  12 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  13
  14         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  15         and Seg3ShortFrom with Shortform.
  16
  17 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         PR gas/4027
  20         * i386.h (i386_optab): Put the real "test" before the pseudo
  21         one.
  22
  23 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  24
  25         * m68k.h (m68010up): OR fido_a.
  26
  27 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  28
  29         * m68k.h (fido_a): New.
  30
  31 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  32
  33         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  34         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  35         values.
  36
  37 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  40
  41 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  42
  43         * score-inst.h (enum score_insn_type): Add Insn_internal.
  44
  45 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  46             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  47             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  48             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  49             Alan Modra  <amodra@bigpond.net.au>
  50
  51         * spu-insns.h: New file.
  52         * spu.h: New file.
  53
  54 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  55
  56         * ppc.h (PPC_OPCODE_CELL): Define.
  57
  58 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  59
  60         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  61         in amdfam10 architecture.
  62
  63 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386.h: Replace CpuMNI with CpuSSSE3.
  66
  67 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  68             Joseph Myers  <joseph@codesourcery.com>
  69             Ian Lance Taylor  <ian@wasabisystems.com>
  70             Ben Elliston  <bje@wasabisystems.com>
  71
  72         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  73
  74 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  75
  76         * score-datadep.h: New file.
  77         * score-inst.h: New file.
  78
  79 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  82         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  83         movdq2q and movq2dq.
  84
  85 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  86            Michael Meissner             <michael.meissner@amd.com>
  87
  88         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  89
  90 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         * i386.h (i386_optab): Add "nop" with memory reference.
  93
  94 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         * i386.h (i386_optab): Update comment for 64bit NOP.
  97
  98 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  99             Anton Blanchard  <anton@samba.org>
 100
 101         * ppc.h (PPC_OPCODE_POWER6): Define.
 102         Adjust whitespace.
 103
 104 2006-06-05  Thiemo Seufer  <ths@mips.com>
 105
 106         * mips.h: Improve description of MT flags.
 107
 108 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 109
 110         * m68k.h (mcf_mask): Define.
 111
 112 2006-05-05  Thiemo Seufer  <ths@mips.com>
 113             David Ung  <davidu@mips.com>
 114
 115         * mips.h (enum): Add macro M_CACHE_AB.
 116
 117 2006-05-04  Thiemo Seufer  <ths@mips.com>
 118             Nigel Stephens  <nigel@mips.com>
 119             David Ung  <davidu@mips.com>
 120
 121         * mips.h: Add INSN_SMARTMIPS define.
 122
 123 2006-04-30  Thiemo Seufer  <ths@mips.com>
 124             David Ung  <davidu@mips.com>
 125
 126         * mips.h: Defines udi bits and masks.  Add description of
 127         characters which may appear in the args field of udi
 128         instructions.
 129
 130 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 131
 132         * mips.h: Improve comments describing the bitfield instruction
 133         fields.
 134
 135 2006-04-26  Julian Brown  <julian@codesourcery.com>
 136
 137         * arm.h (FPU_VFP_EXT_V3): Define constant.
 138         (FPU_NEON_EXT_V1): Likewise.
 139         (FPU_VFP_HARD): Update.
 140         (FPU_VFP_V3): Define macro.
 141         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 142
 143 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 144
 145         * avr.h (AVR_ISA_PWMx): New.
 146
 147 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 148
 149         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 150         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 151         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 152         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 153         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 154
 155 2006-03-10  Paul Brook  <paul@codesourcery.com>
 156
 157         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 158
 159 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 160
 161         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 162         first.  Correct mask of bb "B" opcode.
 163
 164 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 165
 166         * i386.h (i386_optab): Support Intel Merom New Instructions.
 167
 168 2006-02-24  Paul Brook  <paul@codesourcery.com>
 169
 170         * arm.h: Add V7 feature bits.
 171
 172 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 173
 174         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 175
 176 2006-01-31  Paul Brook  <paul@codesourcery.com>
 177         Richard Earnshaw <rearnsha@arm.com>
 178
 179         * arm.h: Use ARM_CPU_FEATURE.
 180         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 181         (arm_feature_set): Change to a structure.
 182         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 183         ARM_FEATURE): New macros.
 184
 185 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 186
 187         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 188         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 189         (ADD_PC_INCR_OPCODE): Don't define.
 190
 191 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         PR gas/1874
 194         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 195
 196 2005-11-14  David Ung  <davidu@mips.com>
 197
 198         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 199         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 200         save/restore encoding of the args field.
 201
 202 2005-10-28  Dave Brolley  <brolley@redhat.com>
 203
 204         Contribute the following changes:
 205         2005-02-16  Dave Brolley  <brolley@redhat.com>
 206
 207         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 208         cgen_isa_mask_* to cgen_bitset_*.
 209         * cgen.h: Likewise.
 210
 211         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 212
 213         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 214         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 215         (CGEN_CPU_TABLE): Make isas a ponter.
 216
 217         2003-09-29  Dave Brolley  <brolley@redhat.com>
 218
 219         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 220         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 221         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 222
 223         2002-12-13  Dave Brolley  <brolley@redhat.com>
 224
 225         * cgen.h (symcat.h): #include it.
 226         (cgen-bitset.h): #include it.
 227         (CGEN_ATTR_VALUE_TYPE): Now a union.
 228         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 229         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 230         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 231         * cgen-bitset.h: New file.
 232
 233 2005-09-30  Catherine Moore  <clm@cm00re.com>
 234
 235         * bfin.h: New file.
 236
 237 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 238
 239         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 240         indirect operands.
 241
 242 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 243
 244         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 245         Add FLAG_STRICT to pa10 ftest opcode.
 246
 247 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 248
 249         * hppa.h (pa_opcodes): Remove lha entries.
 250
 251 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 252
 253         * hppa.h (FLAG_STRICT): Revise comment.
 254         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 255         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 256         entries for "fdc".
 257
 258 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 259
 260         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 261
 262 2005-09-06  Chao-ying Fu  <fu@mips.com>
 263
 264         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 265         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 266         define.
 267         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 268         (INSN_ASE_MASK): Update to include INSN_MT.
 269         (INSN_MT): New define for MT ASE.
 270
 271 2005-08-25  Chao-ying Fu  <fu@mips.com>
 272
 273         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 274         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 275         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 276         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 277         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 278         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 279         instructions.
 280         (INSN_DSP): New define for DSP ASE.
 281
 282 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 283
 284         * a29k.h: Delete.
 285
 286 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 287
 288         * ppc.h (PPC_OPCODE_E300): Define.
 289
 290 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 291
 292         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 293
 294 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 295
 296         PR gas/336
 297         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 298         and pitlb.
 299
 300 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 301
 302         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 303         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 304         Add movq-s as 64-bit variants of movd-s.
 305
 306 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 307
 308         * hppa.h: Fix punctuation in comment.
 309
 310         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 311         implicit space-register addressing.  Set space-register bits on opcodes
 312         using implicit space-register addressing.  Add various missing pa20
 313         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 314         space-register addressing.  Use "fE" instead of "fe" in various
 315         fstw opcodes.
 316
 317 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 318
 319         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 320
 321 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 322
 323         * i386.h (i386_optab): Support Intel VMX Instructions.
 324
 325 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 326
 327         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 328
 329 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 330
 331         * i386.h (i386_optab): Add new insns.
 332
 333 2005-07-01  Nick Clifton  <nickc@redhat.com>
 334
 335         * sparc.h: Add typedefs to structure declarations.
 336
 337 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR 1013
 340         * i386.h (i386_optab): Update comments for 64bit addressing on
 341         mov. Allow 64bit addressing for mov and movq.
 342
 343 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 344
 345         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 346         respectively, in various floating-point load and store patterns.
 347
 348 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 349
 350         * hppa.h (FLAG_STRICT): Correct comment.
 351         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 352         PA 2.0 mneumonics when equivalent.  Entries with cache control
 353         completers now require PA 1.1.  Adjust whitespace.
 354
 355 2005-05-19  Anton Blanchard  <anton@samba.org>
 356
 357         * ppc.h (PPC_OPCODE_POWER5): Define.
 358
 359 2005-05-10  Nick Clifton  <nickc@redhat.com>
 360
 361         * Update the address and phone number of the FSF organization in
 362         the GPL notices in the following files:
 363         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 364         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 365         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 366         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 367         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 368         tic54x.h, tic80.h, v850.h, vax.h
 369
 370 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 371
 372         * i386.h (i386_optab): Add ht and hnt.
 373
 374 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 375
 376         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 377         Add xcrypt-ctr.  Provide aliases without hyphens.
 378
 379 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 380
 381         Moved from ../ChangeLog
 382
 383         2005-04-12  Paul Brook  <paul@codesourcery.com>
 384         * m88k.h: Rename psr macros to avoid conflicts.
 385
 386         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 387         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 388         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 389         and ARM_ARCH_V6ZKT2.
 390
 391         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 392         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 393         Remove redundant instruction types.
 394         (struct argument): X_op - new field.
 395         (struct cst4_entry): Remove.
 396         (no_op_insn): Declare.
 397
 398         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 399         * crx.h (enum argtype): Rename types, remove unused types.
 400
 401         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 402         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 403         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 404         (enum operand_type): Rearrange operands, edit comments.
 405         replace us<N> with ui<N> for unsigned immediate.
 406         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 407         displacements (respectively).
 408         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 409         (instruction type): Add NO_TYPE_INS.
 410         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 411         (operand_entry): New field - 'flags'.
 412         (operand flags): New.
 413
 414         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 415         * crx.h (operand_type): Remove redundant types i3, i4,
 416         i5, i8, i12.
 417         Add new unsigned immediate types us3, us4, us5, us16.
 418
 419 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 420
 421         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 422         adjust them accordingly.
 423
 424 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 425
 426         * i386.h (i386_optab): Add rdtscp.
 427
 428 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 429
 430         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 431         between memory and segment register. Allow movq for moving between
 432         general-purpose register and segment register.
 433
 434 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 435
 436         PR gas/707
 437         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 438         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 439         fnstsw.
 440
 441 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 442
 443         * m68k.h (m68008, m68ec030, m68882): Remove.
 444         (m68k_mask): New.
 445         (cpu_m68k, cpu_cf): New.
 446         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 447         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 448
 449 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 450
 451         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 452         * cgen.h (enum cgen_parse_operand_type): Add
 453         CGEN_PARSE_OPERAND_SYMBOLIC.
 454
 455 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 456
 457         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 458         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 459         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 460
 461 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 462
 463         * mips.h (struct mips_opcode): Add new pinfo2 member.
 464         (INSN_ALIAS): New define for opcode table entries that are
 465         specific instances of another entry, such as 'move' for an 'or'
 466         with a zero operand.
 467         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 468         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 469
 470 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 471
 472         * mips.h (CPU_RM9000): Define.
 473         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 474
 475 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 476
 477         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 478         to/from test registers are illegal in 64-bit mode. Add missing
 479         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 480         (previously one had to explicitly encode a rex64 prefix). Re-enable
 481         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 482         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 483
 484 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 485
 486         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 487         available only with SSE2. Change the MMX additions introduced by SSE
 488         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 489         instructions by their now designated identifier (since combining i686
 490         and 3DNow! does not really imply 3DNow!A).
 491
 492 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 493
 494         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 495         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 496
 497 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 498             Vineet Sharma      <vineets@noida.hcltech.com>
 499
 500         * maxq.h: New file: Disassembly information for the maxq port.
 501
 502 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 503
 504         * i386.h (i386_optab): Put back "movzb".
 505
 506 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 507
 508         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 509         comments.  Remove member cris_ver_sim.  Add members
 510         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 511         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 512         (struct cris_support_reg, struct cris_cond15): New types.
 513         (cris_conds15): Declare.
 514         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 515         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 516         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 517         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 518         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 519         SIZE_FIELD_UNSIGNED.
 520
 521 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 522
 523         * i386.h (sldx_Suf): Remove.
 524         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 525         (q_FP): Define, implying no REX64.
 526         (x_FP, sl_FP): Imply FloatMF.
 527         (i386_optab): Split reg and mem forms of moving from segment registers
 528         so that the memory forms can ignore the 16-/32-bit operand size
 529         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 530         all non-floating-point instructions. Unite 32- and 64-bit forms of
 531         movsx, movzx, and movd. Adjust floating point operations for the above
 532         changes to the *FP macros. Add DefaultSize to floating point control
 533         insns operating on larger memory ranges. Remove left over comments
 534         hinting at certain insns being Intel-syntax ones where the ones
 535         actually meant are already gone.
 536
 537 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 538
 539         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 540         instruction type.
 541
 542 2004-09-30  Paul Brook  <paul@codesourcery.com>
 543
 544         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 545         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 546
 547 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 548
 549         * avr.h: Add support for
 550         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 551
 552 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 553
 554         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 555
 556 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 557
 558         * msp430.h (msp430_opc): Add new instructions.
 559         (msp430_rcodes): Declare new instructions.
 560         (msp430_hcodes): Likewise..
 561
 562 2004-08-13  Nick Clifton  <nickc@redhat.com>
 563
 564         PR/301
 565         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 566         processors.
 567
 568 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 569
 570         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 571
 572 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 575
 576 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 577
 578         * i386.h: Adjust instruction descriptions to better match the
 579         specification.
 580
 581 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 582
 583         * arm.h: Remove all old content.  Replace with architecture defines
 584         from gas/config/tc-arm.c.
 585
 586 2004-07-09  Andreas Schwab  <schwab@suse.de>
 587
 588         * m68k.h: Fix comment.
 589
 590 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 591
 592         * crx.h: New file.
 593
 594 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 595
 596         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 597
 598 2004-05-24  Peter Barada  <peter@the-baradas.com>
 599
 600         * m68k.h: Add 'size' to m68k_opcode.
 601
 602 2004-05-05  Peter Barada  <peter@the-baradas.com>
 603
 604         * m68k.h: Switch from ColdFire chip name to core variant.
 605
 606 2004-04-22  Peter Barada  <peter@the-baradas.com>
 607
 608         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 609         descriptions for new EMAC cases.
 610         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 611         handle Motorola MAC syntax.
 612         Allow disassembly of ColdFire V4e object files.
 613
 614 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 615
 616         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 617
 618 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 619
 620         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 621
 622 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 623
 624         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 625
 626 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 627
 628         * i386.h (i386_optab): Added xstore/xcrypt insns.
 629
 630 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 631
 632         * h8300.h (32bit ldc/stc): Add relaxing support.
 633
 634 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 635
 636         * h8300.h (BITOP): Pass MEMRELAX flag.
 637
 638 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 639
 640         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 641         except for the H8S.
 642
 643 For older changes see ChangeLog-9103
 644 \f
 645 Local Variables:
 646 mode: change-log
 647 left-margin: 8
 648 fill-column: 74
 649 version-control: never
 650 End: