1 2009-01-28 Doug Evans <dje@google.com>
3 * opcode/i386.h: Add multiple inclusion protection.
4 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
5 (EDI_REG_NUM): New macros.
6 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
7 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
8 (REG_PREFIX_P): New macro.
10 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
12 * ppc.h (struct powerpc_opcode): New field "deprecated".
13 (PPC_OPCODE_NOPOWER4): Delete.
15 2008-11-28 Joshua Kinard <kumba@gentoo.org>
17 * mips.h: Define CPU_R14000, CPU_R16000.
18 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
20 2008-11-18 Catherine Moore <clm@codesourcery.com>
22 * arm.h (FPU_NEON_FP16): New.
23 (FPU_ARCH_NEON_FP16): New.
25 2008-11-06 Chao-ying Fu <fu@mips.com>
27 * mips.h: Doucument '1' for 5-bit sync type.
29 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
31 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
34 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
36 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
38 2008-07-30 Michael J. Eager <eager@eagercon.com>
40 * ppc.h (PPC_OPCODE_405): Define.
41 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
43 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
45 * ppc.h (ppc_cpu_t): New typedef.
46 (struct powerpc_opcode <flags>): Use it.
47 (struct powerpc_operand <insert, extract>): Likewise.
48 (struct powerpc_macro <flags>): Likewise.
50 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
52 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
53 Update comment before MIPS16 field descriptors to mention MIPS16.
54 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
56 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
57 New bit masks and shift counts for cins and exts.
59 * mips.h: Document new field descriptors +Q.
60 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
62 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
64 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
65 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
67 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
69 * ppc.h: (PPC_OPCODE_E500MC): New.
71 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
73 * i386.h (MAX_OPERANDS): Set to 5.
74 (MAX_MNEM_SIZE): Changed to 20.
76 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
78 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
80 2008-03-09 Paul Brook <paul@codesourcery.com>
82 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
84 2008-03-04 Paul Brook <paul@codesourcery.com>
86 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
87 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
88 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
90 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
91 Nick Clifton <nickc@redhat.com>
94 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
95 with a 32-bit displacement but without the top bit of the 4th byte
98 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
100 * cr16.h (cr16_num_optab): Declared.
102 2008-02-14 Hakan Ardo <hakan@debian.org>
105 * avr.h (AVR_ISA_2xxe): Define.
107 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
109 * mips.h: Update copyright.
110 (INSN_CHIP_MASK): New macro.
111 (INSN_OCTEON): New macro.
112 (CPU_OCTEON): New macro.
113 (OPCODE_IS_MEMBER): Handle Octeon instructions.
115 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
117 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
119 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
121 * avr.h (AVR_ISA_USB162): Add new opcode set.
122 (AVR_ISA_AVR3): Likewise.
124 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
126 * mips.h (INSN_LOONGSON_2E): New.
127 (INSN_LOONGSON_2F): New.
128 (CPU_LOONGSON_2E): New.
129 (CPU_LOONGSON_2F): New.
130 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
132 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
134 * mips.h (INSN_ISA*): Redefine certain values as an
135 enumeration. Update comments.
136 (mips_isa_table): New.
137 (ISA_MIPS*): Redefine to match enumeration.
138 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
141 2007-08-08 Ben Elliston <bje@au.ibm.com>
143 * ppc.h (PPC_OPCODE_PPCPS): New.
145 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
147 * m68k.h: Document j K & E.
149 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
151 * cr16.h: New file for CR16 target.
153 2007-05-02 Alan Modra <amodra@bigpond.net.au>
155 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
157 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
159 * m68k.h (mcfisa_c): New.
160 (mcfusp, mcf_mask): Adjust.
162 2007-04-20 Alan Modra <amodra@bigpond.net.au>
164 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
165 (num_powerpc_operands): Declare.
166 (PPC_OPERAND_SIGNED et al): Redefine as hex.
167 (PPC_OPERAND_PLUS1): Define.
169 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
171 * i386.h (REX_MODE64): Renamed to ...
173 (REX_EXTX): Renamed to ...
175 (REX_EXTY): Renamed to ...
177 (REX_EXTZ): Renamed to ...
180 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
182 * i386.h: Add entries from config/tc-i386.h and move tables
183 to opcodes/i386-opc.h.
185 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
187 * i386.h (FloatDR): Removed.
188 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
190 2007-03-01 Alan Modra <amodra@bigpond.net.au>
192 * spu-insns.h: Add soma double-float insns.
194 2007-02-20 Thiemo Seufer <ths@mips.com>
195 Chao-Ying Fu <fu@mips.com>
197 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
198 (INSN_DSPR2): Add flag for DSP R2 instructions.
199 (M_BALIGN): New macro.
201 2007-02-14 Alan Modra <amodra@bigpond.net.au>
203 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
204 and Seg3ShortFrom with Shortform.
206 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
209 * i386.h (i386_optab): Put the real "test" before the pseudo
212 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
214 * m68k.h (m68010up): OR fido_a.
216 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
218 * m68k.h (fido_a): New.
220 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
222 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
223 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
226 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
228 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
230 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
232 * score-inst.h (enum score_insn_type): Add Insn_internal.
234 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
235 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
236 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
237 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
238 Alan Modra <amodra@bigpond.net.au>
240 * spu-insns.h: New file.
243 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
245 * ppc.h (PPC_OPCODE_CELL): Define.
247 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
249 * i386.h : Modify opcode to support for the change in POPCNT opcode
250 in amdfam10 architecture.
252 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
254 * i386.h: Replace CpuMNI with CpuSSSE3.
256 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
257 Joseph Myers <joseph@codesourcery.com>
258 Ian Lance Taylor <ian@wasabisystems.com>
259 Ben Elliston <bje@wasabisystems.com>
261 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
263 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
265 * score-datadep.h: New file.
266 * score-inst.h: New file.
268 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
270 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
271 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
274 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
275 Michael Meissner <michael.meissner@amd.com>
277 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
279 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
281 * i386.h (i386_optab): Add "nop" with memory reference.
283 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
285 * i386.h (i386_optab): Update comment for 64bit NOP.
287 2006-06-06 Ben Elliston <bje@au.ibm.com>
288 Anton Blanchard <anton@samba.org>
290 * ppc.h (PPC_OPCODE_POWER6): Define.
293 2006-06-05 Thiemo Seufer <ths@mips.com>
295 * mips.h: Improve description of MT flags.
297 2006-05-25 Richard Sandiford <richard@codesourcery.com>
299 * m68k.h (mcf_mask): Define.
301 2006-05-05 Thiemo Seufer <ths@mips.com>
302 David Ung <davidu@mips.com>
304 * mips.h (enum): Add macro M_CACHE_AB.
306 2006-05-04 Thiemo Seufer <ths@mips.com>
307 Nigel Stephens <nigel@mips.com>
308 David Ung <davidu@mips.com>
310 * mips.h: Add INSN_SMARTMIPS define.
312 2006-04-30 Thiemo Seufer <ths@mips.com>
313 David Ung <davidu@mips.com>
315 * mips.h: Defines udi bits and masks. Add description of
316 characters which may appear in the args field of udi
319 2006-04-26 Thiemo Seufer <ths@networkno.de>
321 * mips.h: Improve comments describing the bitfield instruction
324 2006-04-26 Julian Brown <julian@codesourcery.com>
326 * arm.h (FPU_VFP_EXT_V3): Define constant.
327 (FPU_NEON_EXT_V1): Likewise.
328 (FPU_VFP_HARD): Update.
329 (FPU_VFP_V3): Define macro.
330 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
332 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
334 * avr.h (AVR_ISA_PWMx): New.
336 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
338 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
339 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
340 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
341 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
342 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
344 2006-03-10 Paul Brook <paul@codesourcery.com>
346 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
348 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
350 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
351 first. Correct mask of bb "B" opcode.
353 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
355 * i386.h (i386_optab): Support Intel Merom New Instructions.
357 2006-02-24 Paul Brook <paul@codesourcery.com>
359 * arm.h: Add V7 feature bits.
361 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
363 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
365 2006-01-31 Paul Brook <paul@codesourcery.com>
366 Richard Earnshaw <rearnsha@arm.com>
368 * arm.h: Use ARM_CPU_FEATURE.
369 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
370 (arm_feature_set): Change to a structure.
371 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
372 ARM_FEATURE): New macros.
374 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
376 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
377 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
378 (ADD_PC_INCR_OPCODE): Don't define.
380 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
383 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
385 2005-11-14 David Ung <davidu@mips.com>
387 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
388 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
389 save/restore encoding of the args field.
391 2005-10-28 Dave Brolley <brolley@redhat.com>
393 Contribute the following changes:
394 2005-02-16 Dave Brolley <brolley@redhat.com>
396 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
397 cgen_isa_mask_* to cgen_bitset_*.
400 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
402 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
403 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
404 (CGEN_CPU_TABLE): Make isas a ponter.
406 2003-09-29 Dave Brolley <brolley@redhat.com>
408 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
409 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
410 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
412 2002-12-13 Dave Brolley <brolley@redhat.com>
414 * cgen.h (symcat.h): #include it.
415 (cgen-bitset.h): #include it.
416 (CGEN_ATTR_VALUE_TYPE): Now a union.
417 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
418 (CGEN_ATTR_ENTRY): 'value' now unsigned.
419 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
420 * cgen-bitset.h: New file.
422 2005-09-30 Catherine Moore <clm@cm00re.com>
426 2005-10-24 Jan Beulich <jbeulich@novell.com>
428 * ia64.h (enum ia64_opnd): Move memory operand out of set of
431 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
433 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
434 Add FLAG_STRICT to pa10 ftest opcode.
436 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
438 * hppa.h (pa_opcodes): Remove lha entries.
440 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
442 * hppa.h (FLAG_STRICT): Revise comment.
443 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
444 before corresponding pa11 opcodes. Add strict pa10 register-immediate
447 2005-09-30 Catherine Moore <clm@cm00re.com>
451 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
453 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
455 2005-09-06 Chao-ying Fu <fu@mips.com>
457 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
458 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
460 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
461 (INSN_ASE_MASK): Update to include INSN_MT.
462 (INSN_MT): New define for MT ASE.
464 2005-08-25 Chao-ying Fu <fu@mips.com>
466 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
467 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
468 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
469 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
470 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
471 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
473 (INSN_DSP): New define for DSP ASE.
475 2005-08-18 Alan Modra <amodra@bigpond.net.au>
479 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
481 * ppc.h (PPC_OPCODE_E300): Define.
483 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
485 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
487 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
490 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
493 2005-07-27 Jan Beulich <jbeulich@novell.com>
495 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
496 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
497 Add movq-s as 64-bit variants of movd-s.
499 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
501 * hppa.h: Fix punctuation in comment.
503 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
504 implicit space-register addressing. Set space-register bits on opcodes
505 using implicit space-register addressing. Add various missing pa20
506 long-immediate opcodes. Remove various opcodes using implicit 3-bit
507 space-register addressing. Use "fE" instead of "fe" in various
510 2005-07-18 Jan Beulich <jbeulich@novell.com>
512 * i386.h (i386_optab): Operands of aam and aad are unsigned.
514 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
516 * i386.h (i386_optab): Support Intel VMX Instructions.
518 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
520 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
522 2005-07-05 Jan Beulich <jbeulich@novell.com>
524 * i386.h (i386_optab): Add new insns.
526 2005-07-01 Nick Clifton <nickc@redhat.com>
528 * sparc.h: Add typedefs to structure declarations.
530 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
533 * i386.h (i386_optab): Update comments for 64bit addressing on
534 mov. Allow 64bit addressing for mov and movq.
536 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
538 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
539 respectively, in various floating-point load and store patterns.
541 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
543 * hppa.h (FLAG_STRICT): Correct comment.
544 (pa_opcodes): Update load and store entries to allow both PA 1.X and
545 PA 2.0 mneumonics when equivalent. Entries with cache control
546 completers now require PA 1.1. Adjust whitespace.
548 2005-05-19 Anton Blanchard <anton@samba.org>
550 * ppc.h (PPC_OPCODE_POWER5): Define.
552 2005-05-10 Nick Clifton <nickc@redhat.com>
554 * Update the address and phone number of the FSF organization in
555 the GPL notices in the following files:
556 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
557 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
558 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
559 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
560 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
561 tic54x.h, tic80.h, v850.h, vax.h
563 2005-05-09 Jan Beulich <jbeulich@novell.com>
565 * i386.h (i386_optab): Add ht and hnt.
567 2005-04-18 Mark Kettenis <kettenis@gnu.org>
569 * i386.h: Insert hyphens into selected VIA PadLock extensions.
570 Add xcrypt-ctr. Provide aliases without hyphens.
572 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
574 Moved from ../ChangeLog
576 2005-04-12 Paul Brook <paul@codesourcery.com>
577 * m88k.h: Rename psr macros to avoid conflicts.
579 2005-03-12 Zack Weinberg <zack@codesourcery.com>
580 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
581 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
584 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
585 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
586 Remove redundant instruction types.
587 (struct argument): X_op - new field.
588 (struct cst4_entry): Remove.
589 (no_op_insn): Declare.
591 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
592 * crx.h (enum argtype): Rename types, remove unused types.
594 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
595 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
596 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
597 (enum operand_type): Rearrange operands, edit comments.
598 replace us<N> with ui<N> for unsigned immediate.
599 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
600 displacements (respectively).
601 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
602 (instruction type): Add NO_TYPE_INS.
603 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
604 (operand_entry): New field - 'flags'.
605 (operand flags): New.
607 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
608 * crx.h (operand_type): Remove redundant types i3, i4,
610 Add new unsigned immediate types us3, us4, us5, us16.
612 2005-04-12 Mark Kettenis <kettenis@gnu.org>
614 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
615 adjust them accordingly.
617 2005-04-01 Jan Beulich <jbeulich@novell.com>
619 * i386.h (i386_optab): Add rdtscp.
621 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
623 * i386.h (i386_optab): Don't allow the `l' suffix for moving
624 between memory and segment register. Allow movq for moving between
625 general-purpose register and segment register.
627 2005-02-09 Jan Beulich <jbeulich@novell.com>
630 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
631 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
634 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
636 * m68k.h (m68008, m68ec030, m68882): Remove.
638 (cpu_m68k, cpu_cf): New.
639 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
640 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
642 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
644 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
645 * cgen.h (enum cgen_parse_operand_type): Add
646 CGEN_PARSE_OPERAND_SYMBOLIC.
648 2005-01-21 Fred Fish <fnf@specifixinc.com>
650 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
651 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
652 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
654 2005-01-19 Fred Fish <fnf@specifixinc.com>
656 * mips.h (struct mips_opcode): Add new pinfo2 member.
657 (INSN_ALIAS): New define for opcode table entries that are
658 specific instances of another entry, such as 'move' for an 'or'
660 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
661 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
663 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
665 * mips.h (CPU_RM9000): Define.
666 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
668 2004-11-25 Jan Beulich <jbeulich@novell.com>
670 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
671 to/from test registers are illegal in 64-bit mode. Add missing
672 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
673 (previously one had to explicitly encode a rex64 prefix). Re-enable
674 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
675 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
677 2004-11-23 Jan Beulich <jbeulich@novell.com>
679 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
680 available only with SSE2. Change the MMX additions introduced by SSE
681 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
682 instructions by their now designated identifier (since combining i686
683 and 3DNow! does not really imply 3DNow!A).
685 2004-11-19 Alan Modra <amodra@bigpond.net.au>
687 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
688 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
690 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
691 Vineet Sharma <vineets@noida.hcltech.com>
693 * maxq.h: New file: Disassembly information for the maxq port.
695 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
697 * i386.h (i386_optab): Put back "movzb".
699 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
701 * cris.h (enum cris_insn_version_usage): Tweak formatting and
702 comments. Remove member cris_ver_sim. Add members
703 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
704 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
705 (struct cris_support_reg, struct cris_cond15): New types.
706 (cris_conds15): Declare.
707 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
708 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
709 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
710 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
711 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
714 2004-11-04 Jan Beulich <jbeulich@novell.com>
716 * i386.h (sldx_Suf): Remove.
717 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
718 (q_FP): Define, implying no REX64.
719 (x_FP, sl_FP): Imply FloatMF.
720 (i386_optab): Split reg and mem forms of moving from segment registers
721 so that the memory forms can ignore the 16-/32-bit operand size
722 distinction. Adjust a few others for Intel mode. Remove *FP uses from
723 all non-floating-point instructions. Unite 32- and 64-bit forms of
724 movsx, movzx, and movd. Adjust floating point operations for the above
725 changes to the *FP macros. Add DefaultSize to floating point control
726 insns operating on larger memory ranges. Remove left over comments
727 hinting at certain insns being Intel-syntax ones where the ones
728 actually meant are already gone.
730 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
732 * crx.h: Add COPS_REG_INS - Coprocessor Special register
735 2004-09-30 Paul Brook <paul@codesourcery.com>
737 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
738 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
740 2004-09-11 Theodore A. Roth <troth@openavr.org>
742 * avr.h: Add support for
743 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
745 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
747 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
749 2004-08-24 Dmitry Diky <diwil@spec.ru>
751 * msp430.h (msp430_opc): Add new instructions.
752 (msp430_rcodes): Declare new instructions.
753 (msp430_hcodes): Likewise..
755 2004-08-13 Nick Clifton <nickc@redhat.com>
758 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
761 2004-08-30 Michal Ludvig <mludvig@suse.cz>
763 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
765 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
767 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
769 2004-07-21 Jan Beulich <jbeulich@novell.com>
771 * i386.h: Adjust instruction descriptions to better match the
774 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
776 * arm.h: Remove all old content. Replace with architecture defines
777 from gas/config/tc-arm.c.
779 2004-07-09 Andreas Schwab <schwab@suse.de>
781 * m68k.h: Fix comment.
783 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
787 2004-06-24 Alan Modra <amodra@bigpond.net.au>
789 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
791 2004-05-24 Peter Barada <peter@the-baradas.com>
793 * m68k.h: Add 'size' to m68k_opcode.
795 2004-05-05 Peter Barada <peter@the-baradas.com>
797 * m68k.h: Switch from ColdFire chip name to core variant.
799 2004-04-22 Peter Barada <peter@the-baradas.com>
801 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
802 descriptions for new EMAC cases.
803 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
804 handle Motorola MAC syntax.
805 Allow disassembly of ColdFire V4e object files.
807 2004-03-16 Alan Modra <amodra@bigpond.net.au>
809 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
811 2004-03-12 Jakub Jelinek <jakub@redhat.com>
813 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
815 2004-03-12 Michal Ludvig <mludvig@suse.cz>
817 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
819 2004-03-12 Michal Ludvig <mludvig@suse.cz>
821 * i386.h (i386_optab): Added xstore/xcrypt insns.
823 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
825 * h8300.h (32bit ldc/stc): Add relaxing support.
827 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
829 * h8300.h (BITOP): Pass MEMRELAX flag.
831 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
833 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
836 For older changes see ChangeLog-9103
842 version-control: never