1 2015-11-02 Nick Clifton <nickc@redhat.com>
3 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
5 2015-11-02 Nick Clifton <nickc@redhat.com>
7 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
9 2015-10-28 Yao Qi <yao.qi@linaro.org>
11 * aarch64.h (aarch64_decode_insn): Update declaration.
13 2015-10-07 Yao Qi <yao.qi@linaro.org>
15 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
18 2015-10-07 Yao Qi <yao.qi@linaro.org>
20 * aarch64.h [__cplusplus]: Wrap in extern "C".
22 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
23 Cupertino Miranda <cmiranda@synopsys.com>
25 * arc-func.h: New file.
28 2015-10-02 Yao Qi <yao.qi@linaro.org>
30 * aarch64.h (aarch64_zero_register_p): Move the declaration
33 2015-10-02 Yao Qi <yao.qi@linaro.org>
35 * aarch64.h (aarch64_decode_insn): Declare it.
37 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
39 * s390.h (S390_INSTR_FLAG_HTM): New flag.
40 (S390_INSTR_FLAG_VX): New flag.
41 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
43 2015-09-23 Nick Clifton <nickc@redhat.com>
45 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
48 2015-09-22 Nick Clifton <nickc@redhat.com>
50 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
52 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
54 * visium.h (gen_reg_table): Make static.
55 (fp_reg_table): Likewise.
58 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
60 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
61 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
62 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
63 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
65 2015-07-03 Alan Modra <amodra@gmail.com>
67 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
69 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
70 Cesar Philippidis <cesar@codesourcery.com>
72 * nios2.h (enum iw_format_type): Add R2 formats.
73 (enum overflow_type): Add signed_immed12_overflow and
74 enumeration_overflow for R2.
75 (struct nios2_opcode): Document new argument letters for R2.
76 (REG_3BIT, REG_LDWM, REG_POP): Define.
77 (includes): Include nios2r2.h.
78 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
79 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
80 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
81 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
82 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
83 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
85 * nios2r2.h: New file.
87 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
89 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
90 (ppc_optional_operand_value): New inline function.
92 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
94 * aarch64.h (AARCH64_V8_1): New.
96 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
98 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
99 (ARM_ARCH_V8_1A): New.
100 (ARM_ARCH_V8_1A_FP): New.
101 (ARM_ARCH_V8_1A_SIMD): New.
102 (ARM_ARCH_V8_1A_CRYPTOV1): New.
103 (ARM_FEATURE_CORE): New.
105 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
107 * arm.h (ARM_EXT2_PAN): New.
108 (ARM_FEATURE_CORE_HIGH): New.
110 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
112 * arm.h (ARM_FEATURE_ALL): New.
114 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
116 * aarch64.h (AARCH64_FEATURE_RDMA): New.
118 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
120 * aarch64.h (AARCH64_FEATURE_LOR): New.
122 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
124 * aarch64.h (AARCH64_FEATURE_PAN): New.
125 (aarch64_sys_reg_supported_p): Declare.
126 (aarch64_pstatefield_supported_p): Declare.
128 2015-04-30 DJ Delorie <dj@redhat.com>
130 * rl78.h (RL78_Dis_Isa): New.
131 (rl78_decode_opcode): Add ISA parameter.
133 2015-03-24 Terry Guo <terry.guo@arm.com>
135 * arm.h (arm_feature_set): Extended to provide more available bits.
136 (ARM_ANY): Updated to follow above new definition.
137 (ARM_CPU_HAS_FEATURE): Likewise.
138 (ARM_CPU_IS_ANY): Likewise.
139 (ARM_MERGE_FEATURE_SETS): Likewise.
140 (ARM_CLEAR_FEATURE): Likewise.
141 (ARM_FEATURE): Likewise.
142 (ARM_FEATURE_COPY): New macro.
143 (ARM_FEATURE_EQUAL): Likewise.
144 (ARM_FEATURE_ZERO): Likewise.
145 (ARM_FEATURE_CORE_EQUAL): Likewise.
146 (ARM_FEATURE_LOW): Likewise.
147 (ARM_FEATURE_CORE_LOW): Likewise.
148 (ARM_FEATURE_CORE_COPROC): Likewise.
150 2015-02-19 Pedro Alves <palves@redhat.com>
152 * cgen.h [__cplusplus]: Wrap in extern "C".
153 * msp430-decode.h [__cplusplus]: Likewise.
154 * nios2.h [__cplusplus]: Likewise.
155 * rl78.h [__cplusplus]: Likewise.
156 * rx.h [__cplusplus]: Likewise.
157 * tilegx.h [__cplusplus]: Likewise.
159 2015-01-28 James Bowman <james.bowman@ftdichip.com>
163 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
165 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
167 2015-01-01 Alan Modra <amodra@gmail.com>
169 Update year range in copyright notice of all files.
171 2014-12-27 Anthony Green <green@moxielogic.com>
173 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
174 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
176 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
178 * visium.h: New file.
180 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
182 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
183 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
184 (NIOS2_INSN_OPTARG): Renumber.
186 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
188 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
189 declaration. Fix obsolete comment.
191 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
193 * nios2.h (enum iw_format_type): New.
194 (struct nios2_opcode): Update comments. Add size and format fields.
195 (NIOS2_INSN_OPTARG): New.
196 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
197 (struct nios2_reg): Add regtype field.
198 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
199 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
200 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
201 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
202 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
203 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
204 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
205 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
206 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
207 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
208 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
209 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
210 (OP_MASK_OP, OP_SH_OP): Delete.
211 (OP_MASK_IOP, OP_SH_IOP): Delete.
212 (OP_MASK_IRD, OP_SH_IRD): Delete.
213 (OP_MASK_IRT, OP_SH_IRT): Delete.
214 (OP_MASK_IRS, OP_SH_IRS): Delete.
215 (OP_MASK_ROP, OP_SH_ROP): Delete.
216 (OP_MASK_RRD, OP_SH_RRD): Delete.
217 (OP_MASK_RRT, OP_SH_RRT): Delete.
218 (OP_MASK_RRS, OP_SH_RRS): Delete.
219 (OP_MASK_JOP, OP_SH_JOP): Delete.
220 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
221 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
222 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
223 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
224 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
225 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
226 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
227 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
228 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
229 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
230 (OP_MASK_<insn>, OP_MASK): Delete.
231 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
232 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
233 Include nios2r1.h to define new instruction opcode constants
235 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
236 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
237 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
238 (NUMOPCODES, NUMREGISTERS): Delete.
239 * nios2r1.h: New file.
241 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
243 * sparc.h (HWCAP2_VIS3B): Documentation improved.
245 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
247 * sparc.h (sparc_opcode): new field `hwcaps2'.
248 (HWCAP2_FJATHPLUS): New define.
249 (HWCAP2_VIS3B): Likewise.
250 (HWCAP2_ADP): Likewise.
251 (HWCAP2_SPARC5): Likewise.
252 (HWCAP2_MWAIT): Likewise.
253 (HWCAP2_XMPMUL): Likewise.
254 (HWCAP2_XMONT): Likewise.
255 (HWCAP2_NSEC): Likewise.
256 (HWCAP2_FJATHHPC): Likewise.
257 (HWCAP2_FJDES): Likewise.
258 (HWCAP2_FJAES): Likewise.
259 Document the new operand kind `{', corresponding to the mcdper
260 ancillary state register.
261 Document the new operand kind }, which represents frsd floating
262 point registers (double precision) which must be the same than
263 frs1 in its containing instruction.
265 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
267 * nds32.h: Add new opcode declaration.
269 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
270 Matthew Fortune <matthew.fortune@imgtec.com>
272 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
273 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
274 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
275 +I, +O, +R, +:, +\, +", +;
276 (mips_check_prev_operand): New struct.
277 (INSN2_FORBIDDEN_SLOT): New define.
278 (INSN_ISA32R6): New define.
279 (INSN_ISA64R6): New define.
280 (INSN_UPTO32R6): New define.
281 (INSN_UPTO64R6): New define.
282 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
283 (ISA_MIPS32R6): New define.
284 (ISA_MIPS64R6): New define.
285 (CPU_MIPS32R6): New define.
286 (CPU_MIPS64R6): New define.
287 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
289 2014-09-03 Jiong Wang <jiong.wang@arm.com>
291 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
292 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
293 (aarch64_insn_class): Add lse_atomic.
294 (F_LSE_SZ): New field added.
295 (opcode_has_special_coder): Recognize F_LSE_SZ.
297 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
299 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
302 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
304 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
305 (INSN_LOAD_COPROC): New define.
306 (INSN_COPROC_MOVE_DELAY): Rename to...
307 (INSN_COPROC_MOVE): New define.
309 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
310 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
311 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
312 Soundararajan <Sounderarajan.D@atmel.com>
314 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
315 (AVR_ISA_2xxxa): Define ISA without LPM.
316 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
317 Add doc for contraint used in 16 bit lds/sts.
318 Adjust ISA group for icall, ijmp, pop and push.
319 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
321 2014-05-19 Nick Clifton <nickc@redhat.com>
323 * msp430.h (struct msp430_operand_s): Add vshift field.
325 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
327 * mips.h (INSN_ISA_MASK): Updated.
328 (INSN_ISA32R3): New define.
329 (INSN_ISA32R5): New define.
330 (INSN_ISA64R3): New define.
331 (INSN_ISA64R5): New define.
332 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
333 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
334 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
336 (INSN_UPTO32R3): New define.
337 (INSN_UPTO32R5): New define.
338 (INSN_UPTO64R3): New define.
339 (INSN_UPTO64R5): New define.
340 (ISA_MIPS32R3): New define.
341 (ISA_MIPS32R5): New define.
342 (ISA_MIPS64R3): New define.
343 (ISA_MIPS64R5): New define.
344 (CPU_MIPS32R3): New define.
345 (CPU_MIPS32R5): New define.
346 (CPU_MIPS64R3): New define.
347 (CPU_MIPS64R5): New define.
349 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
351 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
353 2014-04-22 Christian Svensson <blue@cmd.nu>
357 2014-03-05 Alan Modra <amodra@gmail.com>
359 Update copyright years.
361 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
363 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
366 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
367 Wei-Cheng Wang <cole945@gmail.com>
369 * nds32.h: New file for Andes NDS32.
371 2013-12-07 Mike Frysinger <vapier@gentoo.org>
373 * bfin.h: Remove +x file mode.
375 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
377 * aarch64.h (aarch64_pstatefields): Change element type to
380 2013-11-18 Renlin Li <Renlin.Li@arm.com>
382 * arm.h (ARM_AEXT_V7VE): New define.
383 (ARM_ARCH_V7VE): New define.
384 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
386 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
390 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
392 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
393 (aarch64_sys_reg_writeonly_p): Ditto.
395 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
397 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
398 (aarch64_sys_reg_writeonly_p): Ditto.
400 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
402 * aarch64.h (aarch64_sys_reg): New typedef.
403 (aarch64_sys_regs): Change to define with the new type.
404 (aarch64_sys_reg_deprecated_p): Declare.
406 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
408 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
409 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
411 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
413 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
414 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
415 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
416 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
417 For MIPS, update extension character sequences after +.
418 (ASE_MSA): New define.
419 (ASE_MSA64): New define.
420 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
421 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
422 For microMIPS, update extension character sequences after +.
424 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
429 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
431 * mips.h: Remove references to "+I" and imm2_expr.
433 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
435 * mips.h (M_DEXT, M_DINS): Delete.
437 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
439 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
440 (mips_optional_operand_p): New function.
442 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
443 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h: Document new VU0 operand characters.
446 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
447 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
448 (OP_REG_R5900_ACC): New mips_reg_operand_types.
449 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
450 (mips_vu0_channel_mask): Declare.
452 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
454 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
455 (mips_int_operand_min, mips_int_operand_max): New functions.
456 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
458 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
460 * mips.h (mips_decode_reg_operand): New function.
461 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
462 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
463 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
465 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
466 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
467 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
468 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
469 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
470 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
471 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
472 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
473 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
474 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
475 macros to cover the gaps.
476 (INSN2_MOD_SP): Replace with...
477 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
478 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
479 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
480 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
481 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
484 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
486 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
487 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
488 (MIPS16_INSN_COND_BRANCH): Delete.
490 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
491 Kirill Yukhin <kirill.yukhin@intel.com>
492 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
494 * i386.h (BND_PREFIX_OPCODE): New.
496 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
498 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
499 OP_SAVE_RESTORE_LIST.
500 (decode_mips16_operand): Declare.
502 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
504 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
505 (mips_operand, mips_int_operand, mips_mapped_int_operand)
506 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
507 (mips_pcrel_operand): New structures.
508 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
509 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
510 (decode_mips_operand, decode_micromips_operand): Declare.
512 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
514 * mips.h: Document MIPS16 "I" opcode.
516 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
518 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
519 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
520 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
521 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
522 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
523 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
524 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
525 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
526 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
527 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
528 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
529 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
530 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
532 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
533 (M_USD_AB): ...these.
535 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
537 * mips.h: Remove documentation of "[" and "]". Update documentation
538 of "k" and the MDMX formats.
540 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
542 * mips.h: Update documentation of "+s" and "+S".
544 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
546 * mips.h: Document "+i".
548 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
550 * mips.h: Remove "mi" documentation. Update "mh" documentation.
551 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
553 (INSN2_WRITE_GPR_MHI): Rename to...
554 (INSN2_WRITE_GPR_MH): ...this.
556 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
558 * mips.h: Remove documentation of "+D" and "+T".
560 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
562 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
563 Use "source" rather than "destination" for microMIPS "G".
565 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
567 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
570 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
572 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
574 2013-06-17 Catherine Moore <clm@codesourcery.com>
575 Maciej W. Rozycki <macro@codesourcery.com>
576 Chao-Ying Fu <fu@mips.com>
578 * mips.h (OP_SH_EVAOFFSET): Define.
579 (OP_MASK_EVAOFFSET): Define.
580 (INSN_ASE_MASK): Delete.
582 (M_CACHEE_AB, M_CACHEE_OB): New.
583 (M_LBE_OB, M_LBE_AB): New.
584 (M_LBUE_OB, M_LBUE_AB): New.
585 (M_LHE_OB, M_LHE_AB): New.
586 (M_LHUE_OB, M_LHUE_AB): New.
587 (M_LLE_AB, M_LLE_OB): New.
588 (M_LWE_OB, M_LWE_AB): New.
589 (M_LWLE_AB, M_LWLE_OB): New.
590 (M_LWRE_AB, M_LWRE_OB): New.
591 (M_PREFE_AB, M_PREFE_OB): New.
592 (M_SCE_AB, M_SCE_OB): New.
593 (M_SBE_OB, M_SBE_AB): New.
594 (M_SHE_OB, M_SHE_AB): New.
595 (M_SWE_OB, M_SWE_AB): New.
596 (M_SWLE_AB, M_SWLE_OB): New.
597 (M_SWRE_AB, M_SWRE_OB): New.
598 (MICROMIPSOP_SH_EVAOFFSET): Define.
599 (MICROMIPSOP_MASK_EVAOFFSET): Define.
601 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
603 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
605 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
607 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
609 2013-05-09 Andrew Pinski <apinski@cavium.com>
611 * mips.h (OP_MASK_CODE10): Correct definition.
612 (OP_SH_CODE10): Likewise.
613 Add a comment that "+J" is used now for OP_*CODE10.
614 (INSN_ASE_MASK): Update.
615 (INSN_VIRT): New macro.
616 (INSN_VIRT64): New macro
618 2013-05-02 Nick Clifton <nickc@redhat.com>
620 * msp430.h: Add patterns for MSP430X instructions.
622 2013-04-06 David S. Miller <davem@davemloft.net>
624 * sparc.h (F_PREFERRED): Define.
625 (F_PREF_ALIAS): Define.
627 2013-04-03 Nick Clifton <nickc@redhat.com>
629 * v850.h (V850_INVERSE_PCREL): Define.
631 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
634 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
636 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
639 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
641 * tic6xc-opcode-table.h: Add 16-bit insns.
642 * tic6x.h: Add support for 16-bit insns.
644 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
646 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
647 and mov.b/w/l Rs,@(d:32,ERd).
649 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
652 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
653 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
654 tic6x_operand_xregpair operand coding type.
655 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
656 opcode field, usu ORXREGD1324 for the src2 operand and remove the
659 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
662 * tic6x.h (enum tic6x_coding_method): Add
663 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
664 separately the msb and lsb of a register pair. This is needed to
665 encode the opcodes in the same way as TI assembler does.
666 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
667 and rsqrdp opcodes to use the new field coding types.
669 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
671 * arm.h (CRC_EXT_ARMV8): New constant.
672 (ARCH_CRC_ARMV8): New macro.
674 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
676 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
678 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
679 Andrew Jenner <andrew@codesourcery.com>
681 Based on patches from Altera Corporation.
685 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
687 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
689 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
692 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
694 2013-01-24 Nick Clifton <nickc@redhat.com>
696 * v850.h: Add e3v5 support.
698 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
700 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
702 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
704 * ppc.h (PPC_OPCODE_POWER8): New define.
705 (PPC_OPCODE_HTM): Likewise.
707 2013-01-10 Will Newton <will.newton@imgtec.com>
711 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
713 * cr16.h (make_instruction): Rename to cr16_make_instruction.
714 (match_opcode): Rename to cr16_match_opcode.
716 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
718 * mips.h: Add support for r5900 instructions including lq and sq.
720 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
722 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
723 (make_instruction,match_opcode): Added function prototypes.
724 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
726 2012-11-23 Alan Modra <amodra@gmail.com>
728 * ppc.h (ppc_parse_cpu): Update prototype.
730 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
732 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
733 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
735 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
737 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
739 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
741 * ia64.h (ia64_opnd): Add new operand types.
743 2012-08-21 David S. Miller <davem@davemloft.net>
745 * sparc.h (F3F4): New macro.
747 2012-08-13 Ian Bolton <ian.bolton@arm.com>
748 Laurent Desnogues <laurent.desnogues@arm.com>
749 Jim MacArthur <jim.macarthur@arm.com>
750 Marcus Shawcroft <marcus.shawcroft@arm.com>
751 Nigel Stephens <nigel.stephens@arm.com>
752 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
753 Richard Earnshaw <rearnsha@arm.com>
754 Sofiane Naci <sofiane.naci@arm.com>
755 Tejas Belagod <tejas.belagod@arm.com>
756 Yufeng Zhang <yufeng.zhang@arm.com>
758 * aarch64.h: New file.
760 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
761 Maciej W. Rozycki <macro@codesourcery.com>
763 * mips.h (mips_opcode): Add the exclusions field.
764 (OPCODE_IS_MEMBER): Remove macro.
765 (cpu_is_member): New inline function.
766 (opcode_is_member): Likewise.
768 2012-07-31 Chao-Ying Fu <fu@mips.com>
769 Catherine Moore <clm@codesourcery.com>
770 Maciej W. Rozycki <macro@codesourcery.com>
772 * mips.h: Document microMIPS DSP ASE usage.
773 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
774 microMIPS DSP ASE support.
775 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
776 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
777 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
778 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
779 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
780 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
781 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
783 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
785 * mips.h: Fix a typo in description.
787 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
789 * avr.h: (AVR_ISA_XCH): New define.
790 (AVR_ISA_XMEGA): Use it.
791 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
793 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
795 * m68hc11.h: Add XGate definitions.
796 (struct m68hc11_opcode): Add xg_mask field.
798 2012-05-14 Catherine Moore <clm@codesourcery.com>
799 Maciej W. Rozycki <macro@codesourcery.com>
800 Rhonda Wittels <rhonda@codesourcery.com>
802 * ppc.h (PPC_OPCODE_VLE): New definition.
803 (PPC_OP_SA): New macro.
804 (PPC_OP_SE_VLE): New macro.
805 (PPC_OP): Use a variable shift amount.
806 (powerpc_operand): Update comments.
807 (PPC_OPSHIFT_INV): New macro.
808 (PPC_OPERAND_CR): Replace with...
809 (PPC_OPERAND_CR_BIT): ...this and
810 (PPC_OPERAND_CR_REG): ...this.
813 2012-05-03 Sean Keys <skeys@ipdatasys.com>
815 * xgate.h: Header file for XGATE assembler.
817 2012-04-27 David S. Miller <davem@davemloft.net>
819 * sparc.h: Document new arg code' )' for crypto RS3
822 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
823 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
824 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
825 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
826 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
827 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
828 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
829 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
830 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
831 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
832 HWCAP_CBCOND, HWCAP_CRC32): New defines.
834 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
836 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
838 2012-02-27 Alan Modra <amodra@gmail.com>
840 * crx.h (cst4_map): Update declaration.
842 2012-02-25 Walter Lee <walt@tilera.com>
844 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
846 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
847 TILEPRO_OPC_LW_TLS_SN.
849 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
851 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
852 (XRELEASE_PREFIX_OPCODE): Likewise.
854 2011-12-08 Andrew Pinski <apinski@cavium.com>
855 Adam Nemet <anemet@caviumnetworks.com>
857 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
858 (INSN_OCTEON2): New macro.
859 (CPU_OCTEON2): New macro.
860 (OPCODE_IS_MEMBER): Add Octeon2.
862 2011-11-29 Andrew Pinski <apinski@cavium.com>
864 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
865 (INSN_OCTEONP): New macro.
866 (CPU_OCTEONP): New macro.
867 (OPCODE_IS_MEMBER): Add Octeon+.
868 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
870 2011-11-01 DJ Delorie <dj@redhat.com>
874 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
876 * mips.h: Fix a typo in description.
878 2011-09-21 David S. Miller <davem@davemloft.net>
880 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
881 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
882 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
883 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
885 2011-08-09 Chao-ying Fu <fu@mips.com>
886 Maciej W. Rozycki <macro@codesourcery.com>
888 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
889 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
890 (INSN_ASE_MASK): Add the MCU bit.
891 (INSN_MCU): New macro.
892 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
893 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
895 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
897 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
898 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
899 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
900 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
901 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
902 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
903 (INSN2_READ_GPR_MMN): Likewise.
904 (INSN2_READ_FPR_D): Change the bit used.
905 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
906 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
907 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
908 (INSN2_COND_BRANCH): Likewise.
909 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
910 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
911 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
912 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
913 (INSN2_MOD_GPR_MN): Likewise.
915 2011-08-05 David S. Miller <davem@davemloft.net>
917 * sparc.h: Document new format codes '4', '5', and '('.
918 (OPF_LOW4, RS3): New macros.
920 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
922 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
923 order of flags documented.
925 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
927 * mips.h: Clarify the description of microMIPS instruction
929 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
931 2011-07-24 Chao-ying Fu <fu@mips.com>
932 Maciej W. Rozycki <macro@codesourcery.com>
934 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
935 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
936 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
937 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
938 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
939 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
940 (OP_MASK_RS3, OP_SH_RS3): Likewise.
941 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
942 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
943 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
944 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
945 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
946 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
947 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
948 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
949 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
950 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
951 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
952 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
953 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
954 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
955 (INSN_WRITE_GPR_S): New macro.
956 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
957 (INSN2_READ_FPR_D): Likewise.
958 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
959 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
960 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
961 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
962 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
963 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
964 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
965 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
966 (CPU_MICROMIPS): New macro.
967 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
968 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
969 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
970 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
971 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
972 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
973 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
974 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
975 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
976 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
977 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
978 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
979 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
980 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
981 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
982 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
983 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
984 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
985 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
986 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
987 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
988 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
989 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
990 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
991 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
992 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
993 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
994 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
995 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
996 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
997 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
998 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
999 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1000 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1001 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1002 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1003 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1004 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1005 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1006 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1007 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1008 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1009 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1010 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1011 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1012 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1013 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1014 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1015 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1016 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1017 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1018 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1019 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1020 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1021 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1022 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1023 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1024 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1025 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1026 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1027 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1028 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1029 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1030 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1031 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1032 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1033 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1034 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1035 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1036 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1037 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1038 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1039 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1040 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1041 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1042 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1043 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1044 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1045 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1046 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1047 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1048 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1049 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1050 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1051 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1052 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1053 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1054 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1055 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1056 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1057 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1058 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1059 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1060 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1061 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1062 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1063 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1064 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1065 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1066 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1067 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1068 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1069 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1070 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1071 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1072 (micromips_opcodes): New declaration.
1073 (bfd_micromips_num_opcodes): Likewise.
1075 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1077 * mips.h (INSN_TRAP): Rename to...
1078 (INSN_NO_DELAY_SLOT): ... this.
1079 (INSN_SYNC): Remove macro.
1081 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1083 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1084 a duplicate of AVR_ISA_SPM.
1086 2011-07-01 Nick Clifton <nickc@redhat.com>
1088 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1090 2011-06-18 Robin Getz <robin.getz@analog.com>
1092 * bfin.h (is_macmod_signed): New func
1094 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1096 * bfin.h (is_macmod_pmove): Add missing space before func args.
1097 (is_macmod_hmove): Likewise.
1099 2011-06-13 Walter Lee <walt@tilera.com>
1101 * tilegx.h: New file.
1102 * tilepro.h: New file.
1104 2011-05-31 Paul Brook <paul@codesourcery.com>
1106 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1108 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1110 * s390.h: Replace S390_OPERAND_REG_EVEN with
1111 S390_OPERAND_REG_PAIR.
1113 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1115 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1117 2011-04-18 Julian Brown <julian@codesourcery.com>
1119 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1121 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1124 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1126 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1128 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1129 New instruction set flags.
1130 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1132 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1134 * mips.h (M_PREF_AB): New enum value.
1136 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1138 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1140 (is_macmod_pmove, is_macmod_hmove): New functions.
1142 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1144 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1146 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1148 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1149 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1151 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1154 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1157 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1160 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1162 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1164 * mips.h: Update commentary after last commit.
1166 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1168 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1169 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1170 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1172 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1174 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1176 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1178 * mips.h: Fix previous commit.
1180 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1182 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1183 (INSN_LOONGSON_3A): Clear bit 31.
1185 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1188 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1189 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1190 (ARM_ARCH_V6M_ONLY): New define.
1192 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1194 * mips.h (INSN_LOONGSON_3A): Defined.
1195 (CPU_LOONGSON_3A): Defined.
1196 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1198 2010-10-09 Matt Rice <ratmice@gmail.com>
1200 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1201 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1203 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1205 * arm.h (ARM_EXT_VIRT): New define.
1206 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1207 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1210 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1212 * arm.h (ARM_AEXT_ADIV): New define.
1213 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1215 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1217 * arm.h (ARM_EXT_OS): New define.
1218 (ARM_AEXT_V6SM): Likewise.
1219 (ARM_ARCH_V6SM): Likewise.
1221 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1223 * arm.h (ARM_EXT_MP): Add.
1224 (ARM_ARCH_V7A_MP): Likewise.
1226 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1228 * bfin.h: Declare pseudoChr structs/defines.
1230 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1232 * bfin.h: Strip trailing whitespace.
1234 2010-07-29 DJ Delorie <dj@redhat.com>
1236 * rx.h (RX_Operand_Type): Add TwoReg.
1237 (RX_Opcode_ID): Remove ediv and ediv2.
1239 2010-07-27 DJ Delorie <dj@redhat.com>
1241 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1243 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1244 Ina Pandit <ina.pandit@kpitcummins.com>
1246 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1247 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1248 PROCESSOR_V850E2_ALL.
1249 Remove PROCESSOR_V850EA support.
1250 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1251 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1252 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1253 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1254 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1255 V850_OPERAND_PERCENT.
1256 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1258 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1261 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1263 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1264 (MIPS16_INSN_BRANCH): Rename to...
1265 (MIPS16_INSN_COND_BRANCH): ... this.
1267 2010-07-03 Alan Modra <amodra@gmail.com>
1269 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1270 Renumber other PPC_OPCODE defines.
1272 2010-07-03 Alan Modra <amodra@gmail.com>
1274 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1276 2010-06-29 Alan Modra <amodra@gmail.com>
1278 * maxq.h: Delete file.
1280 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1282 * ppc.h (PPC_OPCODE_E500): Define.
1284 2010-05-26 Catherine Moore <clm@codesourcery.com>
1286 * opcode/mips.h (INSN_MIPS16): Remove.
1288 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1290 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1292 2010-04-15 Nick Clifton <nickc@redhat.com>
1294 * alpha.h: Update copyright notice to use GPLv3.
1300 * convex.h: Likewise.
1307 * h8300.h: Likewise.
1314 * m68hc11.h: Likewise.
1320 * mn10200.h: Likewise.
1321 * mn10300.h: Likewise.
1322 * msp430.h: Likewise.
1324 * ns32k.h: Likewise.
1326 * pdp11.h: Likewise.
1333 * score-datadep.h: Likewise.
1334 * score-inst.h: Likewise.
1335 * sparc.h: Likewise.
1336 * spu-insns.h: Likewise.
1338 * tic30.h: Likewise.
1339 * tic4x.h: Likewise.
1340 * tic54x.h: Likewise.
1341 * tic80.h: Likewise.
1345 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1347 * tic6x-control-registers.h, tic6x-insn-formats.h,
1348 tic6x-opcode-table.h, tic6x.h: New.
1350 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1352 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1354 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1356 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1358 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1360 * ia64.h (ia64_find_opcode): Remove argument name.
1361 (ia64_find_next_opcode): Likewise.
1362 (ia64_dis_opcode): Likewise.
1363 (ia64_free_opcode): Likewise.
1364 (ia64_find_dependency): Likewise.
1366 2009-11-22 Doug Evans <dje@sebabeach.org>
1368 * cgen.h: Include bfd_stdint.h.
1369 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1371 2009-11-18 Paul Brook <paul@codesourcery.com>
1373 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1375 2009-11-17 Paul Brook <paul@codesourcery.com>
1376 Daniel Jacobowitz <dan@codesourcery.com>
1378 * arm.h (ARM_EXT_V6_DSP): Define.
1379 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1380 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1382 2009-11-04 DJ Delorie <dj@redhat.com>
1384 * rx.h (rx_decode_opcode) (mvtipl): Add.
1385 (mvtcp, mvfcp, opecp): Remove.
1387 2009-11-02 Paul Brook <paul@codesourcery.com>
1389 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1390 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1391 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1392 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1393 FPU_ARCH_NEON_VFP_V4): Define.
1395 2009-10-23 Doug Evans <dje@sebabeach.org>
1397 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1398 * cgen.h: Update. Improve multi-inclusion macro name.
1400 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1402 * ppc.h (PPC_OPCODE_476): Define.
1404 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1406 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1408 2009-09-29 DJ Delorie <dj@redhat.com>
1412 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1414 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1416 2009-09-21 Ben Elliston <bje@au.ibm.com>
1418 * ppc.h (PPC_OPCODE_PPCA2): New.
1420 2009-09-05 Martin Thuresson <martin@mtme.org>
1422 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1424 2009-08-29 Martin Thuresson <martin@mtme.org>
1426 * tic30.h (template): Rename type template to
1427 insn_template. Updated code to use new name.
1428 * tic54x.h (template): Rename type template to
1431 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1433 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1435 2009-06-11 Anthony Green <green@moxielogic.com>
1437 * moxie.h (MOXIE_F3_PCREL): Define.
1438 (moxie_form3_opc_info): Grow.
1440 2009-06-06 Anthony Green <green@moxielogic.com>
1442 * moxie.h (MOXIE_F1_M): Define.
1444 2009-04-15 Anthony Green <green@moxielogic.com>
1448 2009-04-06 DJ Delorie <dj@redhat.com>
1450 * h8300.h: Add relaxation attributes to MOVA opcodes.
1452 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1454 * ppc.h (ppc_parse_cpu): Declare.
1456 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1458 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1459 and _IMM11 for mbitclr and mbitset.
1460 * score-datadep.h: Update dependency information.
1462 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1464 * ppc.h (PPC_OPCODE_POWER7): New.
1466 2009-02-06 Doug Evans <dje@google.com>
1468 * i386.h: Add comment regarding sse* insns and prefixes.
1470 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1472 * mips.h (INSN_XLR): Define.
1473 (INSN_CHIP_MASK): Update.
1475 (OPCODE_IS_MEMBER): Update.
1476 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1478 2009-01-28 Doug Evans <dje@google.com>
1480 * opcode/i386.h: Add multiple inclusion protection.
1481 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1482 (EDI_REG_NUM): New macros.
1483 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1484 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1485 (REX_PREFIX_P): New macro.
1487 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1489 * ppc.h (struct powerpc_opcode): New field "deprecated".
1490 (PPC_OPCODE_NOPOWER4): Delete.
1492 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1494 * mips.h: Define CPU_R14000, CPU_R16000.
1495 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1497 2008-11-18 Catherine Moore <clm@codesourcery.com>
1499 * arm.h (FPU_NEON_FP16): New.
1500 (FPU_ARCH_NEON_FP16): New.
1502 2008-11-06 Chao-ying Fu <fu@mips.com>
1504 * mips.h: Doucument '1' for 5-bit sync type.
1506 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1508 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1511 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1513 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1515 2008-07-30 Michael J. Eager <eager@eagercon.com>
1517 * ppc.h (PPC_OPCODE_405): Define.
1518 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1520 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1522 * ppc.h (ppc_cpu_t): New typedef.
1523 (struct powerpc_opcode <flags>): Use it.
1524 (struct powerpc_operand <insert, extract>): Likewise.
1525 (struct powerpc_macro <flags>): Likewise.
1527 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1529 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1530 Update comment before MIPS16 field descriptors to mention MIPS16.
1531 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1533 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1534 New bit masks and shift counts for cins and exts.
1536 * mips.h: Document new field descriptors +Q.
1537 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1539 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1541 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1542 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1544 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1546 * ppc.h: (PPC_OPCODE_E500MC): New.
1548 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1550 * i386.h (MAX_OPERANDS): Set to 5.
1551 (MAX_MNEM_SIZE): Changed to 20.
1553 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1555 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1557 2008-03-09 Paul Brook <paul@codesourcery.com>
1559 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1561 2008-03-04 Paul Brook <paul@codesourcery.com>
1563 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1564 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1565 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1567 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1568 Nick Clifton <nickc@redhat.com>
1571 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1572 with a 32-bit displacement but without the top bit of the 4th byte
1575 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1577 * cr16.h (cr16_num_optab): Declared.
1579 2008-02-14 Hakan Ardo <hakan@debian.org>
1582 * avr.h (AVR_ISA_2xxe): Define.
1584 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1586 * mips.h: Update copyright.
1587 (INSN_CHIP_MASK): New macro.
1588 (INSN_OCTEON): New macro.
1589 (CPU_OCTEON): New macro.
1590 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1592 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1594 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1596 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1598 * avr.h (AVR_ISA_USB162): Add new opcode set.
1599 (AVR_ISA_AVR3): Likewise.
1601 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1603 * mips.h (INSN_LOONGSON_2E): New.
1604 (INSN_LOONGSON_2F): New.
1605 (CPU_LOONGSON_2E): New.
1606 (CPU_LOONGSON_2F): New.
1607 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1609 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1611 * mips.h (INSN_ISA*): Redefine certain values as an
1612 enumeration. Update comments.
1613 (mips_isa_table): New.
1614 (ISA_MIPS*): Redefine to match enumeration.
1615 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1618 2007-08-08 Ben Elliston <bje@au.ibm.com>
1620 * ppc.h (PPC_OPCODE_PPCPS): New.
1622 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1624 * m68k.h: Document j K & E.
1626 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1628 * cr16.h: New file for CR16 target.
1630 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1632 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1634 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1636 * m68k.h (mcfisa_c): New.
1637 (mcfusp, mcf_mask): Adjust.
1639 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1641 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1642 (num_powerpc_operands): Declare.
1643 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1644 (PPC_OPERAND_PLUS1): Define.
1646 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1648 * i386.h (REX_MODE64): Renamed to ...
1650 (REX_EXTX): Renamed to ...
1652 (REX_EXTY): Renamed to ...
1654 (REX_EXTZ): Renamed to ...
1657 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1659 * i386.h: Add entries from config/tc-i386.h and move tables
1660 to opcodes/i386-opc.h.
1662 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1664 * i386.h (FloatDR): Removed.
1665 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1667 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1669 * spu-insns.h: Add soma double-float insns.
1671 2007-02-20 Thiemo Seufer <ths@mips.com>
1672 Chao-Ying Fu <fu@mips.com>
1674 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1675 (INSN_DSPR2): Add flag for DSP R2 instructions.
1676 (M_BALIGN): New macro.
1678 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1680 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1681 and Seg3ShortFrom with Shortform.
1683 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1686 * i386.h (i386_optab): Put the real "test" before the pseudo
1689 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1691 * m68k.h (m68010up): OR fido_a.
1693 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1695 * m68k.h (fido_a): New.
1697 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1699 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1700 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1703 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1705 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1707 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1709 * score-inst.h (enum score_insn_type): Add Insn_internal.
1711 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1712 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1713 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1714 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1715 Alan Modra <amodra@bigpond.net.au>
1717 * spu-insns.h: New file.
1720 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1722 * ppc.h (PPC_OPCODE_CELL): Define.
1724 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1726 * i386.h : Modify opcode to support for the change in POPCNT opcode
1727 in amdfam10 architecture.
1729 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1731 * i386.h: Replace CpuMNI with CpuSSSE3.
1733 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1734 Joseph Myers <joseph@codesourcery.com>
1735 Ian Lance Taylor <ian@wasabisystems.com>
1736 Ben Elliston <bje@wasabisystems.com>
1738 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1740 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1742 * score-datadep.h: New file.
1743 * score-inst.h: New file.
1745 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1748 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1749 movdq2q and movq2dq.
1751 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1752 Michael Meissner <michael.meissner@amd.com>
1754 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1756 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1758 * i386.h (i386_optab): Add "nop" with memory reference.
1760 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386.h (i386_optab): Update comment for 64bit NOP.
1764 2006-06-06 Ben Elliston <bje@au.ibm.com>
1765 Anton Blanchard <anton@samba.org>
1767 * ppc.h (PPC_OPCODE_POWER6): Define.
1770 2006-06-05 Thiemo Seufer <ths@mips.com>
1772 * mips.h: Improve description of MT flags.
1774 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1776 * m68k.h (mcf_mask): Define.
1778 2006-05-05 Thiemo Seufer <ths@mips.com>
1779 David Ung <davidu@mips.com>
1781 * mips.h (enum): Add macro M_CACHE_AB.
1783 2006-05-04 Thiemo Seufer <ths@mips.com>
1784 Nigel Stephens <nigel@mips.com>
1785 David Ung <davidu@mips.com>
1787 * mips.h: Add INSN_SMARTMIPS define.
1789 2006-04-30 Thiemo Seufer <ths@mips.com>
1790 David Ung <davidu@mips.com>
1792 * mips.h: Defines udi bits and masks. Add description of
1793 characters which may appear in the args field of udi
1796 2006-04-26 Thiemo Seufer <ths@networkno.de>
1798 * mips.h: Improve comments describing the bitfield instruction
1801 2006-04-26 Julian Brown <julian@codesourcery.com>
1803 * arm.h (FPU_VFP_EXT_V3): Define constant.
1804 (FPU_NEON_EXT_V1): Likewise.
1805 (FPU_VFP_HARD): Update.
1806 (FPU_VFP_V3): Define macro.
1807 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1809 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1811 * avr.h (AVR_ISA_PWMx): New.
1813 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1815 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1816 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1817 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1818 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1819 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1821 2006-03-10 Paul Brook <paul@codesourcery.com>
1823 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1825 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1827 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1828 first. Correct mask of bb "B" opcode.
1830 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1832 * i386.h (i386_optab): Support Intel Merom New Instructions.
1834 2006-02-24 Paul Brook <paul@codesourcery.com>
1836 * arm.h: Add V7 feature bits.
1838 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1840 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1842 2006-01-31 Paul Brook <paul@codesourcery.com>
1843 Richard Earnshaw <rearnsha@arm.com>
1845 * arm.h: Use ARM_CPU_FEATURE.
1846 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1847 (arm_feature_set): Change to a structure.
1848 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1849 ARM_FEATURE): New macros.
1851 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1853 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1854 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1855 (ADD_PC_INCR_OPCODE): Don't define.
1857 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1860 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1862 2005-11-14 David Ung <davidu@mips.com>
1864 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1865 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1866 save/restore encoding of the args field.
1868 2005-10-28 Dave Brolley <brolley@redhat.com>
1870 Contribute the following changes:
1871 2005-02-16 Dave Brolley <brolley@redhat.com>
1873 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1874 cgen_isa_mask_* to cgen_bitset_*.
1877 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1879 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1880 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1881 (CGEN_CPU_TABLE): Make isas a ponter.
1883 2003-09-29 Dave Brolley <brolley@redhat.com>
1885 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1886 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1887 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1889 2002-12-13 Dave Brolley <brolley@redhat.com>
1891 * cgen.h (symcat.h): #include it.
1892 (cgen-bitset.h): #include it.
1893 (CGEN_ATTR_VALUE_TYPE): Now a union.
1894 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1895 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1896 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1897 * cgen-bitset.h: New file.
1899 2005-09-30 Catherine Moore <clm@cm00re.com>
1903 2005-10-24 Jan Beulich <jbeulich@novell.com>
1905 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1908 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1910 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1911 Add FLAG_STRICT to pa10 ftest opcode.
1913 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1915 * hppa.h (pa_opcodes): Remove lha entries.
1917 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1919 * hppa.h (FLAG_STRICT): Revise comment.
1920 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1921 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1924 2005-09-30 Catherine Moore <clm@cm00re.com>
1928 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1930 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1932 2005-09-06 Chao-ying Fu <fu@mips.com>
1934 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1935 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1937 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1938 (INSN_ASE_MASK): Update to include INSN_MT.
1939 (INSN_MT): New define for MT ASE.
1941 2005-08-25 Chao-ying Fu <fu@mips.com>
1943 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1944 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1945 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1946 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1947 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1948 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1950 (INSN_DSP): New define for DSP ASE.
1952 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1956 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1958 * ppc.h (PPC_OPCODE_E300): Define.
1960 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1962 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1964 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1967 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1970 2005-07-27 Jan Beulich <jbeulich@novell.com>
1972 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1973 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1974 Add movq-s as 64-bit variants of movd-s.
1976 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1978 * hppa.h: Fix punctuation in comment.
1980 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1981 implicit space-register addressing. Set space-register bits on opcodes
1982 using implicit space-register addressing. Add various missing pa20
1983 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1984 space-register addressing. Use "fE" instead of "fe" in various
1987 2005-07-18 Jan Beulich <jbeulich@novell.com>
1989 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1991 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1993 * i386.h (i386_optab): Support Intel VMX Instructions.
1995 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1997 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1999 2005-07-05 Jan Beulich <jbeulich@novell.com>
2001 * i386.h (i386_optab): Add new insns.
2003 2005-07-01 Nick Clifton <nickc@redhat.com>
2005 * sparc.h: Add typedefs to structure declarations.
2007 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2010 * i386.h (i386_optab): Update comments for 64bit addressing on
2011 mov. Allow 64bit addressing for mov and movq.
2013 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2015 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2016 respectively, in various floating-point load and store patterns.
2018 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2020 * hppa.h (FLAG_STRICT): Correct comment.
2021 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2022 PA 2.0 mneumonics when equivalent. Entries with cache control
2023 completers now require PA 1.1. Adjust whitespace.
2025 2005-05-19 Anton Blanchard <anton@samba.org>
2027 * ppc.h (PPC_OPCODE_POWER5): Define.
2029 2005-05-10 Nick Clifton <nickc@redhat.com>
2031 * Update the address and phone number of the FSF organization in
2032 the GPL notices in the following files:
2033 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2034 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2035 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2036 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2037 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2038 tic54x.h, tic80.h, v850.h, vax.h
2040 2005-05-09 Jan Beulich <jbeulich@novell.com>
2042 * i386.h (i386_optab): Add ht and hnt.
2044 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2046 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2047 Add xcrypt-ctr. Provide aliases without hyphens.
2049 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2051 Moved from ../ChangeLog
2053 2005-04-12 Paul Brook <paul@codesourcery.com>
2054 * m88k.h: Rename psr macros to avoid conflicts.
2056 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2057 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2058 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2059 and ARM_ARCH_V6ZKT2.
2061 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2062 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2063 Remove redundant instruction types.
2064 (struct argument): X_op - new field.
2065 (struct cst4_entry): Remove.
2066 (no_op_insn): Declare.
2068 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2069 * crx.h (enum argtype): Rename types, remove unused types.
2071 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2072 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2073 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2074 (enum operand_type): Rearrange operands, edit comments.
2075 replace us<N> with ui<N> for unsigned immediate.
2076 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2077 displacements (respectively).
2078 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2079 (instruction type): Add NO_TYPE_INS.
2080 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2081 (operand_entry): New field - 'flags'.
2082 (operand flags): New.
2084 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2085 * crx.h (operand_type): Remove redundant types i3, i4,
2087 Add new unsigned immediate types us3, us4, us5, us16.
2089 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2091 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2092 adjust them accordingly.
2094 2005-04-01 Jan Beulich <jbeulich@novell.com>
2096 * i386.h (i386_optab): Add rdtscp.
2098 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2100 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2101 between memory and segment register. Allow movq for moving between
2102 general-purpose register and segment register.
2104 2005-02-09 Jan Beulich <jbeulich@novell.com>
2107 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2108 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2111 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2113 * m68k.h (m68008, m68ec030, m68882): Remove.
2115 (cpu_m68k, cpu_cf): New.
2116 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2117 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2119 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2121 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2122 * cgen.h (enum cgen_parse_operand_type): Add
2123 CGEN_PARSE_OPERAND_SYMBOLIC.
2125 2005-01-21 Fred Fish <fnf@specifixinc.com>
2127 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2128 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2129 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2131 2005-01-19 Fred Fish <fnf@specifixinc.com>
2133 * mips.h (struct mips_opcode): Add new pinfo2 member.
2134 (INSN_ALIAS): New define for opcode table entries that are
2135 specific instances of another entry, such as 'move' for an 'or'
2136 with a zero operand.
2137 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2138 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2140 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2142 * mips.h (CPU_RM9000): Define.
2143 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2145 2004-11-25 Jan Beulich <jbeulich@novell.com>
2147 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2148 to/from test registers are illegal in 64-bit mode. Add missing
2149 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2150 (previously one had to explicitly encode a rex64 prefix). Re-enable
2151 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2152 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2154 2004-11-23 Jan Beulich <jbeulich@novell.com>
2156 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2157 available only with SSE2. Change the MMX additions introduced by SSE
2158 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2159 instructions by their now designated identifier (since combining i686
2160 and 3DNow! does not really imply 3DNow!A).
2162 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2164 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2165 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2167 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2168 Vineet Sharma <vineets@noida.hcltech.com>
2170 * maxq.h: New file: Disassembly information for the maxq port.
2172 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2174 * i386.h (i386_optab): Put back "movzb".
2176 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2178 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2179 comments. Remove member cris_ver_sim. Add members
2180 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2181 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2182 (struct cris_support_reg, struct cris_cond15): New types.
2183 (cris_conds15): Declare.
2184 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2185 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2186 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2187 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2188 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2189 SIZE_FIELD_UNSIGNED.
2191 2004-11-04 Jan Beulich <jbeulich@novell.com>
2193 * i386.h (sldx_Suf): Remove.
2194 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2195 (q_FP): Define, implying no REX64.
2196 (x_FP, sl_FP): Imply FloatMF.
2197 (i386_optab): Split reg and mem forms of moving from segment registers
2198 so that the memory forms can ignore the 16-/32-bit operand size
2199 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2200 all non-floating-point instructions. Unite 32- and 64-bit forms of
2201 movsx, movzx, and movd. Adjust floating point operations for the above
2202 changes to the *FP macros. Add DefaultSize to floating point control
2203 insns operating on larger memory ranges. Remove left over comments
2204 hinting at certain insns being Intel-syntax ones where the ones
2205 actually meant are already gone.
2207 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2209 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2212 2004-09-30 Paul Brook <paul@codesourcery.com>
2214 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2215 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2217 2004-09-11 Theodore A. Roth <troth@openavr.org>
2219 * avr.h: Add support for
2220 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2222 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2224 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2226 2004-08-24 Dmitry Diky <diwil@spec.ru>
2228 * msp430.h (msp430_opc): Add new instructions.
2229 (msp430_rcodes): Declare new instructions.
2230 (msp430_hcodes): Likewise..
2232 2004-08-13 Nick Clifton <nickc@redhat.com>
2235 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2238 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2240 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2242 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2244 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2246 2004-07-21 Jan Beulich <jbeulich@novell.com>
2248 * i386.h: Adjust instruction descriptions to better match the
2251 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2253 * arm.h: Remove all old content. Replace with architecture defines
2254 from gas/config/tc-arm.c.
2256 2004-07-09 Andreas Schwab <schwab@suse.de>
2258 * m68k.h: Fix comment.
2260 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2264 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2266 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2268 2004-05-24 Peter Barada <peter@the-baradas.com>
2270 * m68k.h: Add 'size' to m68k_opcode.
2272 2004-05-05 Peter Barada <peter@the-baradas.com>
2274 * m68k.h: Switch from ColdFire chip name to core variant.
2276 2004-04-22 Peter Barada <peter@the-baradas.com>
2278 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2279 descriptions for new EMAC cases.
2280 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2281 handle Motorola MAC syntax.
2282 Allow disassembly of ColdFire V4e object files.
2284 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2286 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2288 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2290 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2292 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2294 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2296 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2298 * i386.h (i386_optab): Added xstore/xcrypt insns.
2300 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2302 * h8300.h (32bit ldc/stc): Add relaxing support.
2304 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2306 * h8300.h (BITOP): Pass MEMRELAX flag.
2308 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2310 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2313 For older changes see ChangeLog-9103
2315 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2317 Copying and distribution of this file, with or without modification,
2318 are permitted in any medium without royalty provided the copyright
2319 notice and this notice are preserved.
2325 version-control: never
projects / deliverable / binutils-gdb.git / blob