include/opcode/ChangeLog

   1 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
   2
   3         * tic6x-control-registers.h, tic6x-insn-formats.h,
   4         tic6x-opcode-table.h, tic6x.h: New.
   5
   6 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
   7
   8         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
   9
  10 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
  11
  12         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
  13
  14 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
  15
  16         * ia64.h (ia64_find_opcode): Remove argument name.
  17         (ia64_find_next_opcode): Likewise.
  18         (ia64_dis_opcode): Likewise.
  19         (ia64_free_opcode): Likewise.
  20         (ia64_find_dependency): Likewise.
  21
  22 2009-11-22  Doug Evans  <dje@sebabeach.org>
  23
  24         * cgen.h: Include bfd_stdint.h.
  25         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
  26
  27 2009-11-18  Paul Brook  <paul@codesourcery.com>
  28
  29         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
  30
  31 2009-11-17  Paul Brook  <paul@codesourcery.com>
  32         Daniel Jacobowitz  <dan@codesourcery.com>
  33
  34         * arm.h (ARM_EXT_V6_DSP): Define.
  35         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
  36         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
  37
  38 2009-11-04  DJ Delorie  <dj@redhat.com>
  39
  40         * rx.h (rx_decode_opcode) (mvtipl): Add.
  41         (mvtcp, mvfcp, opecp): Remove.
  42
  43 2009-11-02  Paul Brook  <paul@codesourcery.com>
  44
  45         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
  46         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
  47         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
  48         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
  49         FPU_ARCH_NEON_VFP_V4): Define.
  50
  51 2009-10-23  Doug Evans  <dje@sebabeach.org>
  52
  53         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
  54         * cgen.h: Update.  Improve multi-inclusion macro name.
  55
  56 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
  57
  58         * ppc.h (PPC_OPCODE_476): Define.
  59
  60 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
  61
  62         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
  63
  64 2009-09-29  DJ Delorie  <dj@redhat.com>
  65
  66         * rx.h: New file.
  67
  68 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  69
  70         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  71
  72 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  73
  74         * ppc.h (PPC_OPCODE_PPCA2): New.
  75
  76 2009-09-05  Martin Thuresson  <martin@mtme.org>
  77
  78         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  79
  80 2009-08-29  Martin Thuresson  <martin@mtme.org>
  81
  82         * tic30.h (template): Rename type template to
  83         insn_template. Updated code to use new name.
  84         * tic54x.h (template): Rename type template to
  85         insn_template.
  86
  87 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  88
  89         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  90
  91 2009-06-11  Anthony Green  <green@moxielogic.com>
  92
  93         * moxie.h (MOXIE_F3_PCREL): Define.
  94         (moxie_form3_opc_info): Grow.
  95
  96 2009-06-06  Anthony Green  <green@moxielogic.com>
  97
  98         * moxie.h (MOXIE_F1_M): Define.
  99
 100 2009-04-15  Anthony Green  <green@moxielogic.com>
 101
 102         * moxie.h: Created.
 103
 104 2009-04-06  DJ Delorie  <dj@redhat.com>
 105
 106         * h8300.h: Add relaxation attributes to MOVA opcodes.
 107
 108 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 109
 110         * ppc.h (ppc_parse_cpu): Declare.
 111
 112 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 113
 114         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 115         and _IMM11 for mbitclr and mbitset.
 116         * score-datadep.h: Update dependency information.
 117
 118 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 119
 120         * ppc.h (PPC_OPCODE_POWER7): New.
 121
 122 2009-02-06  Doug Evans  <dje@google.com>
 123
 124         * i386.h: Add comment regarding sse* insns and prefixes.
 125
 126 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 127
 128         * mips.h (INSN_XLR): Define.
 129         (INSN_CHIP_MASK): Update.
 130         (CPU_XLR): Define.
 131         (OPCODE_IS_MEMBER): Update.
 132         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 133
 134 2009-01-28  Doug Evans  <dje@google.com>
 135
 136         * opcode/i386.h: Add multiple inclusion protection.
 137         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 138         (EDI_REG_NUM): New macros.
 139         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 140         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 141         (REX_PREFIX_P): New macro.
 142
 143 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 144
 145         * ppc.h (struct powerpc_opcode): New field "deprecated".
 146         (PPC_OPCODE_NOPOWER4): Delete.
 147
 148 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 149
 150         * mips.h: Define CPU_R14000, CPU_R16000.
 151         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 152
 153 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 154
 155         * arm.h (FPU_NEON_FP16): New.
 156         (FPU_ARCH_NEON_FP16): New.
 157
 158 2008-11-06  Chao-ying Fu  <fu@mips.com>
 159
 160         * mips.h: Doucument '1' for 5-bit sync type.
 161
 162 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 165         IA64_RS_CR.
 166
 167 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 168
 169         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 170
 171 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 172
 173         * ppc.h (PPC_OPCODE_405): Define.
 174         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 175
 176 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 177
 178         * ppc.h (ppc_cpu_t): New typedef.
 179         (struct powerpc_opcode <flags>): Use it.
 180         (struct powerpc_operand <insert, extract>): Likewise.
 181         (struct powerpc_macro <flags>): Likewise.
 182
 183 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 184
 185         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 186         Update comment before MIPS16 field descriptors to mention MIPS16.
 187         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 188         BBIT.
 189         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 190         New bit masks and shift counts for cins and exts.
 191
 192         * mips.h: Document new field descriptors +Q.
 193         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 194
 195 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 196
 197         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 198         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 199
 200 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 201
 202         * ppc.h: (PPC_OPCODE_E500MC): New.
 203
 204 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 205
 206         * i386.h (MAX_OPERANDS): Set to 5.
 207         (MAX_MNEM_SIZE): Changed to 20.
 208
 209 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 210
 211         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 212
 213 2008-03-09  Paul Brook  <paul@codesourcery.com>
 214
 215         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 216
 217 2008-03-04  Paul Brook  <paul@codesourcery.com>
 218
 219         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 220         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 221         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 222
 223 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 224             Nick Clifton  <nickc@redhat.com>
 225
 226         PR 3134
 227         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 228         with a 32-bit displacement but without the top bit of the 4th byte
 229         set.
 230
 231 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 232
 233         * cr16.h (cr16_num_optab): Declared.
 234
 235 2008-02-14  Hakan Ardo  <hakan@debian.org>
 236
 237         PR gas/2626
 238         * avr.h (AVR_ISA_2xxe): Define.
 239
 240 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 241
 242         * mips.h: Update copyright.
 243         (INSN_CHIP_MASK): New macro.
 244         (INSN_OCTEON): New macro.
 245         (CPU_OCTEON): New macro.
 246         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 247
 248 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 249
 250         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 251
 252 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 253
 254         * avr.h (AVR_ISA_USB162): Add new opcode set.
 255         (AVR_ISA_AVR3): Likewise.
 256
 257 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 258
 259         * mips.h (INSN_LOONGSON_2E): New.
 260         (INSN_LOONGSON_2F): New.
 261         (CPU_LOONGSON_2E): New.
 262         (CPU_LOONGSON_2F): New.
 263         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 264
 265 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 266
 267         * mips.h (INSN_ISA*): Redefine certain values as an
 268         enumeration.  Update comments.
 269         (mips_isa_table): New.
 270         (ISA_MIPS*): Redefine to match enumeration.
 271         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 272         values.
 273
 274 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 275
 276         * ppc.h (PPC_OPCODE_PPCPS): New.
 277
 278 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 279
 280         * m68k.h: Document j K & E.
 281
 282 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 283
 284         * cr16.h: New file for CR16 target.
 285
 286 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 287
 288         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 289
 290 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 291
 292         * m68k.h (mcfisa_c): New.
 293         (mcfusp, mcf_mask): Adjust.
 294
 295 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 296
 297         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 298         (num_powerpc_operands): Declare.
 299         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 300         (PPC_OPERAND_PLUS1): Define.
 301
 302 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386.h (REX_MODE64): Renamed to ...
 305         (REX_W): This.
 306         (REX_EXTX): Renamed to ...
 307         (REX_R): This.
 308         (REX_EXTY): Renamed to ...
 309         (REX_X): This.
 310         (REX_EXTZ): Renamed to ...
 311         (REX_B): This.
 312
 313 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * i386.h: Add entries from config/tc-i386.h and move tables
 316         to opcodes/i386-opc.h.
 317
 318 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386.h (FloatDR): Removed.
 321         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 322
 323 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 324
 325         * spu-insns.h: Add soma double-float insns.
 326
 327 2007-02-20  Thiemo Seufer  <ths@mips.com>
 328             Chao-Ying Fu  <fu@mips.com>
 329
 330         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 331         (INSN_DSPR2): Add flag for DSP R2 instructions.
 332         (M_BALIGN): New macro.
 333
 334 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 335
 336         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 337         and Seg3ShortFrom with Shortform.
 338
 339 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 340
 341         PR gas/4027
 342         * i386.h (i386_optab): Put the real "test" before the pseudo
 343         one.
 344
 345 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 346
 347         * m68k.h (m68010up): OR fido_a.
 348
 349 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 350
 351         * m68k.h (fido_a): New.
 352
 353 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 354
 355         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 356         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 357         values.
 358
 359 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 360
 361         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 362
 363 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 364
 365         * score-inst.h (enum score_insn_type): Add Insn_internal.
 366
 367 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 368             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 369             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 370             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 371             Alan Modra  <amodra@bigpond.net.au>
 372
 373         * spu-insns.h: New file.
 374         * spu.h: New file.
 375
 376 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 377
 378         * ppc.h (PPC_OPCODE_CELL): Define.
 379
 380 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 381
 382         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 383         in amdfam10 architecture.
 384
 385 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         * i386.h: Replace CpuMNI with CpuSSSE3.
 388
 389 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 390             Joseph Myers  <joseph@codesourcery.com>
 391             Ian Lance Taylor  <ian@wasabisystems.com>
 392             Ben Elliston  <bje@wasabisystems.com>
 393
 394         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 395
 396 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 397
 398         * score-datadep.h: New file.
 399         * score-inst.h: New file.
 400
 401 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 404         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 405         movdq2q and movq2dq.
 406
 407 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 408            Michael Meissner             <michael.meissner@amd.com>
 409
 410         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 411
 412 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386.h (i386_optab): Add "nop" with memory reference.
 415
 416 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 417
 418         * i386.h (i386_optab): Update comment for 64bit NOP.
 419
 420 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 421             Anton Blanchard  <anton@samba.org>
 422
 423         * ppc.h (PPC_OPCODE_POWER6): Define.
 424         Adjust whitespace.
 425
 426 2006-06-05  Thiemo Seufer  <ths@mips.com>
 427
 428         * mips.h: Improve description of MT flags.
 429
 430 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 431
 432         * m68k.h (mcf_mask): Define.
 433
 434 2006-05-05  Thiemo Seufer  <ths@mips.com>
 435             David Ung  <davidu@mips.com>
 436
 437         * mips.h (enum): Add macro M_CACHE_AB.
 438
 439 2006-05-04  Thiemo Seufer  <ths@mips.com>
 440             Nigel Stephens  <nigel@mips.com>
 441             David Ung  <davidu@mips.com>
 442
 443         * mips.h: Add INSN_SMARTMIPS define.
 444
 445 2006-04-30  Thiemo Seufer  <ths@mips.com>
 446             David Ung  <davidu@mips.com>
 447
 448         * mips.h: Defines udi bits and masks.  Add description of
 449         characters which may appear in the args field of udi
 450         instructions.
 451
 452 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 453
 454         * mips.h: Improve comments describing the bitfield instruction
 455         fields.
 456
 457 2006-04-26  Julian Brown  <julian@codesourcery.com>
 458
 459         * arm.h (FPU_VFP_EXT_V3): Define constant.
 460         (FPU_NEON_EXT_V1): Likewise.
 461         (FPU_VFP_HARD): Update.
 462         (FPU_VFP_V3): Define macro.
 463         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 464
 465 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 466
 467         * avr.h (AVR_ISA_PWMx): New.
 468
 469 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 470
 471         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 472         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 473         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 474         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 475         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 476
 477 2006-03-10  Paul Brook  <paul@codesourcery.com>
 478
 479         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 480
 481 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 482
 483         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 484         first.  Correct mask of bb "B" opcode.
 485
 486 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 487
 488         * i386.h (i386_optab): Support Intel Merom New Instructions.
 489
 490 2006-02-24  Paul Brook  <paul@codesourcery.com>
 491
 492         * arm.h: Add V7 feature bits.
 493
 494 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 497
 498 2006-01-31  Paul Brook  <paul@codesourcery.com>
 499         Richard Earnshaw <rearnsha@arm.com>
 500
 501         * arm.h: Use ARM_CPU_FEATURE.
 502         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 503         (arm_feature_set): Change to a structure.
 504         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 505         ARM_FEATURE): New macros.
 506
 507 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 508
 509         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 510         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 511         (ADD_PC_INCR_OPCODE): Don't define.
 512
 513 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         PR gas/1874
 516         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 517
 518 2005-11-14  David Ung  <davidu@mips.com>
 519
 520         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 521         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 522         save/restore encoding of the args field.
 523
 524 2005-10-28  Dave Brolley  <brolley@redhat.com>
 525
 526         Contribute the following changes:
 527         2005-02-16  Dave Brolley  <brolley@redhat.com>
 528
 529         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 530         cgen_isa_mask_* to cgen_bitset_*.
 531         * cgen.h: Likewise.
 532
 533         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 534
 535         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 536         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 537         (CGEN_CPU_TABLE): Make isas a ponter.
 538
 539         2003-09-29  Dave Brolley  <brolley@redhat.com>
 540
 541         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 542         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 543         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 544
 545         2002-12-13  Dave Brolley  <brolley@redhat.com>
 546
 547         * cgen.h (symcat.h): #include it.
 548         (cgen-bitset.h): #include it.
 549         (CGEN_ATTR_VALUE_TYPE): Now a union.
 550         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 551         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 552         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 553         * cgen-bitset.h: New file.
 554
 555 2005-09-30  Catherine Moore  <clm@cm00re.com>
 556
 557         * bfin.h: New file.
 558
 559 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 560
 561         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 562         indirect operands.
 563
 564 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 565
 566         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 567         Add FLAG_STRICT to pa10 ftest opcode.
 568
 569 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 570
 571         * hppa.h (pa_opcodes): Remove lha entries.
 572
 573 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 574
 575         * hppa.h (FLAG_STRICT): Revise comment.
 576         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 577         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 578         entries for "fdc".
 579
 580 2005-09-30  Catherine Moore  <clm@cm00re.com>
 581
 582         * bfin.h: New file.
 583
 584 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 585
 586         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 587
 588 2005-09-06  Chao-ying Fu  <fu@mips.com>
 589
 590         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 591         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 592         define.
 593         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 594         (INSN_ASE_MASK): Update to include INSN_MT.
 595         (INSN_MT): New define for MT ASE.
 596
 597 2005-08-25  Chao-ying Fu  <fu@mips.com>
 598
 599         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 600         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 601         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 602         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 603         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 604         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 605         instructions.
 606         (INSN_DSP): New define for DSP ASE.
 607
 608 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 609
 610         * a29k.h: Delete.
 611
 612 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 613
 614         * ppc.h (PPC_OPCODE_E300): Define.
 615
 616 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 617
 618         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 619
 620 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 621
 622         PR gas/336
 623         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 624         and pitlb.
 625
 626 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 627
 628         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 629         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 630         Add movq-s as 64-bit variants of movd-s.
 631
 632 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 633
 634         * hppa.h: Fix punctuation in comment.
 635
 636         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 637         implicit space-register addressing.  Set space-register bits on opcodes
 638         using implicit space-register addressing.  Add various missing pa20
 639         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 640         space-register addressing.  Use "fE" instead of "fe" in various
 641         fstw opcodes.
 642
 643 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 644
 645         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 646
 647 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 648
 649         * i386.h (i386_optab): Support Intel VMX Instructions.
 650
 651 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 652
 653         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 654
 655 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 656
 657         * i386.h (i386_optab): Add new insns.
 658
 659 2005-07-01  Nick Clifton  <nickc@redhat.com>
 660
 661         * sparc.h: Add typedefs to structure declarations.
 662
 663 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 664
 665         PR 1013
 666         * i386.h (i386_optab): Update comments for 64bit addressing on
 667         mov. Allow 64bit addressing for mov and movq.
 668
 669 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 670
 671         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 672         respectively, in various floating-point load and store patterns.
 673
 674 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 675
 676         * hppa.h (FLAG_STRICT): Correct comment.
 677         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 678         PA 2.0 mneumonics when equivalent.  Entries with cache control
 679         completers now require PA 1.1.  Adjust whitespace.
 680
 681 2005-05-19  Anton Blanchard  <anton@samba.org>
 682
 683         * ppc.h (PPC_OPCODE_POWER5): Define.
 684
 685 2005-05-10  Nick Clifton  <nickc@redhat.com>
 686
 687         * Update the address and phone number of the FSF organization in
 688         the GPL notices in the following files:
 689         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 690         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 691         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 692         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 693         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 694         tic54x.h, tic80.h, v850.h, vax.h
 695
 696 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 697
 698         * i386.h (i386_optab): Add ht and hnt.
 699
 700 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 701
 702         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 703         Add xcrypt-ctr.  Provide aliases without hyphens.
 704
 705 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 706
 707         Moved from ../ChangeLog
 708
 709         2005-04-12  Paul Brook  <paul@codesourcery.com>
 710         * m88k.h: Rename psr macros to avoid conflicts.
 711
 712         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 713         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 714         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 715         and ARM_ARCH_V6ZKT2.
 716
 717         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 718         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 719         Remove redundant instruction types.
 720         (struct argument): X_op - new field.
 721         (struct cst4_entry): Remove.
 722         (no_op_insn): Declare.
 723
 724         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 725         * crx.h (enum argtype): Rename types, remove unused types.
 726
 727         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 728         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 729         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 730         (enum operand_type): Rearrange operands, edit comments.
 731         replace us<N> with ui<N> for unsigned immediate.
 732         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 733         displacements (respectively).
 734         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 735         (instruction type): Add NO_TYPE_INS.
 736         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 737         (operand_entry): New field - 'flags'.
 738         (operand flags): New.
 739
 740         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 741         * crx.h (operand_type): Remove redundant types i3, i4,
 742         i5, i8, i12.
 743         Add new unsigned immediate types us3, us4, us5, us16.
 744
 745 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 746
 747         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 748         adjust them accordingly.
 749
 750 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 751
 752         * i386.h (i386_optab): Add rdtscp.
 753
 754 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 755
 756         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 757         between memory and segment register. Allow movq for moving between
 758         general-purpose register and segment register.
 759
 760 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 761
 762         PR gas/707
 763         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 764         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 765         fnstsw.
 766
 767 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 768
 769         * m68k.h (m68008, m68ec030, m68882): Remove.
 770         (m68k_mask): New.
 771         (cpu_m68k, cpu_cf): New.
 772         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 773         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 774
 775 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 776
 777         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 778         * cgen.h (enum cgen_parse_operand_type): Add
 779         CGEN_PARSE_OPERAND_SYMBOLIC.
 780
 781 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 782
 783         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 784         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 785         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 786
 787 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 788
 789         * mips.h (struct mips_opcode): Add new pinfo2 member.
 790         (INSN_ALIAS): New define for opcode table entries that are
 791         specific instances of another entry, such as 'move' for an 'or'
 792         with a zero operand.
 793         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 794         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 795
 796 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 797
 798         * mips.h (CPU_RM9000): Define.
 799         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 800
 801 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 802
 803         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 804         to/from test registers are illegal in 64-bit mode. Add missing
 805         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 806         (previously one had to explicitly encode a rex64 prefix). Re-enable
 807         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 808         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 809
 810 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 811
 812         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 813         available only with SSE2. Change the MMX additions introduced by SSE
 814         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 815         instructions by their now designated identifier (since combining i686
 816         and 3DNow! does not really imply 3DNow!A).
 817
 818 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 819
 820         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 821         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 822
 823 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 824             Vineet Sharma      <vineets@noida.hcltech.com>
 825
 826         * maxq.h: New file: Disassembly information for the maxq port.
 827
 828 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 829
 830         * i386.h (i386_optab): Put back "movzb".
 831
 832 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 833
 834         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 835         comments.  Remove member cris_ver_sim.  Add members
 836         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 837         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 838         (struct cris_support_reg, struct cris_cond15): New types.
 839         (cris_conds15): Declare.
 840         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 841         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 842         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 843         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 844         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 845         SIZE_FIELD_UNSIGNED.
 846
 847 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 848
 849         * i386.h (sldx_Suf): Remove.
 850         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 851         (q_FP): Define, implying no REX64.
 852         (x_FP, sl_FP): Imply FloatMF.
 853         (i386_optab): Split reg and mem forms of moving from segment registers
 854         so that the memory forms can ignore the 16-/32-bit operand size
 855         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 856         all non-floating-point instructions. Unite 32- and 64-bit forms of
 857         movsx, movzx, and movd. Adjust floating point operations for the above
 858         changes to the *FP macros. Add DefaultSize to floating point control
 859         insns operating on larger memory ranges. Remove left over comments
 860         hinting at certain insns being Intel-syntax ones where the ones
 861         actually meant are already gone.
 862
 863 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 864
 865         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 866         instruction type.
 867
 868 2004-09-30  Paul Brook  <paul@codesourcery.com>
 869
 870         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 871         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 872
 873 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 874
 875         * avr.h: Add support for
 876         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 877
 878 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 879
 880         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 881
 882 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 883
 884         * msp430.h (msp430_opc): Add new instructions.
 885         (msp430_rcodes): Declare new instructions.
 886         (msp430_hcodes): Likewise..
 887
 888 2004-08-13  Nick Clifton  <nickc@redhat.com>
 889
 890         PR/301
 891         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 892         processors.
 893
 894 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 895
 896         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 897
 898 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 901
 902 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 903
 904         * i386.h: Adjust instruction descriptions to better match the
 905         specification.
 906
 907 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 908
 909         * arm.h: Remove all old content.  Replace with architecture defines
 910         from gas/config/tc-arm.c.
 911
 912 2004-07-09  Andreas Schwab  <schwab@suse.de>
 913
 914         * m68k.h: Fix comment.
 915
 916 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 917
 918         * crx.h: New file.
 919
 920 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 921
 922         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 923
 924 2004-05-24  Peter Barada  <peter@the-baradas.com>
 925
 926         * m68k.h: Add 'size' to m68k_opcode.
 927
 928 2004-05-05  Peter Barada  <peter@the-baradas.com>
 929
 930         * m68k.h: Switch from ColdFire chip name to core variant.
 931
 932 2004-04-22  Peter Barada  <peter@the-baradas.com>
 933
 934         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 935         descriptions for new EMAC cases.
 936         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 937         handle Motorola MAC syntax.
 938         Allow disassembly of ColdFire V4e object files.
 939
 940 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 941
 942         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 943
 944 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 945
 946         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 947
 948 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 949
 950         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 951
 952 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 953
 954         * i386.h (i386_optab): Added xstore/xcrypt insns.
 955
 956 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 957
 958         * h8300.h (32bit ldc/stc): Add relaxing support.
 959
 960 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 961
 962         * h8300.h (BITOP): Pass MEMRELAX flag.
 963
 964 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 965
 966         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 967         except for the H8S.
 968
 969 For older changes see ChangeLog-9103
 970 \f
 971 Local Variables:
 972 mode: change-log
 973 left-margin: 8
 974 fill-column: 74
 975 version-control: never
 976 End: