1 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips.h: Fix previous commit.
5 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
7 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
8 (INSN_LOONGSON_3A): Clear bit 31.
10 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
13 * arm.h (ARM_AEXT_V6M_ONLY): New define.
14 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
15 (ARM_ARCH_V6M_ONLY): New define.
17 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
19 * mips.h (INSN_LOONGSON_3A): Defined.
20 (CPU_LOONGSON_3A): Defined.
21 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
23 2010-10-09 Matt Rice <ratmice@gmail.com>
25 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
26 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
28 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
30 * arm.h (ARM_EXT_VIRT): New define.
31 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
32 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
35 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
37 * arm.h (ARM_AEXT_ADIV): New define.
38 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
40 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
42 * arm.h (ARM_EXT_OS): New define.
43 (ARM_AEXT_V6SM): Likewise.
44 (ARM_ARCH_V6SM): Likewise.
46 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
48 * arm.h (ARM_EXT_MP): Add.
49 (ARM_ARCH_V7A_MP): Likewise.
51 2010-09-22 Mike Frysinger <vapier@gentoo.org>
53 * bfin.h: Declare pseudoChr structs/defines.
55 2010-09-21 Mike Frysinger <vapier@gentoo.org>
57 * bfin.h: Strip trailing whitespace.
59 2010-07-29 DJ Delorie <dj@redhat.com>
61 * rx.h (RX_Operand_Type): Add TwoReg.
62 (RX_Opcode_ID): Remove ediv and ediv2.
64 2010-07-27 DJ Delorie <dj@redhat.com>
66 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
68 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
69 Ina Pandit <ina.pandit@kpitcummins.com>
71 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
72 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
74 Remove PROCESSOR_V850EA support.
75 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
76 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
77 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
78 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
79 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
81 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
83 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
86 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
88 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
89 (MIPS16_INSN_BRANCH): Rename to...
90 (MIPS16_INSN_COND_BRANCH): ... this.
92 2010-07-03 Alan Modra <amodra@gmail.com>
94 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
95 Renumber other PPC_OPCODE defines.
97 2010-07-03 Alan Modra <amodra@gmail.com>
99 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
101 2010-06-29 Alan Modra <amodra@gmail.com>
103 * maxq.h: Delete file.
105 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
107 * ppc.h (PPC_OPCODE_E500): Define.
109 2010-05-26 Catherine Moore <clm@codesourcery.com>
111 * opcode/mips.h (INSN_MIPS16): Remove.
113 2010-04-21 Joseph Myers <joseph@codesourcery.com>
115 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
117 2010-04-15 Nick Clifton <nickc@redhat.com>
119 * alpha.h: Update copyright notice to use GPLv3.
125 * convex.h: Likewise.
139 * m68hc11.h: Likewise.
145 * mn10200.h: Likewise.
146 * mn10300.h: Likewise.
147 * msp430.h: Likewise.
158 * score-datadep.h: Likewise.
159 * score-inst.h: Likewise.
161 * spu-insns.h: Likewise.
165 * tic54x.h: Likewise.
170 2010-03-25 Joseph Myers <joseph@codesourcery.com>
172 * tic6x-control-registers.h, tic6x-insn-formats.h,
173 tic6x-opcode-table.h, tic6x.h: New.
175 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
177 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
179 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
181 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
183 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
185 * ia64.h (ia64_find_opcode): Remove argument name.
186 (ia64_find_next_opcode): Likewise.
187 (ia64_dis_opcode): Likewise.
188 (ia64_free_opcode): Likewise.
189 (ia64_find_dependency): Likewise.
191 2009-11-22 Doug Evans <dje@sebabeach.org>
193 * cgen.h: Include bfd_stdint.h.
194 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
196 2009-11-18 Paul Brook <paul@codesourcery.com>
198 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
200 2009-11-17 Paul Brook <paul@codesourcery.com>
201 Daniel Jacobowitz <dan@codesourcery.com>
203 * arm.h (ARM_EXT_V6_DSP): Define.
204 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
205 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
207 2009-11-04 DJ Delorie <dj@redhat.com>
209 * rx.h (rx_decode_opcode) (mvtipl): Add.
210 (mvtcp, mvfcp, opecp): Remove.
212 2009-11-02 Paul Brook <paul@codesourcery.com>
214 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
215 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
216 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
217 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
218 FPU_ARCH_NEON_VFP_V4): Define.
220 2009-10-23 Doug Evans <dje@sebabeach.org>
222 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
223 * cgen.h: Update. Improve multi-inclusion macro name.
225 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
227 * ppc.h (PPC_OPCODE_476): Define.
229 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
231 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
233 2009-09-29 DJ Delorie <dj@redhat.com>
237 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
239 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
241 2009-09-21 Ben Elliston <bje@au.ibm.com>
243 * ppc.h (PPC_OPCODE_PPCA2): New.
245 2009-09-05 Martin Thuresson <martin@mtme.org>
247 * ia64.h (struct ia64_operand): Renamed member class to op_class.
249 2009-08-29 Martin Thuresson <martin@mtme.org>
251 * tic30.h (template): Rename type template to
252 insn_template. Updated code to use new name.
253 * tic54x.h (template): Rename type template to
256 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
258 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
260 2009-06-11 Anthony Green <green@moxielogic.com>
262 * moxie.h (MOXIE_F3_PCREL): Define.
263 (moxie_form3_opc_info): Grow.
265 2009-06-06 Anthony Green <green@moxielogic.com>
267 * moxie.h (MOXIE_F1_M): Define.
269 2009-04-15 Anthony Green <green@moxielogic.com>
273 2009-04-06 DJ Delorie <dj@redhat.com>
275 * h8300.h: Add relaxation attributes to MOVA opcodes.
277 2009-03-10 Alan Modra <amodra@bigpond.net.au>
279 * ppc.h (ppc_parse_cpu): Declare.
281 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
283 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
284 and _IMM11 for mbitclr and mbitset.
285 * score-datadep.h: Update dependency information.
287 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
289 * ppc.h (PPC_OPCODE_POWER7): New.
291 2009-02-06 Doug Evans <dje@google.com>
293 * i386.h: Add comment regarding sse* insns and prefixes.
295 2009-02-03 Sandip Matte <sandip@rmicorp.com>
297 * mips.h (INSN_XLR): Define.
298 (INSN_CHIP_MASK): Update.
300 (OPCODE_IS_MEMBER): Update.
301 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
303 2009-01-28 Doug Evans <dje@google.com>
305 * opcode/i386.h: Add multiple inclusion protection.
306 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
307 (EDI_REG_NUM): New macros.
308 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
309 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
310 (REX_PREFIX_P): New macro.
312 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
314 * ppc.h (struct powerpc_opcode): New field "deprecated".
315 (PPC_OPCODE_NOPOWER4): Delete.
317 2008-11-28 Joshua Kinard <kumba@gentoo.org>
319 * mips.h: Define CPU_R14000, CPU_R16000.
320 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
322 2008-11-18 Catherine Moore <clm@codesourcery.com>
324 * arm.h (FPU_NEON_FP16): New.
325 (FPU_ARCH_NEON_FP16): New.
327 2008-11-06 Chao-ying Fu <fu@mips.com>
329 * mips.h: Doucument '1' for 5-bit sync type.
331 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
333 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
336 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
338 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
340 2008-07-30 Michael J. Eager <eager@eagercon.com>
342 * ppc.h (PPC_OPCODE_405): Define.
343 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
345 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
347 * ppc.h (ppc_cpu_t): New typedef.
348 (struct powerpc_opcode <flags>): Use it.
349 (struct powerpc_operand <insert, extract>): Likewise.
350 (struct powerpc_macro <flags>): Likewise.
352 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
354 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
355 Update comment before MIPS16 field descriptors to mention MIPS16.
356 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
358 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
359 New bit masks and shift counts for cins and exts.
361 * mips.h: Document new field descriptors +Q.
362 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
364 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
366 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
367 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
369 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
371 * ppc.h: (PPC_OPCODE_E500MC): New.
373 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
375 * i386.h (MAX_OPERANDS): Set to 5.
376 (MAX_MNEM_SIZE): Changed to 20.
378 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
380 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
382 2008-03-09 Paul Brook <paul@codesourcery.com>
384 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
386 2008-03-04 Paul Brook <paul@codesourcery.com>
388 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
389 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
390 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
392 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
393 Nick Clifton <nickc@redhat.com>
396 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
397 with a 32-bit displacement but without the top bit of the 4th byte
400 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
402 * cr16.h (cr16_num_optab): Declared.
404 2008-02-14 Hakan Ardo <hakan@debian.org>
407 * avr.h (AVR_ISA_2xxe): Define.
409 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
411 * mips.h: Update copyright.
412 (INSN_CHIP_MASK): New macro.
413 (INSN_OCTEON): New macro.
414 (CPU_OCTEON): New macro.
415 (OPCODE_IS_MEMBER): Handle Octeon instructions.
417 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
419 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
421 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
423 * avr.h (AVR_ISA_USB162): Add new opcode set.
424 (AVR_ISA_AVR3): Likewise.
426 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
428 * mips.h (INSN_LOONGSON_2E): New.
429 (INSN_LOONGSON_2F): New.
430 (CPU_LOONGSON_2E): New.
431 (CPU_LOONGSON_2F): New.
432 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
434 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
436 * mips.h (INSN_ISA*): Redefine certain values as an
437 enumeration. Update comments.
438 (mips_isa_table): New.
439 (ISA_MIPS*): Redefine to match enumeration.
440 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
443 2007-08-08 Ben Elliston <bje@au.ibm.com>
445 * ppc.h (PPC_OPCODE_PPCPS): New.
447 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
449 * m68k.h: Document j K & E.
451 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
453 * cr16.h: New file for CR16 target.
455 2007-05-02 Alan Modra <amodra@bigpond.net.au>
457 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
459 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
461 * m68k.h (mcfisa_c): New.
462 (mcfusp, mcf_mask): Adjust.
464 2007-04-20 Alan Modra <amodra@bigpond.net.au>
466 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
467 (num_powerpc_operands): Declare.
468 (PPC_OPERAND_SIGNED et al): Redefine as hex.
469 (PPC_OPERAND_PLUS1): Define.
471 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
473 * i386.h (REX_MODE64): Renamed to ...
475 (REX_EXTX): Renamed to ...
477 (REX_EXTY): Renamed to ...
479 (REX_EXTZ): Renamed to ...
482 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
484 * i386.h: Add entries from config/tc-i386.h and move tables
485 to opcodes/i386-opc.h.
487 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
489 * i386.h (FloatDR): Removed.
490 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
492 2007-03-01 Alan Modra <amodra@bigpond.net.au>
494 * spu-insns.h: Add soma double-float insns.
496 2007-02-20 Thiemo Seufer <ths@mips.com>
497 Chao-Ying Fu <fu@mips.com>
499 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
500 (INSN_DSPR2): Add flag for DSP R2 instructions.
501 (M_BALIGN): New macro.
503 2007-02-14 Alan Modra <amodra@bigpond.net.au>
505 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
506 and Seg3ShortFrom with Shortform.
508 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
511 * i386.h (i386_optab): Put the real "test" before the pseudo
514 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
516 * m68k.h (m68010up): OR fido_a.
518 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
520 * m68k.h (fido_a): New.
522 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
524 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
525 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
528 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
530 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
532 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
534 * score-inst.h (enum score_insn_type): Add Insn_internal.
536 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
537 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
538 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
539 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
540 Alan Modra <amodra@bigpond.net.au>
542 * spu-insns.h: New file.
545 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
547 * ppc.h (PPC_OPCODE_CELL): Define.
549 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
551 * i386.h : Modify opcode to support for the change in POPCNT opcode
552 in amdfam10 architecture.
554 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
556 * i386.h: Replace CpuMNI with CpuSSSE3.
558 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
559 Joseph Myers <joseph@codesourcery.com>
560 Ian Lance Taylor <ian@wasabisystems.com>
561 Ben Elliston <bje@wasabisystems.com>
563 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
565 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
567 * score-datadep.h: New file.
568 * score-inst.h: New file.
570 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
572 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
573 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
576 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
577 Michael Meissner <michael.meissner@amd.com>
579 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
581 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
583 * i386.h (i386_optab): Add "nop" with memory reference.
585 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
587 * i386.h (i386_optab): Update comment for 64bit NOP.
589 2006-06-06 Ben Elliston <bje@au.ibm.com>
590 Anton Blanchard <anton@samba.org>
592 * ppc.h (PPC_OPCODE_POWER6): Define.
595 2006-06-05 Thiemo Seufer <ths@mips.com>
597 * mips.h: Improve description of MT flags.
599 2006-05-25 Richard Sandiford <richard@codesourcery.com>
601 * m68k.h (mcf_mask): Define.
603 2006-05-05 Thiemo Seufer <ths@mips.com>
604 David Ung <davidu@mips.com>
606 * mips.h (enum): Add macro M_CACHE_AB.
608 2006-05-04 Thiemo Seufer <ths@mips.com>
609 Nigel Stephens <nigel@mips.com>
610 David Ung <davidu@mips.com>
612 * mips.h: Add INSN_SMARTMIPS define.
614 2006-04-30 Thiemo Seufer <ths@mips.com>
615 David Ung <davidu@mips.com>
617 * mips.h: Defines udi bits and masks. Add description of
618 characters which may appear in the args field of udi
621 2006-04-26 Thiemo Seufer <ths@networkno.de>
623 * mips.h: Improve comments describing the bitfield instruction
626 2006-04-26 Julian Brown <julian@codesourcery.com>
628 * arm.h (FPU_VFP_EXT_V3): Define constant.
629 (FPU_NEON_EXT_V1): Likewise.
630 (FPU_VFP_HARD): Update.
631 (FPU_VFP_V3): Define macro.
632 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
634 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
636 * avr.h (AVR_ISA_PWMx): New.
638 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
640 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
641 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
642 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
643 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
644 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
646 2006-03-10 Paul Brook <paul@codesourcery.com>
648 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
650 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
652 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
653 first. Correct mask of bb "B" opcode.
655 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
657 * i386.h (i386_optab): Support Intel Merom New Instructions.
659 2006-02-24 Paul Brook <paul@codesourcery.com>
661 * arm.h: Add V7 feature bits.
663 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
665 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
667 2006-01-31 Paul Brook <paul@codesourcery.com>
668 Richard Earnshaw <rearnsha@arm.com>
670 * arm.h: Use ARM_CPU_FEATURE.
671 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
672 (arm_feature_set): Change to a structure.
673 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
674 ARM_FEATURE): New macros.
676 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
678 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
679 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
680 (ADD_PC_INCR_OPCODE): Don't define.
682 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
685 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
687 2005-11-14 David Ung <davidu@mips.com>
689 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
690 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
691 save/restore encoding of the args field.
693 2005-10-28 Dave Brolley <brolley@redhat.com>
695 Contribute the following changes:
696 2005-02-16 Dave Brolley <brolley@redhat.com>
698 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
699 cgen_isa_mask_* to cgen_bitset_*.
702 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
704 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
705 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
706 (CGEN_CPU_TABLE): Make isas a ponter.
708 2003-09-29 Dave Brolley <brolley@redhat.com>
710 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
711 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
712 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
714 2002-12-13 Dave Brolley <brolley@redhat.com>
716 * cgen.h (symcat.h): #include it.
717 (cgen-bitset.h): #include it.
718 (CGEN_ATTR_VALUE_TYPE): Now a union.
719 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
720 (CGEN_ATTR_ENTRY): 'value' now unsigned.
721 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
722 * cgen-bitset.h: New file.
724 2005-09-30 Catherine Moore <clm@cm00re.com>
728 2005-10-24 Jan Beulich <jbeulich@novell.com>
730 * ia64.h (enum ia64_opnd): Move memory operand out of set of
733 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
735 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
736 Add FLAG_STRICT to pa10 ftest opcode.
738 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
740 * hppa.h (pa_opcodes): Remove lha entries.
742 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
744 * hppa.h (FLAG_STRICT): Revise comment.
745 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
746 before corresponding pa11 opcodes. Add strict pa10 register-immediate
749 2005-09-30 Catherine Moore <clm@cm00re.com>
753 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
755 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
757 2005-09-06 Chao-ying Fu <fu@mips.com>
759 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
760 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
762 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
763 (INSN_ASE_MASK): Update to include INSN_MT.
764 (INSN_MT): New define for MT ASE.
766 2005-08-25 Chao-ying Fu <fu@mips.com>
768 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
769 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
770 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
771 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
772 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
773 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
775 (INSN_DSP): New define for DSP ASE.
777 2005-08-18 Alan Modra <amodra@bigpond.net.au>
781 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
783 * ppc.h (PPC_OPCODE_E300): Define.
785 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
787 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
789 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
792 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
795 2005-07-27 Jan Beulich <jbeulich@novell.com>
797 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
798 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
799 Add movq-s as 64-bit variants of movd-s.
801 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
803 * hppa.h: Fix punctuation in comment.
805 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
806 implicit space-register addressing. Set space-register bits on opcodes
807 using implicit space-register addressing. Add various missing pa20
808 long-immediate opcodes. Remove various opcodes using implicit 3-bit
809 space-register addressing. Use "fE" instead of "fe" in various
812 2005-07-18 Jan Beulich <jbeulich@novell.com>
814 * i386.h (i386_optab): Operands of aam and aad are unsigned.
816 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
818 * i386.h (i386_optab): Support Intel VMX Instructions.
820 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
822 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
824 2005-07-05 Jan Beulich <jbeulich@novell.com>
826 * i386.h (i386_optab): Add new insns.
828 2005-07-01 Nick Clifton <nickc@redhat.com>
830 * sparc.h: Add typedefs to structure declarations.
832 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
835 * i386.h (i386_optab): Update comments for 64bit addressing on
836 mov. Allow 64bit addressing for mov and movq.
838 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
840 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
841 respectively, in various floating-point load and store patterns.
843 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
845 * hppa.h (FLAG_STRICT): Correct comment.
846 (pa_opcodes): Update load and store entries to allow both PA 1.X and
847 PA 2.0 mneumonics when equivalent. Entries with cache control
848 completers now require PA 1.1. Adjust whitespace.
850 2005-05-19 Anton Blanchard <anton@samba.org>
852 * ppc.h (PPC_OPCODE_POWER5): Define.
854 2005-05-10 Nick Clifton <nickc@redhat.com>
856 * Update the address and phone number of the FSF organization in
857 the GPL notices in the following files:
858 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
859 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
860 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
861 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
862 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
863 tic54x.h, tic80.h, v850.h, vax.h
865 2005-05-09 Jan Beulich <jbeulich@novell.com>
867 * i386.h (i386_optab): Add ht and hnt.
869 2005-04-18 Mark Kettenis <kettenis@gnu.org>
871 * i386.h: Insert hyphens into selected VIA PadLock extensions.
872 Add xcrypt-ctr. Provide aliases without hyphens.
874 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
876 Moved from ../ChangeLog
878 2005-04-12 Paul Brook <paul@codesourcery.com>
879 * m88k.h: Rename psr macros to avoid conflicts.
881 2005-03-12 Zack Weinberg <zack@codesourcery.com>
882 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
883 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
886 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
887 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
888 Remove redundant instruction types.
889 (struct argument): X_op - new field.
890 (struct cst4_entry): Remove.
891 (no_op_insn): Declare.
893 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
894 * crx.h (enum argtype): Rename types, remove unused types.
896 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
897 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
898 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
899 (enum operand_type): Rearrange operands, edit comments.
900 replace us<N> with ui<N> for unsigned immediate.
901 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
902 displacements (respectively).
903 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
904 (instruction type): Add NO_TYPE_INS.
905 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
906 (operand_entry): New field - 'flags'.
907 (operand flags): New.
909 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
910 * crx.h (operand_type): Remove redundant types i3, i4,
912 Add new unsigned immediate types us3, us4, us5, us16.
914 2005-04-12 Mark Kettenis <kettenis@gnu.org>
916 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
917 adjust them accordingly.
919 2005-04-01 Jan Beulich <jbeulich@novell.com>
921 * i386.h (i386_optab): Add rdtscp.
923 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
925 * i386.h (i386_optab): Don't allow the `l' suffix for moving
926 between memory and segment register. Allow movq for moving between
927 general-purpose register and segment register.
929 2005-02-09 Jan Beulich <jbeulich@novell.com>
932 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
933 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
936 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
938 * m68k.h (m68008, m68ec030, m68882): Remove.
940 (cpu_m68k, cpu_cf): New.
941 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
942 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
944 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
946 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
947 * cgen.h (enum cgen_parse_operand_type): Add
948 CGEN_PARSE_OPERAND_SYMBOLIC.
950 2005-01-21 Fred Fish <fnf@specifixinc.com>
952 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
953 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
954 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
956 2005-01-19 Fred Fish <fnf@specifixinc.com>
958 * mips.h (struct mips_opcode): Add new pinfo2 member.
959 (INSN_ALIAS): New define for opcode table entries that are
960 specific instances of another entry, such as 'move' for an 'or'
962 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
963 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
965 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
967 * mips.h (CPU_RM9000): Define.
968 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
970 2004-11-25 Jan Beulich <jbeulich@novell.com>
972 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
973 to/from test registers are illegal in 64-bit mode. Add missing
974 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
975 (previously one had to explicitly encode a rex64 prefix). Re-enable
976 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
977 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
979 2004-11-23 Jan Beulich <jbeulich@novell.com>
981 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
982 available only with SSE2. Change the MMX additions introduced by SSE
983 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
984 instructions by their now designated identifier (since combining i686
985 and 3DNow! does not really imply 3DNow!A).
987 2004-11-19 Alan Modra <amodra@bigpond.net.au>
989 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
990 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
992 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
993 Vineet Sharma <vineets@noida.hcltech.com>
995 * maxq.h: New file: Disassembly information for the maxq port.
997 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
999 * i386.h (i386_optab): Put back "movzb".
1001 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1003 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1004 comments. Remove member cris_ver_sim. Add members
1005 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1006 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1007 (struct cris_support_reg, struct cris_cond15): New types.
1008 (cris_conds15): Declare.
1009 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1010 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1011 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1012 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1013 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1014 SIZE_FIELD_UNSIGNED.
1016 2004-11-04 Jan Beulich <jbeulich@novell.com>
1018 * i386.h (sldx_Suf): Remove.
1019 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1020 (q_FP): Define, implying no REX64.
1021 (x_FP, sl_FP): Imply FloatMF.
1022 (i386_optab): Split reg and mem forms of moving from segment registers
1023 so that the memory forms can ignore the 16-/32-bit operand size
1024 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1025 all non-floating-point instructions. Unite 32- and 64-bit forms of
1026 movsx, movzx, and movd. Adjust floating point operations for the above
1027 changes to the *FP macros. Add DefaultSize to floating point control
1028 insns operating on larger memory ranges. Remove left over comments
1029 hinting at certain insns being Intel-syntax ones where the ones
1030 actually meant are already gone.
1032 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1034 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1037 2004-09-30 Paul Brook <paul@codesourcery.com>
1039 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1040 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1042 2004-09-11 Theodore A. Roth <troth@openavr.org>
1044 * avr.h: Add support for
1045 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1047 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1049 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1051 2004-08-24 Dmitry Diky <diwil@spec.ru>
1053 * msp430.h (msp430_opc): Add new instructions.
1054 (msp430_rcodes): Declare new instructions.
1055 (msp430_hcodes): Likewise..
1057 2004-08-13 Nick Clifton <nickc@redhat.com>
1060 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1063 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1065 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1067 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1071 2004-07-21 Jan Beulich <jbeulich@novell.com>
1073 * i386.h: Adjust instruction descriptions to better match the
1076 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1078 * arm.h: Remove all old content. Replace with architecture defines
1079 from gas/config/tc-arm.c.
1081 2004-07-09 Andreas Schwab <schwab@suse.de>
1083 * m68k.h: Fix comment.
1085 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1089 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1091 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1093 2004-05-24 Peter Barada <peter@the-baradas.com>
1095 * m68k.h: Add 'size' to m68k_opcode.
1097 2004-05-05 Peter Barada <peter@the-baradas.com>
1099 * m68k.h: Switch from ColdFire chip name to core variant.
1101 2004-04-22 Peter Barada <peter@the-baradas.com>
1103 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1104 descriptions for new EMAC cases.
1105 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1106 handle Motorola MAC syntax.
1107 Allow disassembly of ColdFire V4e object files.
1109 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1111 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1113 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1115 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1117 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1119 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1121 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1123 * i386.h (i386_optab): Added xstore/xcrypt insns.
1125 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1127 * h8300.h (32bit ldc/stc): Add relaxing support.
1129 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1131 * h8300.h (BITOP): Pass MEMRELAX flag.
1133 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1135 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1138 For older changes see ChangeLog-9103
1144 version-control: never