include/opcode/ChangeLog

   1 2005-07-01  Nick Clifton  <nickc@redhat.com>
   2
   3         * sparc.h: Add typedefs to structure declarations.
   4
   5 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         PR 1013
   8         * i386.h (i386_optab): Update comments for 64bit addressing on
   9         mov. Allow 64bit addressing for mov and movq.
  10
  11 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  12
  13         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  14         respectively, in various floating-point load and store patterns.
  15
  16 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  17
  18         * hppa.h (FLAG_STRICT): Correct comment.
  19         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  20         PA 2.0 mneumonics when equivalent.  Entries with cache control
  21         completers now require PA 1.1.  Adjust whitespace.
  22
  23 2005-05-19  Anton Blanchard  <anton@samba.org>
  24
  25         * ppc.h (PPC_OPCODE_POWER5): Define.
  26
  27 2005-05-10  Nick Clifton  <nickc@redhat.com>
  28
  29         * Update the address and phone number of the FSF organization in
  30         the GPL notices in the following files:
  31         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
  32         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
  33         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
  34         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
  35         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  36         tic54x.h, tic80.h, v850.h, vax.h
  37
  38 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  39
  40         * i386.h (i386_optab): Add ht and hnt.
  41
  42 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  43
  44         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  45         Add xcrypt-ctr.  Provide aliases without hyphens.
  46
  47 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         Moved from ../ChangeLog
  50
  51         2005-04-12  Paul Brook  <paul@codesourcery.com>
  52         * m88k.h: Rename psr macros to avoid conflicts.
  53
  54         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  55         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  56         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  57         and ARM_ARCH_V6ZKT2.
  58
  59         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  60         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  61         Remove redundant instruction types.
  62         (struct argument): X_op - new field.
  63         (struct cst4_entry): Remove.
  64         (no_op_insn): Declare.
  65
  66         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  67         * crx.h (enum argtype): Rename types, remove unused types.
  68
  69         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  70         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  71         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  72         (enum operand_type): Rearrange operands, edit comments.
  73         replace us<N> with ui<N> for unsigned immediate.
  74         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  75         displacements (respectively).
  76         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  77         (instruction type): Add NO_TYPE_INS.
  78         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  79         (operand_entry): New field - 'flags'.
  80         (operand flags): New.
  81
  82         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  83         * crx.h (operand_type): Remove redundant types i3, i4,
  84         i5, i8, i12.
  85         Add new unsigned immediate types us3, us4, us5, us16.
  86
  87 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  88
  89         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  90         adjust them accordingly.
  91
  92 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  93
  94         * i386.h (i386_optab): Add rdtscp.
  95
  96 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  99         between memory and segment register. Allow movq for moving between
 100         general-purpose register and segment register.
 101
 102 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 103
 104         PR gas/707
 105         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 106         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 107         fnstsw.
 108
 109 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 110
 111         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 112         * cgen.h (enum cgen_parse_operand_type): Add
 113         CGEN_PARSE_OPERAND_SYMBOLIC.
 114
 115 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 116
 117         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 118         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 119         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 120
 121 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 122
 123         * mips.h (struct mips_opcode): Add new pinfo2 member.
 124         (INSN_ALIAS): New define for opcode table entries that are
 125         specific instances of another entry, such as 'move' for an 'or'
 126         with a zero operand.
 127         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 128         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 129
 130 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 131
 132         * mips.h (CPU_RM9000): Define.
 133         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 134
 135 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 136
 137         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 138         to/from test registers are illegal in 64-bit mode. Add missing
 139         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 140         (previously one had to explicitly encode a rex64 prefix). Re-enable
 141         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 142         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 143
 144 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 145
 146         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 147         available only with SSE2. Change the MMX additions introduced by SSE
 148         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 149         instructions by their now designated identifier (since combining i686
 150         and 3DNow! does not really imply 3DNow!A).
 151
 152 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 153
 154         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 155         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 156
 157 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 158             Vineet Sharma      <vineets@noida.hcltech.com>
 159
 160         * maxq.h: New file: Disassembly information for the maxq port.
 161
 162 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386.h (i386_optab): Put back "movzb".
 165
 166 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 167
 168         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 169         comments.  Remove member cris_ver_sim.  Add members
 170         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 171         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 172         (struct cris_support_reg, struct cris_cond15): New types.
 173         (cris_conds15): Declare.
 174         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 175         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 176         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 177         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 178         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 179         SIZE_FIELD_UNSIGNED.
 180
 181 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 182
 183         * i386.h (sldx_Suf): Remove.
 184         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 185         (q_FP): Define, implying no REX64.
 186         (x_FP, sl_FP): Imply FloatMF.
 187         (i386_optab): Split reg and mem forms of moving from segment registers
 188         so that the memory forms can ignore the 16-/32-bit operand size
 189         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 190         all non-floating-point instructions. Unite 32- and 64-bit forms of
 191         movsx, movzx, and movd. Adjust floating point operations for the above
 192         changes to the *FP macros. Add DefaultSize to floating point control
 193         insns operating on larger memory ranges. Remove left over comments
 194         hinting at certain insns being Intel-syntax ones where the ones
 195         actually meant are already gone.
 196
 197 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 198
 199         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 200         instruction type.
 201
 202 2004-09-30  Paul Brook  <paul@codesourcery.com>
 203
 204         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 205         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 206
 207 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 208
 209         * avr.h: Add support for
 210         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 211
 212 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 213
 214         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 215
 216 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 217
 218         * msp430.h (msp430_opc): Add new instructions.
 219         (msp430_rcodes): Declare new instructions.
 220         (msp430_hcodes): Likewise..
 221
 222 2004-08-13  Nick Clifton  <nickc@redhat.com>
 223
 224         PR/301
 225         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 226         processors.
 227
 228 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 229
 230         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 231
 232 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 235
 236 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 237
 238         * i386.h: Adjust instruction descriptions to better match the
 239         specification.
 240
 241 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 242
 243         * arm.h: Remove all old content.  Replace with architecture defines
 244         from gas/config/tc-arm.c.
 245
 246 2004-07-09  Andreas Schwab  <schwab@suse.de>
 247
 248         * m68k.h: Fix comment.
 249
 250 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 251
 252         * crx.h: New file.
 253
 254 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 255
 256         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 257
 258 2004-05-24  Peter Barada  <peter@the-baradas.com>
 259
 260         * m68k.h: Add 'size' to m68k_opcode.
 261
 262 2004-05-05  Peter Barada  <peter@the-baradas.com>
 263
 264         * m68k.h: Switch from ColdFire chip name to core variant.
 265
 266 2004-04-22  Peter Barada  <peter@the-baradas.com>
 267
 268         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 269         descriptions for new EMAC cases.
 270         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 271         handle Motorola MAC syntax.
 272         Allow disassembly of ColdFire V4e object files.
 273
 274 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 275
 276         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 277
 278 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 279
 280         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 281
 282 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 283
 284         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 285
 286 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 287
 288         * i386.h (i386_optab): Added xstore/xcrypt insns.
 289
 290 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 291
 292         * h8300.h (32bit ldc/stc): Add relaxing support.
 293
 294 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 295
 296         * h8300.h (BITOP): Pass MEMRELAX flag.
 297
 298 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 299
 300         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 301         except for the H8S.
 302
 303 For older changes see ChangeLog-9103
 304 \f
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