1 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (aarch64_op): Add OP_BFC.
5 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
7 * aarch64.h (AARCH64_FEATURE_F16): New.
8 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
11 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
13 * aarch64.h (AARCH64_FEATURE_V8_1): New.
14 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
16 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
18 * arm.h (ARM_EXT2_V8_2A): New.
19 (ARM_ARCH_V8_2A): New.
21 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
23 * aarch64.h (AARCH64_FEATURE_V8_2): New.
24 (AARCH64_ARCH_V8_2): New.
26 2015-11-11 Alan Modra <amodra@gmail.com>
27 Peter Bergner <bergner@vnet.ibm.com>
29 * ppc.h (PPC_OPCODE_POWER9): New define.
30 (PPC_OPCODE_VSX3): Likewise.
32 2015-11-02 Nick Clifton <nickc@redhat.com>
34 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
36 2015-11-02 Nick Clifton <nickc@redhat.com>
38 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
40 2015-10-28 Yao Qi <yao.qi@linaro.org>
42 * aarch64.h (aarch64_decode_insn): Update declaration.
44 2015-10-07 Yao Qi <yao.qi@linaro.org>
46 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
49 2015-10-07 Yao Qi <yao.qi@linaro.org>
51 * aarch64.h [__cplusplus]: Wrap in extern "C".
53 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
54 Cupertino Miranda <cmiranda@synopsys.com>
56 * arc-func.h: New file.
59 2015-10-02 Yao Qi <yao.qi@linaro.org>
61 * aarch64.h (aarch64_zero_register_p): Move the declaration
64 2015-10-02 Yao Qi <yao.qi@linaro.org>
66 * aarch64.h (aarch64_decode_insn): Declare it.
68 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
70 * s390.h (S390_INSTR_FLAG_HTM): New flag.
71 (S390_INSTR_FLAG_VX): New flag.
72 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
74 2015-09-23 Nick Clifton <nickc@redhat.com>
76 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
79 2015-09-22 Nick Clifton <nickc@redhat.com>
81 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
83 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
85 * visium.h (gen_reg_table): Make static.
86 (fp_reg_table): Likewise.
89 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
91 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
92 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
93 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
94 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
96 2015-07-03 Alan Modra <amodra@gmail.com>
98 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
100 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
101 Cesar Philippidis <cesar@codesourcery.com>
103 * nios2.h (enum iw_format_type): Add R2 formats.
104 (enum overflow_type): Add signed_immed12_overflow and
105 enumeration_overflow for R2.
106 (struct nios2_opcode): Document new argument letters for R2.
107 (REG_3BIT, REG_LDWM, REG_POP): Define.
108 (includes): Include nios2r2.h.
109 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
110 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
111 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
112 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
113 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
114 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
116 * nios2r2.h: New file.
118 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
120 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
121 (ppc_optional_operand_value): New inline function.
123 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
125 * aarch64.h (AARCH64_V8_1): New.
127 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
129 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
130 (ARM_ARCH_V8_1A): New.
131 (ARM_ARCH_V8_1A_FP): New.
132 (ARM_ARCH_V8_1A_SIMD): New.
133 (ARM_ARCH_V8_1A_CRYPTOV1): New.
134 (ARM_FEATURE_CORE): New.
136 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
138 * arm.h (ARM_EXT2_PAN): New.
139 (ARM_FEATURE_CORE_HIGH): New.
141 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
143 * arm.h (ARM_FEATURE_ALL): New.
145 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
147 * aarch64.h (AARCH64_FEATURE_RDMA): New.
149 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
151 * aarch64.h (AARCH64_FEATURE_LOR): New.
153 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
155 * aarch64.h (AARCH64_FEATURE_PAN): New.
156 (aarch64_sys_reg_supported_p): Declare.
157 (aarch64_pstatefield_supported_p): Declare.
159 2015-04-30 DJ Delorie <dj@redhat.com>
161 * rl78.h (RL78_Dis_Isa): New.
162 (rl78_decode_opcode): Add ISA parameter.
164 2015-03-24 Terry Guo <terry.guo@arm.com>
166 * arm.h (arm_feature_set): Extended to provide more available bits.
167 (ARM_ANY): Updated to follow above new definition.
168 (ARM_CPU_HAS_FEATURE): Likewise.
169 (ARM_CPU_IS_ANY): Likewise.
170 (ARM_MERGE_FEATURE_SETS): Likewise.
171 (ARM_CLEAR_FEATURE): Likewise.
172 (ARM_FEATURE): Likewise.
173 (ARM_FEATURE_COPY): New macro.
174 (ARM_FEATURE_EQUAL): Likewise.
175 (ARM_FEATURE_ZERO): Likewise.
176 (ARM_FEATURE_CORE_EQUAL): Likewise.
177 (ARM_FEATURE_LOW): Likewise.
178 (ARM_FEATURE_CORE_LOW): Likewise.
179 (ARM_FEATURE_CORE_COPROC): Likewise.
181 2015-02-19 Pedro Alves <palves@redhat.com>
183 * cgen.h [__cplusplus]: Wrap in extern "C".
184 * msp430-decode.h [__cplusplus]: Likewise.
185 * nios2.h [__cplusplus]: Likewise.
186 * rl78.h [__cplusplus]: Likewise.
187 * rx.h [__cplusplus]: Likewise.
188 * tilegx.h [__cplusplus]: Likewise.
190 2015-01-28 James Bowman <james.bowman@ftdichip.com>
194 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
196 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
198 2015-01-01 Alan Modra <amodra@gmail.com>
200 Update year range in copyright notice of all files.
202 2014-12-27 Anthony Green <green@moxielogic.com>
204 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
205 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
207 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
209 * visium.h: New file.
211 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
213 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
214 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
215 (NIOS2_INSN_OPTARG): Renumber.
217 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
219 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
220 declaration. Fix obsolete comment.
222 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
224 * nios2.h (enum iw_format_type): New.
225 (struct nios2_opcode): Update comments. Add size and format fields.
226 (NIOS2_INSN_OPTARG): New.
227 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
228 (struct nios2_reg): Add regtype field.
229 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
230 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
231 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
232 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
233 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
234 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
235 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
236 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
237 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
238 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
239 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
240 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
241 (OP_MASK_OP, OP_SH_OP): Delete.
242 (OP_MASK_IOP, OP_SH_IOP): Delete.
243 (OP_MASK_IRD, OP_SH_IRD): Delete.
244 (OP_MASK_IRT, OP_SH_IRT): Delete.
245 (OP_MASK_IRS, OP_SH_IRS): Delete.
246 (OP_MASK_ROP, OP_SH_ROP): Delete.
247 (OP_MASK_RRD, OP_SH_RRD): Delete.
248 (OP_MASK_RRT, OP_SH_RRT): Delete.
249 (OP_MASK_RRS, OP_SH_RRS): Delete.
250 (OP_MASK_JOP, OP_SH_JOP): Delete.
251 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
252 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
253 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
254 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
255 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
256 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
257 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
258 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
259 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
260 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
261 (OP_MASK_<insn>, OP_MASK): Delete.
262 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
263 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
264 Include nios2r1.h to define new instruction opcode constants
266 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
267 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
268 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
269 (NUMOPCODES, NUMREGISTERS): Delete.
270 * nios2r1.h: New file.
272 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
274 * sparc.h (HWCAP2_VIS3B): Documentation improved.
276 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
278 * sparc.h (sparc_opcode): new field `hwcaps2'.
279 (HWCAP2_FJATHPLUS): New define.
280 (HWCAP2_VIS3B): Likewise.
281 (HWCAP2_ADP): Likewise.
282 (HWCAP2_SPARC5): Likewise.
283 (HWCAP2_MWAIT): Likewise.
284 (HWCAP2_XMPMUL): Likewise.
285 (HWCAP2_XMONT): Likewise.
286 (HWCAP2_NSEC): Likewise.
287 (HWCAP2_FJATHHPC): Likewise.
288 (HWCAP2_FJDES): Likewise.
289 (HWCAP2_FJAES): Likewise.
290 Document the new operand kind `{', corresponding to the mcdper
291 ancillary state register.
292 Document the new operand kind }, which represents frsd floating
293 point registers (double precision) which must be the same than
294 frs1 in its containing instruction.
296 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
298 * nds32.h: Add new opcode declaration.
300 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
301 Matthew Fortune <matthew.fortune@imgtec.com>
303 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
304 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
305 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
306 +I, +O, +R, +:, +\, +", +;
307 (mips_check_prev_operand): New struct.
308 (INSN2_FORBIDDEN_SLOT): New define.
309 (INSN_ISA32R6): New define.
310 (INSN_ISA64R6): New define.
311 (INSN_UPTO32R6): New define.
312 (INSN_UPTO64R6): New define.
313 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
314 (ISA_MIPS32R6): New define.
315 (ISA_MIPS64R6): New define.
316 (CPU_MIPS32R6): New define.
317 (CPU_MIPS64R6): New define.
318 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
320 2014-09-03 Jiong Wang <jiong.wang@arm.com>
322 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
323 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
324 (aarch64_insn_class): Add lse_atomic.
325 (F_LSE_SZ): New field added.
326 (opcode_has_special_coder): Recognize F_LSE_SZ.
328 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
330 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
333 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
335 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
336 (INSN_LOAD_COPROC): New define.
337 (INSN_COPROC_MOVE_DELAY): Rename to...
338 (INSN_COPROC_MOVE): New define.
340 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
341 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
342 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
343 Soundararajan <Sounderarajan.D@atmel.com>
345 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
346 (AVR_ISA_2xxxa): Define ISA without LPM.
347 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
348 Add doc for contraint used in 16 bit lds/sts.
349 Adjust ISA group for icall, ijmp, pop and push.
350 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
352 2014-05-19 Nick Clifton <nickc@redhat.com>
354 * msp430.h (struct msp430_operand_s): Add vshift field.
356 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
358 * mips.h (INSN_ISA_MASK): Updated.
359 (INSN_ISA32R3): New define.
360 (INSN_ISA32R5): New define.
361 (INSN_ISA64R3): New define.
362 (INSN_ISA64R5): New define.
363 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
364 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
365 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
367 (INSN_UPTO32R3): New define.
368 (INSN_UPTO32R5): New define.
369 (INSN_UPTO64R3): New define.
370 (INSN_UPTO64R5): New define.
371 (ISA_MIPS32R3): New define.
372 (ISA_MIPS32R5): New define.
373 (ISA_MIPS64R3): New define.
374 (ISA_MIPS64R5): New define.
375 (CPU_MIPS32R3): New define.
376 (CPU_MIPS32R5): New define.
377 (CPU_MIPS64R3): New define.
378 (CPU_MIPS64R5): New define.
380 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
382 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
384 2014-04-22 Christian Svensson <blue@cmd.nu>
388 2014-03-05 Alan Modra <amodra@gmail.com>
390 Update copyright years.
392 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
394 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
397 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
398 Wei-Cheng Wang <cole945@gmail.com>
400 * nds32.h: New file for Andes NDS32.
402 2013-12-07 Mike Frysinger <vapier@gentoo.org>
404 * bfin.h: Remove +x file mode.
406 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
408 * aarch64.h (aarch64_pstatefields): Change element type to
411 2013-11-18 Renlin Li <Renlin.Li@arm.com>
413 * arm.h (ARM_AEXT_V7VE): New define.
414 (ARM_ARCH_V7VE): New define.
415 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
417 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
421 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
423 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
424 (aarch64_sys_reg_writeonly_p): Ditto.
426 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
428 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
429 (aarch64_sys_reg_writeonly_p): Ditto.
431 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
433 * aarch64.h (aarch64_sys_reg): New typedef.
434 (aarch64_sys_regs): Change to define with the new type.
435 (aarch64_sys_reg_deprecated_p): Declare.
437 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
439 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
440 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
442 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
444 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
445 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
446 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
447 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
448 For MIPS, update extension character sequences after +.
449 (ASE_MSA): New define.
450 (ASE_MSA64): New define.
451 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
452 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
453 For microMIPS, update extension character sequences after +.
455 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
460 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
462 * mips.h: Remove references to "+I" and imm2_expr.
464 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
466 * mips.h (M_DEXT, M_DINS): Delete.
468 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
470 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
471 (mips_optional_operand_p): New function.
473 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
474 Richard Sandiford <rdsandiford@googlemail.com>
476 * mips.h: Document new VU0 operand characters.
477 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
478 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
479 (OP_REG_R5900_ACC): New mips_reg_operand_types.
480 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
481 (mips_vu0_channel_mask): Declare.
483 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
485 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
486 (mips_int_operand_min, mips_int_operand_max): New functions.
487 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
489 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
491 * mips.h (mips_decode_reg_operand): New function.
492 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
493 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
494 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
496 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
497 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
498 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
499 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
500 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
501 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
502 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
503 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
504 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
505 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
506 macros to cover the gaps.
507 (INSN2_MOD_SP): Replace with...
508 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
509 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
510 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
511 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
512 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
515 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
517 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
518 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
519 (MIPS16_INSN_COND_BRANCH): Delete.
521 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
522 Kirill Yukhin <kirill.yukhin@intel.com>
523 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
525 * i386.h (BND_PREFIX_OPCODE): New.
527 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
529 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
530 OP_SAVE_RESTORE_LIST.
531 (decode_mips16_operand): Declare.
533 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
535 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
536 (mips_operand, mips_int_operand, mips_mapped_int_operand)
537 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
538 (mips_pcrel_operand): New structures.
539 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
540 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
541 (decode_mips_operand, decode_micromips_operand): Declare.
543 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
545 * mips.h: Document MIPS16 "I" opcode.
547 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
549 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
550 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
551 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
552 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
553 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
554 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
555 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
556 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
557 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
558 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
559 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
560 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
561 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
563 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
564 (M_USD_AB): ...these.
566 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
568 * mips.h: Remove documentation of "[" and "]". Update documentation
569 of "k" and the MDMX formats.
571 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
573 * mips.h: Update documentation of "+s" and "+S".
575 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
577 * mips.h: Document "+i".
579 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
581 * mips.h: Remove "mi" documentation. Update "mh" documentation.
582 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
584 (INSN2_WRITE_GPR_MHI): Rename to...
585 (INSN2_WRITE_GPR_MH): ...this.
587 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
589 * mips.h: Remove documentation of "+D" and "+T".
591 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
593 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
594 Use "source" rather than "destination" for microMIPS "G".
596 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
598 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
601 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
603 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
605 2013-06-17 Catherine Moore <clm@codesourcery.com>
606 Maciej W. Rozycki <macro@codesourcery.com>
607 Chao-Ying Fu <fu@mips.com>
609 * mips.h (OP_SH_EVAOFFSET): Define.
610 (OP_MASK_EVAOFFSET): Define.
611 (INSN_ASE_MASK): Delete.
613 (M_CACHEE_AB, M_CACHEE_OB): New.
614 (M_LBE_OB, M_LBE_AB): New.
615 (M_LBUE_OB, M_LBUE_AB): New.
616 (M_LHE_OB, M_LHE_AB): New.
617 (M_LHUE_OB, M_LHUE_AB): New.
618 (M_LLE_AB, M_LLE_OB): New.
619 (M_LWE_OB, M_LWE_AB): New.
620 (M_LWLE_AB, M_LWLE_OB): New.
621 (M_LWRE_AB, M_LWRE_OB): New.
622 (M_PREFE_AB, M_PREFE_OB): New.
623 (M_SCE_AB, M_SCE_OB): New.
624 (M_SBE_OB, M_SBE_AB): New.
625 (M_SHE_OB, M_SHE_AB): New.
626 (M_SWE_OB, M_SWE_AB): New.
627 (M_SWLE_AB, M_SWLE_OB): New.
628 (M_SWRE_AB, M_SWRE_OB): New.
629 (MICROMIPSOP_SH_EVAOFFSET): Define.
630 (MICROMIPSOP_MASK_EVAOFFSET): Define.
632 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
634 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
636 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
638 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
640 2013-05-09 Andrew Pinski <apinski@cavium.com>
642 * mips.h (OP_MASK_CODE10): Correct definition.
643 (OP_SH_CODE10): Likewise.
644 Add a comment that "+J" is used now for OP_*CODE10.
645 (INSN_ASE_MASK): Update.
646 (INSN_VIRT): New macro.
647 (INSN_VIRT64): New macro
649 2013-05-02 Nick Clifton <nickc@redhat.com>
651 * msp430.h: Add patterns for MSP430X instructions.
653 2013-04-06 David S. Miller <davem@davemloft.net>
655 * sparc.h (F_PREFERRED): Define.
656 (F_PREF_ALIAS): Define.
658 2013-04-03 Nick Clifton <nickc@redhat.com>
660 * v850.h (V850_INVERSE_PCREL): Define.
662 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
665 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
667 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
670 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
672 * tic6xc-opcode-table.h: Add 16-bit insns.
673 * tic6x.h: Add support for 16-bit insns.
675 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
677 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
678 and mov.b/w/l Rs,@(d:32,ERd).
680 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
683 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
684 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
685 tic6x_operand_xregpair operand coding type.
686 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
687 opcode field, usu ORXREGD1324 for the src2 operand and remove the
690 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
693 * tic6x.h (enum tic6x_coding_method): Add
694 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
695 separately the msb and lsb of a register pair. This is needed to
696 encode the opcodes in the same way as TI assembler does.
697 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
698 and rsqrdp opcodes to use the new field coding types.
700 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
702 * arm.h (CRC_EXT_ARMV8): New constant.
703 (ARCH_CRC_ARMV8): New macro.
705 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
707 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
709 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
710 Andrew Jenner <andrew@codesourcery.com>
712 Based on patches from Altera Corporation.
716 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
718 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
720 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
723 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
725 2013-01-24 Nick Clifton <nickc@redhat.com>
727 * v850.h: Add e3v5 support.
729 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
731 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
733 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
735 * ppc.h (PPC_OPCODE_POWER8): New define.
736 (PPC_OPCODE_HTM): Likewise.
738 2013-01-10 Will Newton <will.newton@imgtec.com>
742 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
744 * cr16.h (make_instruction): Rename to cr16_make_instruction.
745 (match_opcode): Rename to cr16_match_opcode.
747 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
749 * mips.h: Add support for r5900 instructions including lq and sq.
751 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
753 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
754 (make_instruction,match_opcode): Added function prototypes.
755 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
757 2012-11-23 Alan Modra <amodra@gmail.com>
759 * ppc.h (ppc_parse_cpu): Update prototype.
761 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
763 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
764 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
766 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
768 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
770 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
772 * ia64.h (ia64_opnd): Add new operand types.
774 2012-08-21 David S. Miller <davem@davemloft.net>
776 * sparc.h (F3F4): New macro.
778 2012-08-13 Ian Bolton <ian.bolton@arm.com>
779 Laurent Desnogues <laurent.desnogues@arm.com>
780 Jim MacArthur <jim.macarthur@arm.com>
781 Marcus Shawcroft <marcus.shawcroft@arm.com>
782 Nigel Stephens <nigel.stephens@arm.com>
783 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
784 Richard Earnshaw <rearnsha@arm.com>
785 Sofiane Naci <sofiane.naci@arm.com>
786 Tejas Belagod <tejas.belagod@arm.com>
787 Yufeng Zhang <yufeng.zhang@arm.com>
789 * aarch64.h: New file.
791 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
792 Maciej W. Rozycki <macro@codesourcery.com>
794 * mips.h (mips_opcode): Add the exclusions field.
795 (OPCODE_IS_MEMBER): Remove macro.
796 (cpu_is_member): New inline function.
797 (opcode_is_member): Likewise.
799 2012-07-31 Chao-Ying Fu <fu@mips.com>
800 Catherine Moore <clm@codesourcery.com>
801 Maciej W. Rozycki <macro@codesourcery.com>
803 * mips.h: Document microMIPS DSP ASE usage.
804 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
805 microMIPS DSP ASE support.
806 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
807 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
808 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
809 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
810 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
811 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
812 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
814 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
816 * mips.h: Fix a typo in description.
818 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
820 * avr.h: (AVR_ISA_XCH): New define.
821 (AVR_ISA_XMEGA): Use it.
822 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
824 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
826 * m68hc11.h: Add XGate definitions.
827 (struct m68hc11_opcode): Add xg_mask field.
829 2012-05-14 Catherine Moore <clm@codesourcery.com>
830 Maciej W. Rozycki <macro@codesourcery.com>
831 Rhonda Wittels <rhonda@codesourcery.com>
833 * ppc.h (PPC_OPCODE_VLE): New definition.
834 (PPC_OP_SA): New macro.
835 (PPC_OP_SE_VLE): New macro.
836 (PPC_OP): Use a variable shift amount.
837 (powerpc_operand): Update comments.
838 (PPC_OPSHIFT_INV): New macro.
839 (PPC_OPERAND_CR): Replace with...
840 (PPC_OPERAND_CR_BIT): ...this and
841 (PPC_OPERAND_CR_REG): ...this.
844 2012-05-03 Sean Keys <skeys@ipdatasys.com>
846 * xgate.h: Header file for XGATE assembler.
848 2012-04-27 David S. Miller <davem@davemloft.net>
850 * sparc.h: Document new arg code' )' for crypto RS3
853 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
854 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
855 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
856 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
857 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
858 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
859 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
860 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
861 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
862 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
863 HWCAP_CBCOND, HWCAP_CRC32): New defines.
865 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
867 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
869 2012-02-27 Alan Modra <amodra@gmail.com>
871 * crx.h (cst4_map): Update declaration.
873 2012-02-25 Walter Lee <walt@tilera.com>
875 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
877 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
878 TILEPRO_OPC_LW_TLS_SN.
880 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
882 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
883 (XRELEASE_PREFIX_OPCODE): Likewise.
885 2011-12-08 Andrew Pinski <apinski@cavium.com>
886 Adam Nemet <anemet@caviumnetworks.com>
888 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
889 (INSN_OCTEON2): New macro.
890 (CPU_OCTEON2): New macro.
891 (OPCODE_IS_MEMBER): Add Octeon2.
893 2011-11-29 Andrew Pinski <apinski@cavium.com>
895 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
896 (INSN_OCTEONP): New macro.
897 (CPU_OCTEONP): New macro.
898 (OPCODE_IS_MEMBER): Add Octeon+.
899 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
901 2011-11-01 DJ Delorie <dj@redhat.com>
905 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
907 * mips.h: Fix a typo in description.
909 2011-09-21 David S. Miller <davem@davemloft.net>
911 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
912 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
913 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
914 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
916 2011-08-09 Chao-ying Fu <fu@mips.com>
917 Maciej W. Rozycki <macro@codesourcery.com>
919 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
920 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
921 (INSN_ASE_MASK): Add the MCU bit.
922 (INSN_MCU): New macro.
923 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
924 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
926 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
928 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
929 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
930 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
931 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
932 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
933 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
934 (INSN2_READ_GPR_MMN): Likewise.
935 (INSN2_READ_FPR_D): Change the bit used.
936 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
937 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
938 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
939 (INSN2_COND_BRANCH): Likewise.
940 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
941 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
942 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
943 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
944 (INSN2_MOD_GPR_MN): Likewise.
946 2011-08-05 David S. Miller <davem@davemloft.net>
948 * sparc.h: Document new format codes '4', '5', and '('.
949 (OPF_LOW4, RS3): New macros.
951 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
953 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
954 order of flags documented.
956 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
958 * mips.h: Clarify the description of microMIPS instruction
960 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
962 2011-07-24 Chao-ying Fu <fu@mips.com>
963 Maciej W. Rozycki <macro@codesourcery.com>
965 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
966 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
967 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
968 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
969 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
970 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
971 (OP_MASK_RS3, OP_SH_RS3): Likewise.
972 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
973 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
974 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
975 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
976 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
977 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
978 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
979 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
980 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
981 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
982 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
983 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
984 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
985 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
986 (INSN_WRITE_GPR_S): New macro.
987 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
988 (INSN2_READ_FPR_D): Likewise.
989 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
990 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
991 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
992 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
993 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
994 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
995 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
996 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
997 (CPU_MICROMIPS): New macro.
998 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
999 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1000 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1001 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1002 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1003 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1004 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1005 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1006 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1007 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1008 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1009 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1010 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1011 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1012 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1013 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1014 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1015 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1016 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1017 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1018 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1019 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1020 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1021 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1022 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1023 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1024 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1025 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1026 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1027 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1028 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1029 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1030 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1031 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1032 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1033 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1034 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1035 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1036 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1037 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1038 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1039 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1040 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1041 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1042 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1043 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1044 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1045 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1046 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1047 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1048 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1049 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1050 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1051 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1052 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1053 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1054 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1055 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1056 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1057 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1058 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1059 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1060 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1061 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1062 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1063 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1064 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1065 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1066 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1067 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1068 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1069 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1070 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1071 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1072 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1073 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1074 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1075 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1076 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1077 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1078 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1079 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1080 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1081 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1082 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1083 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1084 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1085 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1086 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1087 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1088 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1089 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1090 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1091 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1092 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1093 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1094 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1095 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1096 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1097 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1098 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1099 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1100 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1101 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1102 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1103 (micromips_opcodes): New declaration.
1104 (bfd_micromips_num_opcodes): Likewise.
1106 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1108 * mips.h (INSN_TRAP): Rename to...
1109 (INSN_NO_DELAY_SLOT): ... this.
1110 (INSN_SYNC): Remove macro.
1112 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1114 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1115 a duplicate of AVR_ISA_SPM.
1117 2011-07-01 Nick Clifton <nickc@redhat.com>
1119 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1121 2011-06-18 Robin Getz <robin.getz@analog.com>
1123 * bfin.h (is_macmod_signed): New func
1125 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1127 * bfin.h (is_macmod_pmove): Add missing space before func args.
1128 (is_macmod_hmove): Likewise.
1130 2011-06-13 Walter Lee <walt@tilera.com>
1132 * tilegx.h: New file.
1133 * tilepro.h: New file.
1135 2011-05-31 Paul Brook <paul@codesourcery.com>
1137 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1139 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1141 * s390.h: Replace S390_OPERAND_REG_EVEN with
1142 S390_OPERAND_REG_PAIR.
1144 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1146 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1148 2011-04-18 Julian Brown <julian@codesourcery.com>
1150 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1152 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1155 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1157 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1159 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1160 New instruction set flags.
1161 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1163 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1165 * mips.h (M_PREF_AB): New enum value.
1167 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1169 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1171 (is_macmod_pmove, is_macmod_hmove): New functions.
1173 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1175 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1177 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1179 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1180 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1182 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1185 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1188 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1191 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1193 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1195 * mips.h: Update commentary after last commit.
1197 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1199 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1200 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1201 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1203 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1205 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1207 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1209 * mips.h: Fix previous commit.
1211 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1213 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1214 (INSN_LOONGSON_3A): Clear bit 31.
1216 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1219 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1220 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1221 (ARM_ARCH_V6M_ONLY): New define.
1223 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1225 * mips.h (INSN_LOONGSON_3A): Defined.
1226 (CPU_LOONGSON_3A): Defined.
1227 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1229 2010-10-09 Matt Rice <ratmice@gmail.com>
1231 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1232 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1234 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1236 * arm.h (ARM_EXT_VIRT): New define.
1237 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1238 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1241 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1243 * arm.h (ARM_AEXT_ADIV): New define.
1244 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1246 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1248 * arm.h (ARM_EXT_OS): New define.
1249 (ARM_AEXT_V6SM): Likewise.
1250 (ARM_ARCH_V6SM): Likewise.
1252 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1254 * arm.h (ARM_EXT_MP): Add.
1255 (ARM_ARCH_V7A_MP): Likewise.
1257 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1259 * bfin.h: Declare pseudoChr structs/defines.
1261 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1263 * bfin.h: Strip trailing whitespace.
1265 2010-07-29 DJ Delorie <dj@redhat.com>
1267 * rx.h (RX_Operand_Type): Add TwoReg.
1268 (RX_Opcode_ID): Remove ediv and ediv2.
1270 2010-07-27 DJ Delorie <dj@redhat.com>
1272 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1274 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1275 Ina Pandit <ina.pandit@kpitcummins.com>
1277 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1278 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1279 PROCESSOR_V850E2_ALL.
1280 Remove PROCESSOR_V850EA support.
1281 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1282 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1283 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1284 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1285 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1286 V850_OPERAND_PERCENT.
1287 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1289 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1292 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1294 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1295 (MIPS16_INSN_BRANCH): Rename to...
1296 (MIPS16_INSN_COND_BRANCH): ... this.
1298 2010-07-03 Alan Modra <amodra@gmail.com>
1300 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1301 Renumber other PPC_OPCODE defines.
1303 2010-07-03 Alan Modra <amodra@gmail.com>
1305 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1307 2010-06-29 Alan Modra <amodra@gmail.com>
1309 * maxq.h: Delete file.
1311 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1313 * ppc.h (PPC_OPCODE_E500): Define.
1315 2010-05-26 Catherine Moore <clm@codesourcery.com>
1317 * opcode/mips.h (INSN_MIPS16): Remove.
1319 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1321 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1323 2010-04-15 Nick Clifton <nickc@redhat.com>
1325 * alpha.h: Update copyright notice to use GPLv3.
1331 * convex.h: Likewise.
1338 * h8300.h: Likewise.
1345 * m68hc11.h: Likewise.
1351 * mn10200.h: Likewise.
1352 * mn10300.h: Likewise.
1353 * msp430.h: Likewise.
1355 * ns32k.h: Likewise.
1357 * pdp11.h: Likewise.
1364 * score-datadep.h: Likewise.
1365 * score-inst.h: Likewise.
1366 * sparc.h: Likewise.
1367 * spu-insns.h: Likewise.
1369 * tic30.h: Likewise.
1370 * tic4x.h: Likewise.
1371 * tic54x.h: Likewise.
1372 * tic80.h: Likewise.
1376 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1378 * tic6x-control-registers.h, tic6x-insn-formats.h,
1379 tic6x-opcode-table.h, tic6x.h: New.
1381 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1383 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1385 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1387 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1389 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1391 * ia64.h (ia64_find_opcode): Remove argument name.
1392 (ia64_find_next_opcode): Likewise.
1393 (ia64_dis_opcode): Likewise.
1394 (ia64_free_opcode): Likewise.
1395 (ia64_find_dependency): Likewise.
1397 2009-11-22 Doug Evans <dje@sebabeach.org>
1399 * cgen.h: Include bfd_stdint.h.
1400 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1402 2009-11-18 Paul Brook <paul@codesourcery.com>
1404 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1406 2009-11-17 Paul Brook <paul@codesourcery.com>
1407 Daniel Jacobowitz <dan@codesourcery.com>
1409 * arm.h (ARM_EXT_V6_DSP): Define.
1410 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1411 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1413 2009-11-04 DJ Delorie <dj@redhat.com>
1415 * rx.h (rx_decode_opcode) (mvtipl): Add.
1416 (mvtcp, mvfcp, opecp): Remove.
1418 2009-11-02 Paul Brook <paul@codesourcery.com>
1420 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1421 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1422 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1423 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1424 FPU_ARCH_NEON_VFP_V4): Define.
1426 2009-10-23 Doug Evans <dje@sebabeach.org>
1428 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1429 * cgen.h: Update. Improve multi-inclusion macro name.
1431 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1433 * ppc.h (PPC_OPCODE_476): Define.
1435 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1437 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1439 2009-09-29 DJ Delorie <dj@redhat.com>
1443 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1445 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1447 2009-09-21 Ben Elliston <bje@au.ibm.com>
1449 * ppc.h (PPC_OPCODE_PPCA2): New.
1451 2009-09-05 Martin Thuresson <martin@mtme.org>
1453 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1455 2009-08-29 Martin Thuresson <martin@mtme.org>
1457 * tic30.h (template): Rename type template to
1458 insn_template. Updated code to use new name.
1459 * tic54x.h (template): Rename type template to
1462 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1464 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1466 2009-06-11 Anthony Green <green@moxielogic.com>
1468 * moxie.h (MOXIE_F3_PCREL): Define.
1469 (moxie_form3_opc_info): Grow.
1471 2009-06-06 Anthony Green <green@moxielogic.com>
1473 * moxie.h (MOXIE_F1_M): Define.
1475 2009-04-15 Anthony Green <green@moxielogic.com>
1479 2009-04-06 DJ Delorie <dj@redhat.com>
1481 * h8300.h: Add relaxation attributes to MOVA opcodes.
1483 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1485 * ppc.h (ppc_parse_cpu): Declare.
1487 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1489 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1490 and _IMM11 for mbitclr and mbitset.
1491 * score-datadep.h: Update dependency information.
1493 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1495 * ppc.h (PPC_OPCODE_POWER7): New.
1497 2009-02-06 Doug Evans <dje@google.com>
1499 * i386.h: Add comment regarding sse* insns and prefixes.
1501 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1503 * mips.h (INSN_XLR): Define.
1504 (INSN_CHIP_MASK): Update.
1506 (OPCODE_IS_MEMBER): Update.
1507 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1509 2009-01-28 Doug Evans <dje@google.com>
1511 * opcode/i386.h: Add multiple inclusion protection.
1512 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1513 (EDI_REG_NUM): New macros.
1514 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1515 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1516 (REX_PREFIX_P): New macro.
1518 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1520 * ppc.h (struct powerpc_opcode): New field "deprecated".
1521 (PPC_OPCODE_NOPOWER4): Delete.
1523 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1525 * mips.h: Define CPU_R14000, CPU_R16000.
1526 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1528 2008-11-18 Catherine Moore <clm@codesourcery.com>
1530 * arm.h (FPU_NEON_FP16): New.
1531 (FPU_ARCH_NEON_FP16): New.
1533 2008-11-06 Chao-ying Fu <fu@mips.com>
1535 * mips.h: Doucument '1' for 5-bit sync type.
1537 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1539 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1542 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1544 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1546 2008-07-30 Michael J. Eager <eager@eagercon.com>
1548 * ppc.h (PPC_OPCODE_405): Define.
1549 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1551 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1553 * ppc.h (ppc_cpu_t): New typedef.
1554 (struct powerpc_opcode <flags>): Use it.
1555 (struct powerpc_operand <insert, extract>): Likewise.
1556 (struct powerpc_macro <flags>): Likewise.
1558 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1560 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1561 Update comment before MIPS16 field descriptors to mention MIPS16.
1562 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1564 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1565 New bit masks and shift counts for cins and exts.
1567 * mips.h: Document new field descriptors +Q.
1568 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1570 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1572 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1573 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1575 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1577 * ppc.h: (PPC_OPCODE_E500MC): New.
1579 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1581 * i386.h (MAX_OPERANDS): Set to 5.
1582 (MAX_MNEM_SIZE): Changed to 20.
1584 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1586 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1588 2008-03-09 Paul Brook <paul@codesourcery.com>
1590 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1592 2008-03-04 Paul Brook <paul@codesourcery.com>
1594 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1595 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1596 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1598 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1599 Nick Clifton <nickc@redhat.com>
1602 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1603 with a 32-bit displacement but without the top bit of the 4th byte
1606 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1608 * cr16.h (cr16_num_optab): Declared.
1610 2008-02-14 Hakan Ardo <hakan@debian.org>
1613 * avr.h (AVR_ISA_2xxe): Define.
1615 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1617 * mips.h: Update copyright.
1618 (INSN_CHIP_MASK): New macro.
1619 (INSN_OCTEON): New macro.
1620 (CPU_OCTEON): New macro.
1621 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1623 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1625 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1627 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1629 * avr.h (AVR_ISA_USB162): Add new opcode set.
1630 (AVR_ISA_AVR3): Likewise.
1632 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1634 * mips.h (INSN_LOONGSON_2E): New.
1635 (INSN_LOONGSON_2F): New.
1636 (CPU_LOONGSON_2E): New.
1637 (CPU_LOONGSON_2F): New.
1638 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1640 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1642 * mips.h (INSN_ISA*): Redefine certain values as an
1643 enumeration. Update comments.
1644 (mips_isa_table): New.
1645 (ISA_MIPS*): Redefine to match enumeration.
1646 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1649 2007-08-08 Ben Elliston <bje@au.ibm.com>
1651 * ppc.h (PPC_OPCODE_PPCPS): New.
1653 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1655 * m68k.h: Document j K & E.
1657 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1659 * cr16.h: New file for CR16 target.
1661 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1663 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1665 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1667 * m68k.h (mcfisa_c): New.
1668 (mcfusp, mcf_mask): Adjust.
1670 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1672 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1673 (num_powerpc_operands): Declare.
1674 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1675 (PPC_OPERAND_PLUS1): Define.
1677 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1679 * i386.h (REX_MODE64): Renamed to ...
1681 (REX_EXTX): Renamed to ...
1683 (REX_EXTY): Renamed to ...
1685 (REX_EXTZ): Renamed to ...
1688 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386.h: Add entries from config/tc-i386.h and move tables
1691 to opcodes/i386-opc.h.
1693 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1695 * i386.h (FloatDR): Removed.
1696 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1698 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1700 * spu-insns.h: Add soma double-float insns.
1702 2007-02-20 Thiemo Seufer <ths@mips.com>
1703 Chao-Ying Fu <fu@mips.com>
1705 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1706 (INSN_DSPR2): Add flag for DSP R2 instructions.
1707 (M_BALIGN): New macro.
1709 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1711 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1712 and Seg3ShortFrom with Shortform.
1714 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1717 * i386.h (i386_optab): Put the real "test" before the pseudo
1720 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1722 * m68k.h (m68010up): OR fido_a.
1724 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1726 * m68k.h (fido_a): New.
1728 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1730 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1731 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1734 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1736 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1738 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1740 * score-inst.h (enum score_insn_type): Add Insn_internal.
1742 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1743 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1744 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1745 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1746 Alan Modra <amodra@bigpond.net.au>
1748 * spu-insns.h: New file.
1751 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1753 * ppc.h (PPC_OPCODE_CELL): Define.
1755 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1757 * i386.h : Modify opcode to support for the change in POPCNT opcode
1758 in amdfam10 architecture.
1760 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386.h: Replace CpuMNI with CpuSSSE3.
1764 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1765 Joseph Myers <joseph@codesourcery.com>
1766 Ian Lance Taylor <ian@wasabisystems.com>
1767 Ben Elliston <bje@wasabisystems.com>
1769 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1771 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1773 * score-datadep.h: New file.
1774 * score-inst.h: New file.
1776 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1778 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1779 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1780 movdq2q and movq2dq.
1782 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1783 Michael Meissner <michael.meissner@amd.com>
1785 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1787 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1789 * i386.h (i386_optab): Add "nop" with memory reference.
1791 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1793 * i386.h (i386_optab): Update comment for 64bit NOP.
1795 2006-06-06 Ben Elliston <bje@au.ibm.com>
1796 Anton Blanchard <anton@samba.org>
1798 * ppc.h (PPC_OPCODE_POWER6): Define.
1801 2006-06-05 Thiemo Seufer <ths@mips.com>
1803 * mips.h: Improve description of MT flags.
1805 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1807 * m68k.h (mcf_mask): Define.
1809 2006-05-05 Thiemo Seufer <ths@mips.com>
1810 David Ung <davidu@mips.com>
1812 * mips.h (enum): Add macro M_CACHE_AB.
1814 2006-05-04 Thiemo Seufer <ths@mips.com>
1815 Nigel Stephens <nigel@mips.com>
1816 David Ung <davidu@mips.com>
1818 * mips.h: Add INSN_SMARTMIPS define.
1820 2006-04-30 Thiemo Seufer <ths@mips.com>
1821 David Ung <davidu@mips.com>
1823 * mips.h: Defines udi bits and masks. Add description of
1824 characters which may appear in the args field of udi
1827 2006-04-26 Thiemo Seufer <ths@networkno.de>
1829 * mips.h: Improve comments describing the bitfield instruction
1832 2006-04-26 Julian Brown <julian@codesourcery.com>
1834 * arm.h (FPU_VFP_EXT_V3): Define constant.
1835 (FPU_NEON_EXT_V1): Likewise.
1836 (FPU_VFP_HARD): Update.
1837 (FPU_VFP_V3): Define macro.
1838 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1840 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1842 * avr.h (AVR_ISA_PWMx): New.
1844 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1846 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1847 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1848 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1849 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1850 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1852 2006-03-10 Paul Brook <paul@codesourcery.com>
1854 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1856 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1858 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1859 first. Correct mask of bb "B" opcode.
1861 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1863 * i386.h (i386_optab): Support Intel Merom New Instructions.
1865 2006-02-24 Paul Brook <paul@codesourcery.com>
1867 * arm.h: Add V7 feature bits.
1869 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1871 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1873 2006-01-31 Paul Brook <paul@codesourcery.com>
1874 Richard Earnshaw <rearnsha@arm.com>
1876 * arm.h: Use ARM_CPU_FEATURE.
1877 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1878 (arm_feature_set): Change to a structure.
1879 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1880 ARM_FEATURE): New macros.
1882 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1884 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1885 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1886 (ADD_PC_INCR_OPCODE): Don't define.
1888 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1891 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1893 2005-11-14 David Ung <davidu@mips.com>
1895 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1896 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1897 save/restore encoding of the args field.
1899 2005-10-28 Dave Brolley <brolley@redhat.com>
1901 Contribute the following changes:
1902 2005-02-16 Dave Brolley <brolley@redhat.com>
1904 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1905 cgen_isa_mask_* to cgen_bitset_*.
1908 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1910 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1911 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1912 (CGEN_CPU_TABLE): Make isas a ponter.
1914 2003-09-29 Dave Brolley <brolley@redhat.com>
1916 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1917 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1918 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1920 2002-12-13 Dave Brolley <brolley@redhat.com>
1922 * cgen.h (symcat.h): #include it.
1923 (cgen-bitset.h): #include it.
1924 (CGEN_ATTR_VALUE_TYPE): Now a union.
1925 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1926 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1927 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1928 * cgen-bitset.h: New file.
1930 2005-09-30 Catherine Moore <clm@cm00re.com>
1934 2005-10-24 Jan Beulich <jbeulich@novell.com>
1936 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1939 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1941 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1942 Add FLAG_STRICT to pa10 ftest opcode.
1944 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1946 * hppa.h (pa_opcodes): Remove lha entries.
1948 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1950 * hppa.h (FLAG_STRICT): Revise comment.
1951 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1952 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1955 2005-09-30 Catherine Moore <clm@cm00re.com>
1959 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1961 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1963 2005-09-06 Chao-ying Fu <fu@mips.com>
1965 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1966 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1968 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1969 (INSN_ASE_MASK): Update to include INSN_MT.
1970 (INSN_MT): New define for MT ASE.
1972 2005-08-25 Chao-ying Fu <fu@mips.com>
1974 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1975 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1976 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1977 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1978 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1979 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1981 (INSN_DSP): New define for DSP ASE.
1983 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1987 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1989 * ppc.h (PPC_OPCODE_E300): Define.
1991 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1993 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1995 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1998 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2001 2005-07-27 Jan Beulich <jbeulich@novell.com>
2003 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2004 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2005 Add movq-s as 64-bit variants of movd-s.
2007 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2009 * hppa.h: Fix punctuation in comment.
2011 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2012 implicit space-register addressing. Set space-register bits on opcodes
2013 using implicit space-register addressing. Add various missing pa20
2014 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2015 space-register addressing. Use "fE" instead of "fe" in various
2018 2005-07-18 Jan Beulich <jbeulich@novell.com>
2020 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2022 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2024 * i386.h (i386_optab): Support Intel VMX Instructions.
2026 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2028 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2030 2005-07-05 Jan Beulich <jbeulich@novell.com>
2032 * i386.h (i386_optab): Add new insns.
2034 2005-07-01 Nick Clifton <nickc@redhat.com>
2036 * sparc.h: Add typedefs to structure declarations.
2038 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2041 * i386.h (i386_optab): Update comments for 64bit addressing on
2042 mov. Allow 64bit addressing for mov and movq.
2044 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2046 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2047 respectively, in various floating-point load and store patterns.
2049 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2051 * hppa.h (FLAG_STRICT): Correct comment.
2052 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2053 PA 2.0 mneumonics when equivalent. Entries with cache control
2054 completers now require PA 1.1. Adjust whitespace.
2056 2005-05-19 Anton Blanchard <anton@samba.org>
2058 * ppc.h (PPC_OPCODE_POWER5): Define.
2060 2005-05-10 Nick Clifton <nickc@redhat.com>
2062 * Update the address and phone number of the FSF organization in
2063 the GPL notices in the following files:
2064 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2065 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2066 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2067 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2068 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2069 tic54x.h, tic80.h, v850.h, vax.h
2071 2005-05-09 Jan Beulich <jbeulich@novell.com>
2073 * i386.h (i386_optab): Add ht and hnt.
2075 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2077 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2078 Add xcrypt-ctr. Provide aliases without hyphens.
2080 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2082 Moved from ../ChangeLog
2084 2005-04-12 Paul Brook <paul@codesourcery.com>
2085 * m88k.h: Rename psr macros to avoid conflicts.
2087 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2088 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2089 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2090 and ARM_ARCH_V6ZKT2.
2092 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2093 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2094 Remove redundant instruction types.
2095 (struct argument): X_op - new field.
2096 (struct cst4_entry): Remove.
2097 (no_op_insn): Declare.
2099 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2100 * crx.h (enum argtype): Rename types, remove unused types.
2102 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2103 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2104 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2105 (enum operand_type): Rearrange operands, edit comments.
2106 replace us<N> with ui<N> for unsigned immediate.
2107 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2108 displacements (respectively).
2109 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2110 (instruction type): Add NO_TYPE_INS.
2111 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2112 (operand_entry): New field - 'flags'.
2113 (operand flags): New.
2115 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2116 * crx.h (operand_type): Remove redundant types i3, i4,
2118 Add new unsigned immediate types us3, us4, us5, us16.
2120 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2122 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2123 adjust them accordingly.
2125 2005-04-01 Jan Beulich <jbeulich@novell.com>
2127 * i386.h (i386_optab): Add rdtscp.
2129 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2131 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2132 between memory and segment register. Allow movq for moving between
2133 general-purpose register and segment register.
2135 2005-02-09 Jan Beulich <jbeulich@novell.com>
2138 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2139 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2142 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2144 * m68k.h (m68008, m68ec030, m68882): Remove.
2146 (cpu_m68k, cpu_cf): New.
2147 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2148 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2150 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2152 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2153 * cgen.h (enum cgen_parse_operand_type): Add
2154 CGEN_PARSE_OPERAND_SYMBOLIC.
2156 2005-01-21 Fred Fish <fnf@specifixinc.com>
2158 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2159 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2160 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2162 2005-01-19 Fred Fish <fnf@specifixinc.com>
2164 * mips.h (struct mips_opcode): Add new pinfo2 member.
2165 (INSN_ALIAS): New define for opcode table entries that are
2166 specific instances of another entry, such as 'move' for an 'or'
2167 with a zero operand.
2168 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2169 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2171 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2173 * mips.h (CPU_RM9000): Define.
2174 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2176 2004-11-25 Jan Beulich <jbeulich@novell.com>
2178 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2179 to/from test registers are illegal in 64-bit mode. Add missing
2180 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2181 (previously one had to explicitly encode a rex64 prefix). Re-enable
2182 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2183 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2185 2004-11-23 Jan Beulich <jbeulich@novell.com>
2187 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2188 available only with SSE2. Change the MMX additions introduced by SSE
2189 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2190 instructions by their now designated identifier (since combining i686
2191 and 3DNow! does not really imply 3DNow!A).
2193 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2195 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2196 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2198 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2199 Vineet Sharma <vineets@noida.hcltech.com>
2201 * maxq.h: New file: Disassembly information for the maxq port.
2203 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2205 * i386.h (i386_optab): Put back "movzb".
2207 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2209 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2210 comments. Remove member cris_ver_sim. Add members
2211 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2212 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2213 (struct cris_support_reg, struct cris_cond15): New types.
2214 (cris_conds15): Declare.
2215 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2216 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2217 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2218 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2219 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2220 SIZE_FIELD_UNSIGNED.
2222 2004-11-04 Jan Beulich <jbeulich@novell.com>
2224 * i386.h (sldx_Suf): Remove.
2225 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2226 (q_FP): Define, implying no REX64.
2227 (x_FP, sl_FP): Imply FloatMF.
2228 (i386_optab): Split reg and mem forms of moving from segment registers
2229 so that the memory forms can ignore the 16-/32-bit operand size
2230 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2231 all non-floating-point instructions. Unite 32- and 64-bit forms of
2232 movsx, movzx, and movd. Adjust floating point operations for the above
2233 changes to the *FP macros. Add DefaultSize to floating point control
2234 insns operating on larger memory ranges. Remove left over comments
2235 hinting at certain insns being Intel-syntax ones where the ones
2236 actually meant are already gone.
2238 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2240 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2243 2004-09-30 Paul Brook <paul@codesourcery.com>
2245 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2246 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2248 2004-09-11 Theodore A. Roth <troth@openavr.org>
2250 * avr.h: Add support for
2251 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2253 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2255 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2257 2004-08-24 Dmitry Diky <diwil@spec.ru>
2259 * msp430.h (msp430_opc): Add new instructions.
2260 (msp430_rcodes): Declare new instructions.
2261 (msp430_hcodes): Likewise..
2263 2004-08-13 Nick Clifton <nickc@redhat.com>
2266 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2269 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2271 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2273 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2275 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2277 2004-07-21 Jan Beulich <jbeulich@novell.com>
2279 * i386.h: Adjust instruction descriptions to better match the
2282 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2284 * arm.h: Remove all old content. Replace with architecture defines
2285 from gas/config/tc-arm.c.
2287 2004-07-09 Andreas Schwab <schwab@suse.de>
2289 * m68k.h: Fix comment.
2291 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2295 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2297 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2299 2004-05-24 Peter Barada <peter@the-baradas.com>
2301 * m68k.h: Add 'size' to m68k_opcode.
2303 2004-05-05 Peter Barada <peter@the-baradas.com>
2305 * m68k.h: Switch from ColdFire chip name to core variant.
2307 2004-04-22 Peter Barada <peter@the-baradas.com>
2309 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2310 descriptions for new EMAC cases.
2311 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2312 handle Motorola MAC syntax.
2313 Allow disassembly of ColdFire V4e object files.
2315 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2317 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2319 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2321 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2323 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2325 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2327 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2329 * i386.h (i386_optab): Added xstore/xcrypt insns.
2331 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2333 * h8300.h (32bit ldc/stc): Add relaxing support.
2335 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2337 * h8300.h (BITOP): Pass MEMRELAX flag.
2339 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2341 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2344 For older changes see ChangeLog-9103
2346 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2348 Copying and distribution of this file, with or without modification,
2349 are permitted in any medium without royalty provided the copyright
2350 notice and this notice are preserved.
2356 version-control: never
projects / deliverable / binutils-gdb.git / blob