include/opcode/ChangeLog

   1 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   2
   3         * arm.h (ARM_EXT_MP): Add.
   4         (ARM_ARCH_V7A_MP): Likewise.
   5
   6 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * bfin.h: Declare pseudoChr structs/defines.
   9
  10 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * bfin.h: Strip trailing whitespace.
  13
  14 2010-07-29  DJ Delorie  <dj@redhat.com>
  15
  16         * rx.h (RX_Operand_Type): Add TwoReg.
  17         (RX_Opcode_ID): Remove ediv and ediv2.
  18
  19 2010-07-27  DJ Delorie  <dj@redhat.com>
  20
  21         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
  22
  23 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
  24             Ina Pandit  <ina.pandit@kpitcummins.com>
  25
  26         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
  27         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
  28         PROCESSOR_V850E2_ALL.
  29         Remove PROCESSOR_V850EA support.
  30         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
  31         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
  32         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
  33         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
  34         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
  35         V850_OPERAND_PERCENT.
  36         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
  37         V850_NOT_R0.
  38         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
  39         and V850E_PUSH_POP
  40
  41 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
  42
  43         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
  44         (MIPS16_INSN_BRANCH): Rename to...
  45         (MIPS16_INSN_COND_BRANCH): ... this.
  46
  47 2010-07-03  Alan Modra  <amodra@gmail.com>
  48
  49         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
  50         Renumber other PPC_OPCODE defines.
  51
  52 2010-07-03  Alan Modra  <amodra@gmail.com>
  53
  54         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
  55
  56 2010-06-29  Alan Modra  <amodra@gmail.com>
  57
  58         * maxq.h: Delete file.
  59
  60 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
  61
  62         * ppc.h (PPC_OPCODE_E500): Define.
  63
  64 2010-05-26  Catherine Moore  <clm@codesourcery.com>
  65
  66         * opcode/mips.h (INSN_MIPS16): Remove.
  67
  68 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
  69
  70         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
  71
  72 2010-04-15  Nick Clifton  <nickc@redhat.com>
  73
  74         * alpha.h: Update copyright notice to use GPLv3.
  75         * arc.h: Likewise.
  76         * arm.h: Likewise.
  77         * avr.h: Likewise.
  78         * bfin.h: Likewise.
  79         * cgen.h: Likewise.
  80         * convex.h: Likewise.
  81         * cr16.h: Likewise.
  82         * cris.h: Likewise.
  83         * crx.h: Likewise.
  84         * d10v.h: Likewise.
  85         * d30v.h: Likewise.
  86         * dlx.h: Likewise.
  87         * h8300.h: Likewise.
  88         * hppa.h: Likewise.
  89         * i370.h: Likewise.
  90         * i386.h: Likewise.
  91         * i860.h: Likewise.
  92         * i960.h: Likewise.
  93         * ia64.h: Likewise.
  94         * m68hc11.h: Likewise.
  95         * m68k.h: Likewise.
  96         * m88k.h: Likewise.
  97         * maxq.h: Likewise.
  98         * mips.h: Likewise.
  99         * mmix.h: Likewise.
 100         * mn10200.h: Likewise.
 101         * mn10300.h: Likewise.
 102         * msp430.h: Likewise.
 103         * np1.h: Likewise.
 104         * ns32k.h: Likewise.
 105         * or32.h: Likewise.
 106         * pdp11.h: Likewise.
 107         * pj.h: Likewise.
 108         * pn.h: Likewise.
 109         * ppc.h: Likewise.
 110         * pyr.h: Likewise.
 111         * rx.h: Likewise.
 112         * s390.h: Likewise.
 113         * score-datadep.h: Likewise.
 114         * score-inst.h: Likewise.
 115         * sparc.h: Likewise.
 116         * spu-insns.h: Likewise.
 117         * spu.h: Likewise.
 118         * tic30.h: Likewise.
 119         * tic4x.h: Likewise.
 120         * tic54x.h: Likewise.
 121         * tic80.h: Likewise.
 122         * v850.h: Likewise.
 123         * vax.h: Likewise.
 124
 125 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 126
 127         * tic6x-control-registers.h, tic6x-insn-formats.h,
 128         tic6x-opcode-table.h, tic6x.h: New.
 129
 130 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 131
 132         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 133
 134 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 135
 136         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 137
 138 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         * ia64.h (ia64_find_opcode): Remove argument name.
 141         (ia64_find_next_opcode): Likewise.
 142         (ia64_dis_opcode): Likewise.
 143         (ia64_free_opcode): Likewise.
 144         (ia64_find_dependency): Likewise.
 145
 146 2009-11-22  Doug Evans  <dje@sebabeach.org>
 147
 148         * cgen.h: Include bfd_stdint.h.
 149         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 150
 151 2009-11-18  Paul Brook  <paul@codesourcery.com>
 152
 153         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 154
 155 2009-11-17  Paul Brook  <paul@codesourcery.com>
 156         Daniel Jacobowitz  <dan@codesourcery.com>
 157
 158         * arm.h (ARM_EXT_V6_DSP): Define.
 159         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 160         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 161
 162 2009-11-04  DJ Delorie  <dj@redhat.com>
 163
 164         * rx.h (rx_decode_opcode) (mvtipl): Add.
 165         (mvtcp, mvfcp, opecp): Remove.
 166
 167 2009-11-02  Paul Brook  <paul@codesourcery.com>
 168
 169         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 170         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 171         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 172         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 173         FPU_ARCH_NEON_VFP_V4): Define.
 174
 175 2009-10-23  Doug Evans  <dje@sebabeach.org>
 176
 177         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 178         * cgen.h: Update.  Improve multi-inclusion macro name.
 179
 180 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 181
 182         * ppc.h (PPC_OPCODE_476): Define.
 183
 184 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 185
 186         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 187
 188 2009-09-29  DJ Delorie  <dj@redhat.com>
 189
 190         * rx.h: New file.
 191
 192 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 193
 194         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 195
 196 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 197
 198         * ppc.h (PPC_OPCODE_PPCA2): New.
 199
 200 2009-09-05  Martin Thuresson  <martin@mtme.org>
 201
 202         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 203
 204 2009-08-29  Martin Thuresson  <martin@mtme.org>
 205
 206         * tic30.h (template): Rename type template to
 207         insn_template. Updated code to use new name.
 208         * tic54x.h (template): Rename type template to
 209         insn_template.
 210
 211 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 212
 213         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 214
 215 2009-06-11  Anthony Green  <green@moxielogic.com>
 216
 217         * moxie.h (MOXIE_F3_PCREL): Define.
 218         (moxie_form3_opc_info): Grow.
 219
 220 2009-06-06  Anthony Green  <green@moxielogic.com>
 221
 222         * moxie.h (MOXIE_F1_M): Define.
 223
 224 2009-04-15  Anthony Green  <green@moxielogic.com>
 225
 226         * moxie.h: Created.
 227
 228 2009-04-06  DJ Delorie  <dj@redhat.com>
 229
 230         * h8300.h: Add relaxation attributes to MOVA opcodes.
 231
 232 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 233
 234         * ppc.h (ppc_parse_cpu): Declare.
 235
 236 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 237
 238         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 239         and _IMM11 for mbitclr and mbitset.
 240         * score-datadep.h: Update dependency information.
 241
 242 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 243
 244         * ppc.h (PPC_OPCODE_POWER7): New.
 245
 246 2009-02-06  Doug Evans  <dje@google.com>
 247
 248         * i386.h: Add comment regarding sse* insns and prefixes.
 249
 250 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 251
 252         * mips.h (INSN_XLR): Define.
 253         (INSN_CHIP_MASK): Update.
 254         (CPU_XLR): Define.
 255         (OPCODE_IS_MEMBER): Update.
 256         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 257
 258 2009-01-28  Doug Evans  <dje@google.com>
 259
 260         * opcode/i386.h: Add multiple inclusion protection.
 261         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 262         (EDI_REG_NUM): New macros.
 263         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 264         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 265         (REX_PREFIX_P): New macro.
 266
 267 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 268
 269         * ppc.h (struct powerpc_opcode): New field "deprecated".
 270         (PPC_OPCODE_NOPOWER4): Delete.
 271
 272 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 273
 274         * mips.h: Define CPU_R14000, CPU_R16000.
 275         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 276
 277 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 278
 279         * arm.h (FPU_NEON_FP16): New.
 280         (FPU_ARCH_NEON_FP16): New.
 281
 282 2008-11-06  Chao-ying Fu  <fu@mips.com>
 283
 284         * mips.h: Doucument '1' for 5-bit sync type.
 285
 286 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 289         IA64_RS_CR.
 290
 291 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 292
 293         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 294
 295 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 296
 297         * ppc.h (PPC_OPCODE_405): Define.
 298         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 299
 300 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 301
 302         * ppc.h (ppc_cpu_t): New typedef.
 303         (struct powerpc_opcode <flags>): Use it.
 304         (struct powerpc_operand <insert, extract>): Likewise.
 305         (struct powerpc_macro <flags>): Likewise.
 306
 307 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 308
 309         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 310         Update comment before MIPS16 field descriptors to mention MIPS16.
 311         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 312         BBIT.
 313         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 314         New bit masks and shift counts for cins and exts.
 315
 316         * mips.h: Document new field descriptors +Q.
 317         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 318
 319 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 320
 321         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 322         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 323
 324 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 325
 326         * ppc.h: (PPC_OPCODE_E500MC): New.
 327
 328 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         * i386.h (MAX_OPERANDS): Set to 5.
 331         (MAX_MNEM_SIZE): Changed to 20.
 332
 333 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 334
 335         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 336
 337 2008-03-09  Paul Brook  <paul@codesourcery.com>
 338
 339         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 340
 341 2008-03-04  Paul Brook  <paul@codesourcery.com>
 342
 343         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 344         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 345         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 346
 347 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 348             Nick Clifton  <nickc@redhat.com>
 349
 350         PR 3134
 351         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 352         with a 32-bit displacement but without the top bit of the 4th byte
 353         set.
 354
 355 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 356
 357         * cr16.h (cr16_num_optab): Declared.
 358
 359 2008-02-14  Hakan Ardo  <hakan@debian.org>
 360
 361         PR gas/2626
 362         * avr.h (AVR_ISA_2xxe): Define.
 363
 364 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 365
 366         * mips.h: Update copyright.
 367         (INSN_CHIP_MASK): New macro.
 368         (INSN_OCTEON): New macro.
 369         (CPU_OCTEON): New macro.
 370         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 371
 372 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 373
 374         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 375
 376 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 377
 378         * avr.h (AVR_ISA_USB162): Add new opcode set.
 379         (AVR_ISA_AVR3): Likewise.
 380
 381 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 382
 383         * mips.h (INSN_LOONGSON_2E): New.
 384         (INSN_LOONGSON_2F): New.
 385         (CPU_LOONGSON_2E): New.
 386         (CPU_LOONGSON_2F): New.
 387         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 388
 389 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 390
 391         * mips.h (INSN_ISA*): Redefine certain values as an
 392         enumeration.  Update comments.
 393         (mips_isa_table): New.
 394         (ISA_MIPS*): Redefine to match enumeration.
 395         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 396         values.
 397
 398 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 399
 400         * ppc.h (PPC_OPCODE_PPCPS): New.
 401
 402 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 403
 404         * m68k.h: Document j K & E.
 405
 406 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 407
 408         * cr16.h: New file for CR16 target.
 409
 410 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 411
 412         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 413
 414 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 415
 416         * m68k.h (mcfisa_c): New.
 417         (mcfusp, mcf_mask): Adjust.
 418
 419 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 420
 421         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 422         (num_powerpc_operands): Declare.
 423         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 424         (PPC_OPERAND_PLUS1): Define.
 425
 426 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 427
 428         * i386.h (REX_MODE64): Renamed to ...
 429         (REX_W): This.
 430         (REX_EXTX): Renamed to ...
 431         (REX_R): This.
 432         (REX_EXTY): Renamed to ...
 433         (REX_X): This.
 434         (REX_EXTZ): Renamed to ...
 435         (REX_B): This.
 436
 437 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * i386.h: Add entries from config/tc-i386.h and move tables
 440         to opcodes/i386-opc.h.
 441
 442 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386.h (FloatDR): Removed.
 445         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 446
 447 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 448
 449         * spu-insns.h: Add soma double-float insns.
 450
 451 2007-02-20  Thiemo Seufer  <ths@mips.com>
 452             Chao-Ying Fu  <fu@mips.com>
 453
 454         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 455         (INSN_DSPR2): Add flag for DSP R2 instructions.
 456         (M_BALIGN): New macro.
 457
 458 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 459
 460         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 461         and Seg3ShortFrom with Shortform.
 462
 463 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         PR gas/4027
 466         * i386.h (i386_optab): Put the real "test" before the pseudo
 467         one.
 468
 469 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 470
 471         * m68k.h (m68010up): OR fido_a.
 472
 473 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 474
 475         * m68k.h (fido_a): New.
 476
 477 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 478
 479         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 480         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 481         values.
 482
 483 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 486
 487 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 488
 489         * score-inst.h (enum score_insn_type): Add Insn_internal.
 490
 491 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 492             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 493             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 494             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 495             Alan Modra  <amodra@bigpond.net.au>
 496
 497         * spu-insns.h: New file.
 498         * spu.h: New file.
 499
 500 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 501
 502         * ppc.h (PPC_OPCODE_CELL): Define.
 503
 504 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 505
 506         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 507         in amdfam10 architecture.
 508
 509 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386.h: Replace CpuMNI with CpuSSSE3.
 512
 513 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 514             Joseph Myers  <joseph@codesourcery.com>
 515             Ian Lance Taylor  <ian@wasabisystems.com>
 516             Ben Elliston  <bje@wasabisystems.com>
 517
 518         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 519
 520 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 521
 522         * score-datadep.h: New file.
 523         * score-inst.h: New file.
 524
 525 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 528         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 529         movdq2q and movq2dq.
 530
 531 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 532            Michael Meissner             <michael.meissner@amd.com>
 533
 534         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 535
 536 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         * i386.h (i386_optab): Add "nop" with memory reference.
 539
 540 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * i386.h (i386_optab): Update comment for 64bit NOP.
 543
 544 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 545             Anton Blanchard  <anton@samba.org>
 546
 547         * ppc.h (PPC_OPCODE_POWER6): Define.
 548         Adjust whitespace.
 549
 550 2006-06-05  Thiemo Seufer  <ths@mips.com>
 551
 552         * mips.h: Improve description of MT flags.
 553
 554 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 555
 556         * m68k.h (mcf_mask): Define.
 557
 558 2006-05-05  Thiemo Seufer  <ths@mips.com>
 559             David Ung  <davidu@mips.com>
 560
 561         * mips.h (enum): Add macro M_CACHE_AB.
 562
 563 2006-05-04  Thiemo Seufer  <ths@mips.com>
 564             Nigel Stephens  <nigel@mips.com>
 565             David Ung  <davidu@mips.com>
 566
 567         * mips.h: Add INSN_SMARTMIPS define.
 568
 569 2006-04-30  Thiemo Seufer  <ths@mips.com>
 570             David Ung  <davidu@mips.com>
 571
 572         * mips.h: Defines udi bits and masks.  Add description of
 573         characters which may appear in the args field of udi
 574         instructions.
 575
 576 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 577
 578         * mips.h: Improve comments describing the bitfield instruction
 579         fields.
 580
 581 2006-04-26  Julian Brown  <julian@codesourcery.com>
 582
 583         * arm.h (FPU_VFP_EXT_V3): Define constant.
 584         (FPU_NEON_EXT_V1): Likewise.
 585         (FPU_VFP_HARD): Update.
 586         (FPU_VFP_V3): Define macro.
 587         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 588
 589 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 590
 591         * avr.h (AVR_ISA_PWMx): New.
 592
 593 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 594
 595         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 596         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 597         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 598         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 599         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 600
 601 2006-03-10  Paul Brook  <paul@codesourcery.com>
 602
 603         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 604
 605 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 606
 607         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 608         first.  Correct mask of bb "B" opcode.
 609
 610 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 611
 612         * i386.h (i386_optab): Support Intel Merom New Instructions.
 613
 614 2006-02-24  Paul Brook  <paul@codesourcery.com>
 615
 616         * arm.h: Add V7 feature bits.
 617
 618 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 621
 622 2006-01-31  Paul Brook  <paul@codesourcery.com>
 623         Richard Earnshaw <rearnsha@arm.com>
 624
 625         * arm.h: Use ARM_CPU_FEATURE.
 626         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 627         (arm_feature_set): Change to a structure.
 628         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 629         ARM_FEATURE): New macros.
 630
 631 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 632
 633         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 634         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 635         (ADD_PC_INCR_OPCODE): Don't define.
 636
 637 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         PR gas/1874
 640         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 641
 642 2005-11-14  David Ung  <davidu@mips.com>
 643
 644         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 645         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 646         save/restore encoding of the args field.
 647
 648 2005-10-28  Dave Brolley  <brolley@redhat.com>
 649
 650         Contribute the following changes:
 651         2005-02-16  Dave Brolley  <brolley@redhat.com>
 652
 653         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 654         cgen_isa_mask_* to cgen_bitset_*.
 655         * cgen.h: Likewise.
 656
 657         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 658
 659         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 660         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 661         (CGEN_CPU_TABLE): Make isas a ponter.
 662
 663         2003-09-29  Dave Brolley  <brolley@redhat.com>
 664
 665         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 666         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 667         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 668
 669         2002-12-13  Dave Brolley  <brolley@redhat.com>
 670
 671         * cgen.h (symcat.h): #include it.
 672         (cgen-bitset.h): #include it.
 673         (CGEN_ATTR_VALUE_TYPE): Now a union.
 674         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 675         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 676         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 677         * cgen-bitset.h: New file.
 678
 679 2005-09-30  Catherine Moore  <clm@cm00re.com>
 680
 681         * bfin.h: New file.
 682
 683 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 684
 685         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 686         indirect operands.
 687
 688 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 689
 690         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 691         Add FLAG_STRICT to pa10 ftest opcode.
 692
 693 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 694
 695         * hppa.h (pa_opcodes): Remove lha entries.
 696
 697 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 698
 699         * hppa.h (FLAG_STRICT): Revise comment.
 700         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 701         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 702         entries for "fdc".
 703
 704 2005-09-30  Catherine Moore  <clm@cm00re.com>
 705
 706         * bfin.h: New file.
 707
 708 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 709
 710         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 711
 712 2005-09-06  Chao-ying Fu  <fu@mips.com>
 713
 714         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 715         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 716         define.
 717         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 718         (INSN_ASE_MASK): Update to include INSN_MT.
 719         (INSN_MT): New define for MT ASE.
 720
 721 2005-08-25  Chao-ying Fu  <fu@mips.com>
 722
 723         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 724         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 725         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 726         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 727         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 728         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 729         instructions.
 730         (INSN_DSP): New define for DSP ASE.
 731
 732 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 733
 734         * a29k.h: Delete.
 735
 736 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 737
 738         * ppc.h (PPC_OPCODE_E300): Define.
 739
 740 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 741
 742         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 743
 744 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 745
 746         PR gas/336
 747         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 748         and pitlb.
 749
 750 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 751
 752         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 753         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 754         Add movq-s as 64-bit variants of movd-s.
 755
 756 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 757
 758         * hppa.h: Fix punctuation in comment.
 759
 760         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 761         implicit space-register addressing.  Set space-register bits on opcodes
 762         using implicit space-register addressing.  Add various missing pa20
 763         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 764         space-register addressing.  Use "fE" instead of "fe" in various
 765         fstw opcodes.
 766
 767 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 768
 769         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 770
 771 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 772
 773         * i386.h (i386_optab): Support Intel VMX Instructions.
 774
 775 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 776
 777         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 778
 779 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 780
 781         * i386.h (i386_optab): Add new insns.
 782
 783 2005-07-01  Nick Clifton  <nickc@redhat.com>
 784
 785         * sparc.h: Add typedefs to structure declarations.
 786
 787 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         PR 1013
 790         * i386.h (i386_optab): Update comments for 64bit addressing on
 791         mov. Allow 64bit addressing for mov and movq.
 792
 793 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 794
 795         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 796         respectively, in various floating-point load and store patterns.
 797
 798 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 799
 800         * hppa.h (FLAG_STRICT): Correct comment.
 801         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 802         PA 2.0 mneumonics when equivalent.  Entries with cache control
 803         completers now require PA 1.1.  Adjust whitespace.
 804
 805 2005-05-19  Anton Blanchard  <anton@samba.org>
 806
 807         * ppc.h (PPC_OPCODE_POWER5): Define.
 808
 809 2005-05-10  Nick Clifton  <nickc@redhat.com>
 810
 811         * Update the address and phone number of the FSF organization in
 812         the GPL notices in the following files:
 813         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 814         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 815         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 816         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 817         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 818         tic54x.h, tic80.h, v850.h, vax.h
 819
 820 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 821
 822         * i386.h (i386_optab): Add ht and hnt.
 823
 824 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 825
 826         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 827         Add xcrypt-ctr.  Provide aliases without hyphens.
 828
 829 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         Moved from ../ChangeLog
 832
 833         2005-04-12  Paul Brook  <paul@codesourcery.com>
 834         * m88k.h: Rename psr macros to avoid conflicts.
 835
 836         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 837         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 838         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 839         and ARM_ARCH_V6ZKT2.
 840
 841         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 842         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 843         Remove redundant instruction types.
 844         (struct argument): X_op - new field.
 845         (struct cst4_entry): Remove.
 846         (no_op_insn): Declare.
 847
 848         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 849         * crx.h (enum argtype): Rename types, remove unused types.
 850
 851         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 852         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 853         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 854         (enum operand_type): Rearrange operands, edit comments.
 855         replace us<N> with ui<N> for unsigned immediate.
 856         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 857         displacements (respectively).
 858         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 859         (instruction type): Add NO_TYPE_INS.
 860         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 861         (operand_entry): New field - 'flags'.
 862         (operand flags): New.
 863
 864         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 865         * crx.h (operand_type): Remove redundant types i3, i4,
 866         i5, i8, i12.
 867         Add new unsigned immediate types us3, us4, us5, us16.
 868
 869 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 870
 871         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 872         adjust them accordingly.
 873
 874 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 875
 876         * i386.h (i386_optab): Add rdtscp.
 877
 878 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 881         between memory and segment register. Allow movq for moving between
 882         general-purpose register and segment register.
 883
 884 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 885
 886         PR gas/707
 887         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 888         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 889         fnstsw.
 890
 891 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 892
 893         * m68k.h (m68008, m68ec030, m68882): Remove.
 894         (m68k_mask): New.
 895         (cpu_m68k, cpu_cf): New.
 896         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 897         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 898
 899 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 900
 901         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 902         * cgen.h (enum cgen_parse_operand_type): Add
 903         CGEN_PARSE_OPERAND_SYMBOLIC.
 904
 905 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 906
 907         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 908         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 909         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 910
 911 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 912
 913         * mips.h (struct mips_opcode): Add new pinfo2 member.
 914         (INSN_ALIAS): New define for opcode table entries that are
 915         specific instances of another entry, such as 'move' for an 'or'
 916         with a zero operand.
 917         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 918         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 919
 920 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 921
 922         * mips.h (CPU_RM9000): Define.
 923         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 924
 925 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 926
 927         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 928         to/from test registers are illegal in 64-bit mode. Add missing
 929         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 930         (previously one had to explicitly encode a rex64 prefix). Re-enable
 931         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 932         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 933
 934 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 935
 936         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 937         available only with SSE2. Change the MMX additions introduced by SSE
 938         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 939         instructions by their now designated identifier (since combining i686
 940         and 3DNow! does not really imply 3DNow!A).
 941
 942 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 943
 944         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 945         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 946
 947 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 948             Vineet Sharma      <vineets@noida.hcltech.com>
 949
 950         * maxq.h: New file: Disassembly information for the maxq port.
 951
 952 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386.h (i386_optab): Put back "movzb".
 955
 956 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 957
 958         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 959         comments.  Remove member cris_ver_sim.  Add members
 960         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 961         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 962         (struct cris_support_reg, struct cris_cond15): New types.
 963         (cris_conds15): Declare.
 964         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 965         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 966         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 967         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 968         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 969         SIZE_FIELD_UNSIGNED.
 970
 971 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 972
 973         * i386.h (sldx_Suf): Remove.
 974         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 975         (q_FP): Define, implying no REX64.
 976         (x_FP, sl_FP): Imply FloatMF.
 977         (i386_optab): Split reg and mem forms of moving from segment registers
 978         so that the memory forms can ignore the 16-/32-bit operand size
 979         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 980         all non-floating-point instructions. Unite 32- and 64-bit forms of
 981         movsx, movzx, and movd. Adjust floating point operations for the above
 982         changes to the *FP macros. Add DefaultSize to floating point control
 983         insns operating on larger memory ranges. Remove left over comments
 984         hinting at certain insns being Intel-syntax ones where the ones
 985         actually meant are already gone.
 986
 987 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 988
 989         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 990         instruction type.
 991
 992 2004-09-30  Paul Brook  <paul@codesourcery.com>
 993
 994         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 995         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 996
 997 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 998
 999         * avr.h: Add support for
1000         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1001
1002 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1003
1004         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1005
1006 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1007
1008         * msp430.h (msp430_opc): Add new instructions.
1009         (msp430_rcodes): Declare new instructions.
1010         (msp430_hcodes): Likewise..
1011
1012 2004-08-13  Nick Clifton  <nickc@redhat.com>
1013
1014         PR/301
1015         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1016         processors.
1017
1018 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1019
1020         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1021
1022 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1023
1024         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1025
1026 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1027
1028         * i386.h: Adjust instruction descriptions to better match the
1029         specification.
1030
1031 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1032
1033         * arm.h: Remove all old content.  Replace with architecture defines
1034         from gas/config/tc-arm.c.
1035
1036 2004-07-09  Andreas Schwab  <schwab@suse.de>
1037
1038         * m68k.h: Fix comment.
1039
1040 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1041
1042         * crx.h: New file.
1043
1044 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1045
1046         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1047
1048 2004-05-24  Peter Barada  <peter@the-baradas.com>
1049
1050         * m68k.h: Add 'size' to m68k_opcode.
1051
1052 2004-05-05  Peter Barada  <peter@the-baradas.com>
1053
1054         * m68k.h: Switch from ColdFire chip name to core variant.
1055
1056 2004-04-22  Peter Barada  <peter@the-baradas.com>
1057
1058         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1059         descriptions for new EMAC cases.
1060         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1061         handle Motorola MAC syntax.
1062         Allow disassembly of ColdFire V4e object files.
1063
1064 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1065
1066         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1067
1068 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1069
1070         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1071
1072 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1073
1074         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1075
1076 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1077
1078         * i386.h (i386_optab): Added xstore/xcrypt insns.
1079
1080 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1081
1082         * h8300.h (32bit ldc/stc): Add relaxing support.
1083
1084 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1085
1086         * h8300.h (BITOP): Pass MEMRELAX flag.
1087
1088 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1089
1090         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1091         except for the H8S.
1092
1093 For older changes see ChangeLog-9103
1094 \f
1095 Local Variables:
1096 mode: change-log
1097 left-margin: 8
1098 fill-column: 74
1099 version-control: never
1100 End: