1 2005-10-24 Jan Beulich <jbeulich@novell.com>
3 * ia64.h (enum ia64_opnd): Move memory operand out of set of
6 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
8 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
9 Add FLAG_STRICT to pa10 ftest opcode.
11 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
13 * hppa.h (pa_opcodes): Remove lha entries.
15 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
17 * hppa.h (FLAG_STRICT): Revise comment.
18 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
19 before corresponding pa11 opcodes. Add strict pa10 register-immediate
22 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
24 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
26 2005-09-06 Chao-ying Fu <fu@mips.com>
28 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
29 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
31 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
32 (INSN_ASE_MASK): Update to include INSN_MT.
33 (INSN_MT): New define for MT ASE.
35 2005-08-25 Chao-ying Fu <fu@mips.com>
37 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
38 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
39 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
40 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
41 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
42 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
44 (INSN_DSP): New define for DSP ASE.
46 2005-08-18 Alan Modra <amodra@bigpond.net.au>
50 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
52 * ppc.h (PPC_OPCODE_E300): Define.
54 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
56 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
58 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
61 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
64 2005-07-27 Jan Beulich <jbeulich@novell.com>
66 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
67 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
68 Add movq-s as 64-bit variants of movd-s.
70 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
72 * hppa.h: Fix punctuation in comment.
74 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
75 implicit space-register addressing. Set space-register bits on opcodes
76 using implicit space-register addressing. Add various missing pa20
77 long-immediate opcodes. Remove various opcodes using implicit 3-bit
78 space-register addressing. Use "fE" instead of "fe" in various
81 2005-07-18 Jan Beulich <jbeulich@novell.com>
83 * i386.h (i386_optab): Operands of aam and aad are unsigned.
85 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
87 * i386.h (i386_optab): Support Intel VMX Instructions.
89 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
91 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
93 2005-07-05 Jan Beulich <jbeulich@novell.com>
95 * i386.h (i386_optab): Add new insns.
97 2005-07-01 Nick Clifton <nickc@redhat.com>
99 * sparc.h: Add typedefs to structure declarations.
101 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
104 * i386.h (i386_optab): Update comments for 64bit addressing on
105 mov. Allow 64bit addressing for mov and movq.
107 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
109 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
110 respectively, in various floating-point load and store patterns.
112 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
114 * hppa.h (FLAG_STRICT): Correct comment.
115 (pa_opcodes): Update load and store entries to allow both PA 1.X and
116 PA 2.0 mneumonics when equivalent. Entries with cache control
117 completers now require PA 1.1. Adjust whitespace.
119 2005-05-19 Anton Blanchard <anton@samba.org>
121 * ppc.h (PPC_OPCODE_POWER5): Define.
123 2005-05-10 Nick Clifton <nickc@redhat.com>
125 * Update the address and phone number of the FSF organization in
126 the GPL notices in the following files:
127 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
128 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
129 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
130 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
131 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
132 tic54x.h, tic80.h, v850.h, vax.h
134 2005-05-09 Jan Beulich <jbeulich@novell.com>
136 * i386.h (i386_optab): Add ht and hnt.
138 2005-04-18 Mark Kettenis <kettenis@gnu.org>
140 * i386.h: Insert hyphens into selected VIA PadLock extensions.
141 Add xcrypt-ctr. Provide aliases without hyphens.
143 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
145 Moved from ../ChangeLog
147 2005-04-12 Paul Brook <paul@codesourcery.com>
148 * m88k.h: Rename psr macros to avoid conflicts.
150 2005-03-12 Zack Weinberg <zack@codesourcery.com>
151 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
152 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
155 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
156 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
157 Remove redundant instruction types.
158 (struct argument): X_op - new field.
159 (struct cst4_entry): Remove.
160 (no_op_insn): Declare.
162 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
163 * crx.h (enum argtype): Rename types, remove unused types.
165 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
166 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
167 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
168 (enum operand_type): Rearrange operands, edit comments.
169 replace us<N> with ui<N> for unsigned immediate.
170 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
171 displacements (respectively).
172 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
173 (instruction type): Add NO_TYPE_INS.
174 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
175 (operand_entry): New field - 'flags'.
176 (operand flags): New.
178 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
179 * crx.h (operand_type): Remove redundant types i3, i4,
181 Add new unsigned immediate types us3, us4, us5, us16.
183 2005-04-12 Mark Kettenis <kettenis@gnu.org>
185 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
186 adjust them accordingly.
188 2005-04-01 Jan Beulich <jbeulich@novell.com>
190 * i386.h (i386_optab): Add rdtscp.
192 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
194 * i386.h (i386_optab): Don't allow the `l' suffix for moving
195 between memory and segment register. Allow movq for moving between
196 general-purpose register and segment register.
198 2005-02-09 Jan Beulich <jbeulich@novell.com>
201 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
202 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
205 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
207 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
208 * cgen.h (enum cgen_parse_operand_type): Add
209 CGEN_PARSE_OPERAND_SYMBOLIC.
211 2005-01-21 Fred Fish <fnf@specifixinc.com>
213 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
214 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
215 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
217 2005-01-19 Fred Fish <fnf@specifixinc.com>
219 * mips.h (struct mips_opcode): Add new pinfo2 member.
220 (INSN_ALIAS): New define for opcode table entries that are
221 specific instances of another entry, such as 'move' for an 'or'
223 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
224 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
226 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
228 * mips.h (CPU_RM9000): Define.
229 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
231 2004-11-25 Jan Beulich <jbeulich@novell.com>
233 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
234 to/from test registers are illegal in 64-bit mode. Add missing
235 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
236 (previously one had to explicitly encode a rex64 prefix). Re-enable
237 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
238 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
240 2004-11-23 Jan Beulich <jbeulich@novell.com>
242 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
243 available only with SSE2. Change the MMX additions introduced by SSE
244 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
245 instructions by their now designated identifier (since combining i686
246 and 3DNow! does not really imply 3DNow!A).
248 2004-11-19 Alan Modra <amodra@bigpond.net.au>
250 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
251 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
253 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
254 Vineet Sharma <vineets@noida.hcltech.com>
256 * maxq.h: New file: Disassembly information for the maxq port.
258 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
260 * i386.h (i386_optab): Put back "movzb".
262 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
264 * cris.h (enum cris_insn_version_usage): Tweak formatting and
265 comments. Remove member cris_ver_sim. Add members
266 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
267 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
268 (struct cris_support_reg, struct cris_cond15): New types.
269 (cris_conds15): Declare.
270 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
271 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
272 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
273 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
274 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
277 2004-11-04 Jan Beulich <jbeulich@novell.com>
279 * i386.h (sldx_Suf): Remove.
280 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
281 (q_FP): Define, implying no REX64.
282 (x_FP, sl_FP): Imply FloatMF.
283 (i386_optab): Split reg and mem forms of moving from segment registers
284 so that the memory forms can ignore the 16-/32-bit operand size
285 distinction. Adjust a few others for Intel mode. Remove *FP uses from
286 all non-floating-point instructions. Unite 32- and 64-bit forms of
287 movsx, movzx, and movd. Adjust floating point operations for the above
288 changes to the *FP macros. Add DefaultSize to floating point control
289 insns operating on larger memory ranges. Remove left over comments
290 hinting at certain insns being Intel-syntax ones where the ones
291 actually meant are already gone.
293 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
295 * crx.h: Add COPS_REG_INS - Coprocessor Special register
298 2004-09-30 Paul Brook <paul@codesourcery.com>
300 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
301 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
303 2004-09-11 Theodore A. Roth <troth@openavr.org>
305 * avr.h: Add support for
306 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
308 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
310 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
312 2004-08-24 Dmitry Diky <diwil@spec.ru>
314 * msp430.h (msp430_opc): Add new instructions.
315 (msp430_rcodes): Declare new instructions.
316 (msp430_hcodes): Likewise..
318 2004-08-13 Nick Clifton <nickc@redhat.com>
321 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
324 2004-08-30 Michal Ludvig <mludvig@suse.cz>
326 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
328 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
330 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
332 2004-07-21 Jan Beulich <jbeulich@novell.com>
334 * i386.h: Adjust instruction descriptions to better match the
337 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
339 * arm.h: Remove all old content. Replace with architecture defines
340 from gas/config/tc-arm.c.
342 2004-07-09 Andreas Schwab <schwab@suse.de>
344 * m68k.h: Fix comment.
346 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
350 2004-06-24 Alan Modra <amodra@bigpond.net.au>
352 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
354 2004-05-24 Peter Barada <peter@the-baradas.com>
356 * m68k.h: Add 'size' to m68k_opcode.
358 2004-05-05 Peter Barada <peter@the-baradas.com>
360 * m68k.h: Switch from ColdFire chip name to core variant.
362 2004-04-22 Peter Barada <peter@the-baradas.com>
364 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
365 descriptions for new EMAC cases.
366 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
367 handle Motorola MAC syntax.
368 Allow disassembly of ColdFire V4e object files.
370 2004-03-16 Alan Modra <amodra@bigpond.net.au>
372 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
374 2004-03-12 Jakub Jelinek <jakub@redhat.com>
376 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
378 2004-03-12 Michal Ludvig <mludvig@suse.cz>
380 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
382 2004-03-12 Michal Ludvig <mludvig@suse.cz>
384 * i386.h (i386_optab): Added xstore/xcrypt insns.
386 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
388 * h8300.h (32bit ldc/stc): Add relaxing support.
390 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
392 * h8300.h (BITOP): Pass MEMRELAX flag.
394 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
396 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
399 For older changes see ChangeLog-9103
405 version-control: never