include/opcode/ChangeLog

   1 2012-02-25  Walter Lee  <walt@tilera.com>
   2
   3         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
   4         TILEGX_OPC_LD_TLS.
   5         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
   6         TILEPRO_OPC_LW_TLS_SN.
   7
   8 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
  11         (XRELEASE_PREFIX_OPCODE): Likewise.
  12
  13 2011-12-08  Andrew Pinski  <apinski@cavium.com>
  14             Adam Nemet  <anemet@caviumnetworks.com>
  15
  16         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
  17         (INSN_OCTEON2): New macro.
  18         (CPU_OCTEON2): New macro.
  19         (OPCODE_IS_MEMBER): Add Octeon2.
  20
  21 2011-11-29  Andrew Pinski  <apinski@cavium.com>
  22
  23         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
  24         (INSN_OCTEONP): New macro.
  25         (CPU_OCTEONP): New macro.
  26         (OPCODE_IS_MEMBER): Add Octeon+.
  27         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
  28
  29 2011-11-01  DJ Delorie  <dj@redhat.com>
  30
  31         * rl78.h: New file.
  32
  33 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
  34
  35         * mips.h: Fix a typo in description.
  36
  37 2011-09-21  David S. Miller  <davem@davemloft.net>
  38
  39         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
  40         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
  41         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
  42         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
  43
  44 2011-08-09  Chao-ying Fu  <fu@mips.com>
  45             Maciej W. Rozycki  <macro@codesourcery.com>
  46
  47         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
  48         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
  49         (INSN_ASE_MASK): Add the MCU bit.
  50         (INSN_MCU): New macro.
  51         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
  52         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
  53
  54 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
  55
  56         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
  57         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
  58         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
  59         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
  60         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
  61         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
  62         (INSN2_READ_GPR_MMN): Likewise.
  63         (INSN2_READ_FPR_D): Change the bit used.
  64         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
  65         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
  66         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
  67         (INSN2_COND_BRANCH): Likewise.
  68         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
  69         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
  70         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
  71         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
  72         (INSN2_MOD_GPR_MN): Likewise.
  73
  74 2011-08-05  David S. Miller  <davem@davemloft.net>
  75
  76         * sparc.h: Document new format codes '4', '5', and '('.
  77         (OPF_LOW4, RS3): New macros.
  78
  79 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
  80
  81         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
  82         order of flags documented.
  83
  84 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
  85
  86         * mips.h: Clarify the description of microMIPS instruction
  87         manipulation macros.
  88         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
  89
  90 2011-07-24  Chao-ying Fu  <fu@mips.com>
  91             Maciej W. Rozycki  <macro@codesourcery.com>
  92
  93         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
  94         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
  95         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
  96         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
  97         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
  98         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
  99         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 100         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 101         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 102         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 103         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 104         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 105         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 106         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 107         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 108         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 109         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 110         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 111         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 112         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 113         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 114         (INSN_WRITE_GPR_S): New macro.
 115         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 116         (INSN2_READ_FPR_D): Likewise.
 117         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 118         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 119         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 120         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 121         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 122         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 123         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 124         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 125         (CPU_MICROMIPS): New macro.
 126         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 127         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 128         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 129         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 130         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 131         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 132         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 133         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 134         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 135         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 136         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 137         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 138         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 139         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 140         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 141         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 142         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 143         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 144         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 145         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 146         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 147         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 148         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 149         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 150         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 151         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 152         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 153         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 154         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 155         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 156         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 157         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 158         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 159         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 160         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 161         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 162         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 163         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 164         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 165         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 166         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 167         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 168         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 169         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 170         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 171         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 172         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 173         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 174         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 175         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 176         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 177         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 178         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 179         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 180         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 181         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 182         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 183         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 184         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 185         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 186         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 187         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 188         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 189         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 190         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 191         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 192         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 193         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 194         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 195         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 196         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 197         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 198         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 199         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 200         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 201         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 202         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 203         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 204         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 205         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 206         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 207         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 208         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 209         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 210         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 211         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 212         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 213         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 214         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 215         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 216         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 217         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 218         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 219         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 220         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 221         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 222         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 223         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 224         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 225         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 226         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 227         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 228         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 229         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 230         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 231         (micromips_opcodes): New declaration.
 232         (bfd_micromips_num_opcodes): Likewise.
 233
 234 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 235
 236         * mips.h (INSN_TRAP): Rename to...
 237         (INSN_NO_DELAY_SLOT): ... this.
 238         (INSN_SYNC): Remove macro.
 239
 240 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 241
 242         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 243         a duplicate of AVR_ISA_SPM.
 244
 245 2011-07-01  Nick Clifton  <nickc@redhat.com>
 246
 247         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 248
 249 2011-06-18  Robin Getz  <robin.getz@analog.com>
 250
 251         * bfin.h (is_macmod_signed): New func
 252
 253 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 254
 255         * bfin.h (is_macmod_pmove): Add missing space before func args.
 256         (is_macmod_hmove): Likewise.
 257
 258 2011-06-13  Walter Lee  <walt@tilera.com>
 259
 260         * tilegx.h: New file.
 261         * tilepro.h: New file.
 262
 263 2011-05-31  Paul Brook  <paul@codesourcery.com>
 264
 265         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 266
 267 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 268
 269         * s390.h: Replace S390_OPERAND_REG_EVEN with
 270         S390_OPERAND_REG_PAIR.
 271
 272 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 273
 274         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 275
 276 2011-04-18  Julian Brown  <julian@codesourcery.com>
 277
 278         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 279
 280 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 281
 282         PR gas/12296
 283         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 284
 285 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 286
 287         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 288         New instruction set flags.
 289         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 290
 291 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 292
 293         * mips.h (M_PREF_AB): New enum value.
 294
 295 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 298         M_IU): Define.
 299         (is_macmod_pmove, is_macmod_hmove): New functions.
 300
 301 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 302
 303         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 304
 305 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 306
 307         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 308         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 309
 310 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 311
 312         PR gas/11395
 313         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 314         "bb" entries.
 315
 316 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 317
 318         PR gas/11395
 319         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 320
 321 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 322
 323         * mips.h: Update commentary after last commit.
 324
 325 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 326
 327         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 328         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 329         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 330
 331 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 332
 333         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 334
 335 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 336
 337         * mips.h: Fix previous commit.
 338
 339 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 340
 341         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 342         (INSN_LOONGSON_3A): Clear bit 31.
 343
 344 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 345
 346         PR gas/12198
 347         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 348         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 349         (ARM_ARCH_V6M_ONLY): New define.
 350
 351 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 352
 353         * mips.h (INSN_LOONGSON_3A): Defined.
 354         (CPU_LOONGSON_3A): Defined.
 355         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 356
 357 2010-10-09  Matt Rice  <ratmice@gmail.com>
 358
 359         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 360         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 361
 362 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 363
 364         * arm.h (ARM_EXT_VIRT): New define.
 365         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 366         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 367         Extensions.
 368
 369 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 370
 371         * arm.h (ARM_AEXT_ADIV): New define.
 372         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 373
 374 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 375
 376         * arm.h (ARM_EXT_OS): New define.
 377         (ARM_AEXT_V6SM): Likewise.
 378         (ARM_ARCH_V6SM): Likewise.
 379
 380 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 381
 382         * arm.h (ARM_EXT_MP): Add.
 383         (ARM_ARCH_V7A_MP): Likewise.
 384
 385 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 386
 387         * bfin.h: Declare pseudoChr structs/defines.
 388
 389 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 390
 391         * bfin.h: Strip trailing whitespace.
 392
 393 2010-07-29  DJ Delorie  <dj@redhat.com>
 394
 395         * rx.h (RX_Operand_Type): Add TwoReg.
 396         (RX_Opcode_ID): Remove ediv and ediv2.
 397
 398 2010-07-27  DJ Delorie  <dj@redhat.com>
 399
 400         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 401
 402 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 403             Ina Pandit  <ina.pandit@kpitcummins.com>
 404
 405         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 406         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 407         PROCESSOR_V850E2_ALL.
 408         Remove PROCESSOR_V850EA support.
 409         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 410         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 411         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 412         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 413         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 414         V850_OPERAND_PERCENT.
 415         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 416         V850_NOT_R0.
 417         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 418         and V850E_PUSH_POP
 419
 420 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 421
 422         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 423         (MIPS16_INSN_BRANCH): Rename to...
 424         (MIPS16_INSN_COND_BRANCH): ... this.
 425
 426 2010-07-03  Alan Modra  <amodra@gmail.com>
 427
 428         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 429         Renumber other PPC_OPCODE defines.
 430
 431 2010-07-03  Alan Modra  <amodra@gmail.com>
 432
 433         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 434
 435 2010-06-29  Alan Modra  <amodra@gmail.com>
 436
 437         * maxq.h: Delete file.
 438
 439 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 440
 441         * ppc.h (PPC_OPCODE_E500): Define.
 442
 443 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 444
 445         * opcode/mips.h (INSN_MIPS16): Remove.
 446
 447 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 448
 449         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 450
 451 2010-04-15  Nick Clifton  <nickc@redhat.com>
 452
 453         * alpha.h: Update copyright notice to use GPLv3.
 454         * arc.h: Likewise.
 455         * arm.h: Likewise.
 456         * avr.h: Likewise.
 457         * bfin.h: Likewise.
 458         * cgen.h: Likewise.
 459         * convex.h: Likewise.
 460         * cr16.h: Likewise.
 461         * cris.h: Likewise.
 462         * crx.h: Likewise.
 463         * d10v.h: Likewise.
 464         * d30v.h: Likewise.
 465         * dlx.h: Likewise.
 466         * h8300.h: Likewise.
 467         * hppa.h: Likewise.
 468         * i370.h: Likewise.
 469         * i386.h: Likewise.
 470         * i860.h: Likewise.
 471         * i960.h: Likewise.
 472         * ia64.h: Likewise.
 473         * m68hc11.h: Likewise.
 474         * m68k.h: Likewise.
 475         * m88k.h: Likewise.
 476         * maxq.h: Likewise.
 477         * mips.h: Likewise.
 478         * mmix.h: Likewise.
 479         * mn10200.h: Likewise.
 480         * mn10300.h: Likewise.
 481         * msp430.h: Likewise.
 482         * np1.h: Likewise.
 483         * ns32k.h: Likewise.
 484         * or32.h: Likewise.
 485         * pdp11.h: Likewise.
 486         * pj.h: Likewise.
 487         * pn.h: Likewise.
 488         * ppc.h: Likewise.
 489         * pyr.h: Likewise.
 490         * rx.h: Likewise.
 491         * s390.h: Likewise.
 492         * score-datadep.h: Likewise.
 493         * score-inst.h: Likewise.
 494         * sparc.h: Likewise.
 495         * spu-insns.h: Likewise.
 496         * spu.h: Likewise.
 497         * tic30.h: Likewise.
 498         * tic4x.h: Likewise.
 499         * tic54x.h: Likewise.
 500         * tic80.h: Likewise.
 501         * v850.h: Likewise.
 502         * vax.h: Likewise.
 503
 504 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 505
 506         * tic6x-control-registers.h, tic6x-insn-formats.h,
 507         tic6x-opcode-table.h, tic6x.h: New.
 508
 509 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 510
 511         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 512
 513 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 514
 515         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 516
 517 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         * ia64.h (ia64_find_opcode): Remove argument name.
 520         (ia64_find_next_opcode): Likewise.
 521         (ia64_dis_opcode): Likewise.
 522         (ia64_free_opcode): Likewise.
 523         (ia64_find_dependency): Likewise.
 524
 525 2009-11-22  Doug Evans  <dje@sebabeach.org>
 526
 527         * cgen.h: Include bfd_stdint.h.
 528         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 529
 530 2009-11-18  Paul Brook  <paul@codesourcery.com>
 531
 532         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 533
 534 2009-11-17  Paul Brook  <paul@codesourcery.com>
 535         Daniel Jacobowitz  <dan@codesourcery.com>
 536
 537         * arm.h (ARM_EXT_V6_DSP): Define.
 538         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 539         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 540
 541 2009-11-04  DJ Delorie  <dj@redhat.com>
 542
 543         * rx.h (rx_decode_opcode) (mvtipl): Add.
 544         (mvtcp, mvfcp, opecp): Remove.
 545
 546 2009-11-02  Paul Brook  <paul@codesourcery.com>
 547
 548         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 549         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 550         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 551         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 552         FPU_ARCH_NEON_VFP_V4): Define.
 553
 554 2009-10-23  Doug Evans  <dje@sebabeach.org>
 555
 556         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 557         * cgen.h: Update.  Improve multi-inclusion macro name.
 558
 559 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 560
 561         * ppc.h (PPC_OPCODE_476): Define.
 562
 563 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 564
 565         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 566
 567 2009-09-29  DJ Delorie  <dj@redhat.com>
 568
 569         * rx.h: New file.
 570
 571 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 572
 573         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 574
 575 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 576
 577         * ppc.h (PPC_OPCODE_PPCA2): New.
 578
 579 2009-09-05  Martin Thuresson  <martin@mtme.org>
 580
 581         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 582
 583 2009-08-29  Martin Thuresson  <martin@mtme.org>
 584
 585         * tic30.h (template): Rename type template to
 586         insn_template. Updated code to use new name.
 587         * tic54x.h (template): Rename type template to
 588         insn_template.
 589
 590 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 591
 592         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 593
 594 2009-06-11  Anthony Green  <green@moxielogic.com>
 595
 596         * moxie.h (MOXIE_F3_PCREL): Define.
 597         (moxie_form3_opc_info): Grow.
 598
 599 2009-06-06  Anthony Green  <green@moxielogic.com>
 600
 601         * moxie.h (MOXIE_F1_M): Define.
 602
 603 2009-04-15  Anthony Green  <green@moxielogic.com>
 604
 605         * moxie.h: Created.
 606
 607 2009-04-06  DJ Delorie  <dj@redhat.com>
 608
 609         * h8300.h: Add relaxation attributes to MOVA opcodes.
 610
 611 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 612
 613         * ppc.h (ppc_parse_cpu): Declare.
 614
 615 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 616
 617         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 618         and _IMM11 for mbitclr and mbitset.
 619         * score-datadep.h: Update dependency information.
 620
 621 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 622
 623         * ppc.h (PPC_OPCODE_POWER7): New.
 624
 625 2009-02-06  Doug Evans  <dje@google.com>
 626
 627         * i386.h: Add comment regarding sse* insns and prefixes.
 628
 629 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 630
 631         * mips.h (INSN_XLR): Define.
 632         (INSN_CHIP_MASK): Update.
 633         (CPU_XLR): Define.
 634         (OPCODE_IS_MEMBER): Update.
 635         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 636
 637 2009-01-28  Doug Evans  <dje@google.com>
 638
 639         * opcode/i386.h: Add multiple inclusion protection.
 640         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 641         (EDI_REG_NUM): New macros.
 642         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 643         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 644         (REX_PREFIX_P): New macro.
 645
 646 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 647
 648         * ppc.h (struct powerpc_opcode): New field "deprecated".
 649         (PPC_OPCODE_NOPOWER4): Delete.
 650
 651 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 652
 653         * mips.h: Define CPU_R14000, CPU_R16000.
 654         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 655
 656 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 657
 658         * arm.h (FPU_NEON_FP16): New.
 659         (FPU_ARCH_NEON_FP16): New.
 660
 661 2008-11-06  Chao-ying Fu  <fu@mips.com>
 662
 663         * mips.h: Doucument '1' for 5-bit sync type.
 664
 665 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 666
 667         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 668         IA64_RS_CR.
 669
 670 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 671
 672         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 673
 674 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 675
 676         * ppc.h (PPC_OPCODE_405): Define.
 677         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 678
 679 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 680
 681         * ppc.h (ppc_cpu_t): New typedef.
 682         (struct powerpc_opcode <flags>): Use it.
 683         (struct powerpc_operand <insert, extract>): Likewise.
 684         (struct powerpc_macro <flags>): Likewise.
 685
 686 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 687
 688         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 689         Update comment before MIPS16 field descriptors to mention MIPS16.
 690         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 691         BBIT.
 692         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 693         New bit masks and shift counts for cins and exts.
 694
 695         * mips.h: Document new field descriptors +Q.
 696         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 697
 698 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 699
 700         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 701         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 702
 703 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 704
 705         * ppc.h: (PPC_OPCODE_E500MC): New.
 706
 707 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386.h (MAX_OPERANDS): Set to 5.
 710         (MAX_MNEM_SIZE): Changed to 20.
 711
 712 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 713
 714         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 715
 716 2008-03-09  Paul Brook  <paul@codesourcery.com>
 717
 718         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 719
 720 2008-03-04  Paul Brook  <paul@codesourcery.com>
 721
 722         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 723         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 724         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 725
 726 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 727             Nick Clifton  <nickc@redhat.com>
 728
 729         PR 3134
 730         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 731         with a 32-bit displacement but without the top bit of the 4th byte
 732         set.
 733
 734 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 735
 736         * cr16.h (cr16_num_optab): Declared.
 737
 738 2008-02-14  Hakan Ardo  <hakan@debian.org>
 739
 740         PR gas/2626
 741         * avr.h (AVR_ISA_2xxe): Define.
 742
 743 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 744
 745         * mips.h: Update copyright.
 746         (INSN_CHIP_MASK): New macro.
 747         (INSN_OCTEON): New macro.
 748         (CPU_OCTEON): New macro.
 749         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 750
 751 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 752
 753         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 754
 755 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 756
 757         * avr.h (AVR_ISA_USB162): Add new opcode set.
 758         (AVR_ISA_AVR3): Likewise.
 759
 760 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 761
 762         * mips.h (INSN_LOONGSON_2E): New.
 763         (INSN_LOONGSON_2F): New.
 764         (CPU_LOONGSON_2E): New.
 765         (CPU_LOONGSON_2F): New.
 766         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 767
 768 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 769
 770         * mips.h (INSN_ISA*): Redefine certain values as an
 771         enumeration.  Update comments.
 772         (mips_isa_table): New.
 773         (ISA_MIPS*): Redefine to match enumeration.
 774         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 775         values.
 776
 777 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 778
 779         * ppc.h (PPC_OPCODE_PPCPS): New.
 780
 781 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 782
 783         * m68k.h: Document j K & E.
 784
 785 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 786
 787         * cr16.h: New file for CR16 target.
 788
 789 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 790
 791         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 792
 793 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 794
 795         * m68k.h (mcfisa_c): New.
 796         (mcfusp, mcf_mask): Adjust.
 797
 798 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 799
 800         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 801         (num_powerpc_operands): Declare.
 802         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 803         (PPC_OPERAND_PLUS1): Define.
 804
 805 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * i386.h (REX_MODE64): Renamed to ...
 808         (REX_W): This.
 809         (REX_EXTX): Renamed to ...
 810         (REX_R): This.
 811         (REX_EXTY): Renamed to ...
 812         (REX_X): This.
 813         (REX_EXTZ): Renamed to ...
 814         (REX_B): This.
 815
 816 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386.h: Add entries from config/tc-i386.h and move tables
 819         to opcodes/i386-opc.h.
 820
 821 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         * i386.h (FloatDR): Removed.
 824         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 825
 826 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 827
 828         * spu-insns.h: Add soma double-float insns.
 829
 830 2007-02-20  Thiemo Seufer  <ths@mips.com>
 831             Chao-Ying Fu  <fu@mips.com>
 832
 833         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 834         (INSN_DSPR2): Add flag for DSP R2 instructions.
 835         (M_BALIGN): New macro.
 836
 837 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 838
 839         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 840         and Seg3ShortFrom with Shortform.
 841
 842 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 843
 844         PR gas/4027
 845         * i386.h (i386_optab): Put the real "test" before the pseudo
 846         one.
 847
 848 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 849
 850         * m68k.h (m68010up): OR fido_a.
 851
 852 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 853
 854         * m68k.h (fido_a): New.
 855
 856 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 857
 858         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 859         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 860         values.
 861
 862 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 865
 866 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 867
 868         * score-inst.h (enum score_insn_type): Add Insn_internal.
 869
 870 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 871             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 872             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 873             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 874             Alan Modra  <amodra@bigpond.net.au>
 875
 876         * spu-insns.h: New file.
 877         * spu.h: New file.
 878
 879 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 880
 881         * ppc.h (PPC_OPCODE_CELL): Define.
 882
 883 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 884
 885         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 886         in amdfam10 architecture.
 887
 888 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 889
 890         * i386.h: Replace CpuMNI with CpuSSSE3.
 891
 892 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 893             Joseph Myers  <joseph@codesourcery.com>
 894             Ian Lance Taylor  <ian@wasabisystems.com>
 895             Ben Elliston  <bje@wasabisystems.com>
 896
 897         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 898
 899 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 900
 901         * score-datadep.h: New file.
 902         * score-inst.h: New file.
 903
 904 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 905
 906         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 907         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 908         movdq2q and movq2dq.
 909
 910 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 911            Michael Meissner             <michael.meissner@amd.com>
 912
 913         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 914
 915 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386.h (i386_optab): Add "nop" with memory reference.
 918
 919 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 920
 921         * i386.h (i386_optab): Update comment for 64bit NOP.
 922
 923 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 924             Anton Blanchard  <anton@samba.org>
 925
 926         * ppc.h (PPC_OPCODE_POWER6): Define.
 927         Adjust whitespace.
 928
 929 2006-06-05  Thiemo Seufer  <ths@mips.com>
 930
 931         * mips.h: Improve description of MT flags.
 932
 933 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 934
 935         * m68k.h (mcf_mask): Define.
 936
 937 2006-05-05  Thiemo Seufer  <ths@mips.com>
 938             David Ung  <davidu@mips.com>
 939
 940         * mips.h (enum): Add macro M_CACHE_AB.
 941
 942 2006-05-04  Thiemo Seufer  <ths@mips.com>
 943             Nigel Stephens  <nigel@mips.com>
 944             David Ung  <davidu@mips.com>
 945
 946         * mips.h: Add INSN_SMARTMIPS define.
 947
 948 2006-04-30  Thiemo Seufer  <ths@mips.com>
 949             David Ung  <davidu@mips.com>
 950
 951         * mips.h: Defines udi bits and masks.  Add description of
 952         characters which may appear in the args field of udi
 953         instructions.
 954
 955 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 956
 957         * mips.h: Improve comments describing the bitfield instruction
 958         fields.
 959
 960 2006-04-26  Julian Brown  <julian@codesourcery.com>
 961
 962         * arm.h (FPU_VFP_EXT_V3): Define constant.
 963         (FPU_NEON_EXT_V1): Likewise.
 964         (FPU_VFP_HARD): Update.
 965         (FPU_VFP_V3): Define macro.
 966         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 967
 968 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 969
 970         * avr.h (AVR_ISA_PWMx): New.
 971
 972 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 973
 974         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 975         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 976         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 977         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 978         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 979
 980 2006-03-10  Paul Brook  <paul@codesourcery.com>
 981
 982         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 983
 984 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 985
 986         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 987         first.  Correct mask of bb "B" opcode.
 988
 989 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 990
 991         * i386.h (i386_optab): Support Intel Merom New Instructions.
 992
 993 2006-02-24  Paul Brook  <paul@codesourcery.com>
 994
 995         * arm.h: Add V7 feature bits.
 996
 997 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1000
1001 2006-01-31  Paul Brook  <paul@codesourcery.com>
1002         Richard Earnshaw <rearnsha@arm.com>
1003
1004         * arm.h: Use ARM_CPU_FEATURE.
1005         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1006         (arm_feature_set): Change to a structure.
1007         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1008         ARM_FEATURE): New macros.
1009
1010 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1011
1012         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1013         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1014         (ADD_PC_INCR_OPCODE): Don't define.
1015
1016 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1017
1018         PR gas/1874
1019         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1020
1021 2005-11-14  David Ung  <davidu@mips.com>
1022
1023         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1024         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1025         save/restore encoding of the args field.
1026
1027 2005-10-28  Dave Brolley  <brolley@redhat.com>
1028
1029         Contribute the following changes:
1030         2005-02-16  Dave Brolley  <brolley@redhat.com>
1031
1032         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1033         cgen_isa_mask_* to cgen_bitset_*.
1034         * cgen.h: Likewise.
1035
1036         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1037
1038         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1039         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1040         (CGEN_CPU_TABLE): Make isas a ponter.
1041
1042         2003-09-29  Dave Brolley  <brolley@redhat.com>
1043
1044         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1045         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1046         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1047
1048         2002-12-13  Dave Brolley  <brolley@redhat.com>
1049
1050         * cgen.h (symcat.h): #include it.
1051         (cgen-bitset.h): #include it.
1052         (CGEN_ATTR_VALUE_TYPE): Now a union.
1053         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1054         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1055         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1056         * cgen-bitset.h: New file.
1057
1058 2005-09-30  Catherine Moore  <clm@cm00re.com>
1059
1060         * bfin.h: New file.
1061
1062 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1063
1064         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1065         indirect operands.
1066
1067 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1068
1069         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1070         Add FLAG_STRICT to pa10 ftest opcode.
1071
1072 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1073
1074         * hppa.h (pa_opcodes): Remove lha entries.
1075
1076 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1077
1078         * hppa.h (FLAG_STRICT): Revise comment.
1079         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1080         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1081         entries for "fdc".
1082
1083 2005-09-30  Catherine Moore  <clm@cm00re.com>
1084
1085         * bfin.h: New file.
1086
1087 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1088
1089         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1090
1091 2005-09-06  Chao-ying Fu  <fu@mips.com>
1092
1093         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1094         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1095         define.
1096         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1097         (INSN_ASE_MASK): Update to include INSN_MT.
1098         (INSN_MT): New define for MT ASE.
1099
1100 2005-08-25  Chao-ying Fu  <fu@mips.com>
1101
1102         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1103         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1104         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1105         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1106         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1107         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1108         instructions.
1109         (INSN_DSP): New define for DSP ASE.
1110
1111 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1112
1113         * a29k.h: Delete.
1114
1115 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1116
1117         * ppc.h (PPC_OPCODE_E300): Define.
1118
1119 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1120
1121         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1122
1123 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1124
1125         PR gas/336
1126         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1127         and pitlb.
1128
1129 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1130
1131         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1132         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1133         Add movq-s as 64-bit variants of movd-s.
1134
1135 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1136
1137         * hppa.h: Fix punctuation in comment.
1138
1139         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1140         implicit space-register addressing.  Set space-register bits on opcodes
1141         using implicit space-register addressing.  Add various missing pa20
1142         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1143         space-register addressing.  Use "fE" instead of "fe" in various
1144         fstw opcodes.
1145
1146 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1147
1148         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1149
1150 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1151
1152         * i386.h (i386_optab): Support Intel VMX Instructions.
1153
1154 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1155
1156         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1157
1158 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1159
1160         * i386.h (i386_optab): Add new insns.
1161
1162 2005-07-01  Nick Clifton  <nickc@redhat.com>
1163
1164         * sparc.h: Add typedefs to structure declarations.
1165
1166 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1167
1168         PR 1013
1169         * i386.h (i386_optab): Update comments for 64bit addressing on
1170         mov. Allow 64bit addressing for mov and movq.
1171
1172 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1173
1174         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1175         respectively, in various floating-point load and store patterns.
1176
1177 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1178
1179         * hppa.h (FLAG_STRICT): Correct comment.
1180         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1181         PA 2.0 mneumonics when equivalent.  Entries with cache control
1182         completers now require PA 1.1.  Adjust whitespace.
1183
1184 2005-05-19  Anton Blanchard  <anton@samba.org>
1185
1186         * ppc.h (PPC_OPCODE_POWER5): Define.
1187
1188 2005-05-10  Nick Clifton  <nickc@redhat.com>
1189
1190         * Update the address and phone number of the FSF organization in
1191         the GPL notices in the following files:
1192         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1193         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1194         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1195         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1196         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1197         tic54x.h, tic80.h, v850.h, vax.h
1198
1199 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1200
1201         * i386.h (i386_optab): Add ht and hnt.
1202
1203 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1204
1205         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1206         Add xcrypt-ctr.  Provide aliases without hyphens.
1207
1208 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1209
1210         Moved from ../ChangeLog
1211
1212         2005-04-12  Paul Brook  <paul@codesourcery.com>
1213         * m88k.h: Rename psr macros to avoid conflicts.
1214
1215         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1216         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1217         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1218         and ARM_ARCH_V6ZKT2.
1219
1220         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1221         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1222         Remove redundant instruction types.
1223         (struct argument): X_op - new field.
1224         (struct cst4_entry): Remove.
1225         (no_op_insn): Declare.
1226
1227         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1228         * crx.h (enum argtype): Rename types, remove unused types.
1229
1230         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1231         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1232         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1233         (enum operand_type): Rearrange operands, edit comments.
1234         replace us<N> with ui<N> for unsigned immediate.
1235         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1236         displacements (respectively).
1237         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1238         (instruction type): Add NO_TYPE_INS.
1239         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1240         (operand_entry): New field - 'flags'.
1241         (operand flags): New.
1242
1243         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1244         * crx.h (operand_type): Remove redundant types i3, i4,
1245         i5, i8, i12.
1246         Add new unsigned immediate types us3, us4, us5, us16.
1247
1248 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1249
1250         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1251         adjust them accordingly.
1252
1253 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1254
1255         * i386.h (i386_optab): Add rdtscp.
1256
1257 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1258
1259         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1260         between memory and segment register. Allow movq for moving between
1261         general-purpose register and segment register.
1262
1263 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1264
1265         PR gas/707
1266         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1267         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1268         fnstsw.
1269
1270 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1271
1272         * m68k.h (m68008, m68ec030, m68882): Remove.
1273         (m68k_mask): New.
1274         (cpu_m68k, cpu_cf): New.
1275         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1276         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1277
1278 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1279
1280         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1281         * cgen.h (enum cgen_parse_operand_type): Add
1282         CGEN_PARSE_OPERAND_SYMBOLIC.
1283
1284 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1285
1286         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1287         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1288         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1289
1290 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1291
1292         * mips.h (struct mips_opcode): Add new pinfo2 member.
1293         (INSN_ALIAS): New define for opcode table entries that are
1294         specific instances of another entry, such as 'move' for an 'or'
1295         with a zero operand.
1296         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1297         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1298
1299 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1300
1301         * mips.h (CPU_RM9000): Define.
1302         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1303
1304 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1305
1306         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1307         to/from test registers are illegal in 64-bit mode. Add missing
1308         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1309         (previously one had to explicitly encode a rex64 prefix). Re-enable
1310         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1311         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1312
1313 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1314
1315         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1316         available only with SSE2. Change the MMX additions introduced by SSE
1317         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1318         instructions by their now designated identifier (since combining i686
1319         and 3DNow! does not really imply 3DNow!A).
1320
1321 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1322
1323         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1324         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1325
1326 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1327             Vineet Sharma      <vineets@noida.hcltech.com>
1328
1329         * maxq.h: New file: Disassembly information for the maxq port.
1330
1331 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1332
1333         * i386.h (i386_optab): Put back "movzb".
1334
1335 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1336
1337         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1338         comments.  Remove member cris_ver_sim.  Add members
1339         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1340         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1341         (struct cris_support_reg, struct cris_cond15): New types.
1342         (cris_conds15): Declare.
1343         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1344         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1345         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1346         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1347         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1348         SIZE_FIELD_UNSIGNED.
1349
1350 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1351
1352         * i386.h (sldx_Suf): Remove.
1353         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1354         (q_FP): Define, implying no REX64.
1355         (x_FP, sl_FP): Imply FloatMF.
1356         (i386_optab): Split reg and mem forms of moving from segment registers
1357         so that the memory forms can ignore the 16-/32-bit operand size
1358         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1359         all non-floating-point instructions. Unite 32- and 64-bit forms of
1360         movsx, movzx, and movd. Adjust floating point operations for the above
1361         changes to the *FP macros. Add DefaultSize to floating point control
1362         insns operating on larger memory ranges. Remove left over comments
1363         hinting at certain insns being Intel-syntax ones where the ones
1364         actually meant are already gone.
1365
1366 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1367
1368         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1369         instruction type.
1370
1371 2004-09-30  Paul Brook  <paul@codesourcery.com>
1372
1373         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1374         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1375
1376 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1377
1378         * avr.h: Add support for
1379         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1380
1381 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1382
1383         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1384
1385 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1386
1387         * msp430.h (msp430_opc): Add new instructions.
1388         (msp430_rcodes): Declare new instructions.
1389         (msp430_hcodes): Likewise..
1390
1391 2004-08-13  Nick Clifton  <nickc@redhat.com>
1392
1393         PR/301
1394         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1395         processors.
1396
1397 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1398
1399         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1400
1401 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1402
1403         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1404
1405 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1406
1407         * i386.h: Adjust instruction descriptions to better match the
1408         specification.
1409
1410 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1411
1412         * arm.h: Remove all old content.  Replace with architecture defines
1413         from gas/config/tc-arm.c.
1414
1415 2004-07-09  Andreas Schwab  <schwab@suse.de>
1416
1417         * m68k.h: Fix comment.
1418
1419 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1420
1421         * crx.h: New file.
1422
1423 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1424
1425         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1426
1427 2004-05-24  Peter Barada  <peter@the-baradas.com>
1428
1429         * m68k.h: Add 'size' to m68k_opcode.
1430
1431 2004-05-05  Peter Barada  <peter@the-baradas.com>
1432
1433         * m68k.h: Switch from ColdFire chip name to core variant.
1434
1435 2004-04-22  Peter Barada  <peter@the-baradas.com>
1436
1437         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1438         descriptions for new EMAC cases.
1439         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1440         handle Motorola MAC syntax.
1441         Allow disassembly of ColdFire V4e object files.
1442
1443 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1444
1445         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1446
1447 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1448
1449         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1450
1451 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1452
1453         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1454
1455 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1456
1457         * i386.h (i386_optab): Added xstore/xcrypt insns.
1458
1459 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1460
1461         * h8300.h (32bit ldc/stc): Add relaxing support.
1462
1463 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1464
1465         * h8300.h (BITOP): Pass MEMRELAX flag.
1466
1467 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1468
1469         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1470         except for the H8S.
1471
1472 For older changes see ChangeLog-9103
1473 \f
1474 Local Variables:
1475 mode: change-log
1476 left-margin: 8
1477 fill-column: 74
1478 version-control: never
1479 End: