include/opcode/ChangeLog

   1 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * bfin.h (is_macmod_pmove): Add missing space before func args.
   4         (is_macmod_hmove): Likewise.
   5
   6 2011-06-13  Walter Lee  <walt@tilera.com>
   7
   8         * tilegx.h: New file.
   9         * tilepro.h: New file.
  10
  11 2011-05-31  Paul Brook  <paul@codesourcery.com>
  12
  13         * arm.h (ARM_ARCH_V7R_IDIV): Define.
  14
  15 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  16
  17         * s390.h: Replace S390_OPERAND_REG_EVEN with
  18         S390_OPERAND_REG_PAIR.
  19
  20 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  21
  22         * s390.h: Add S390_OPCODE_REG_EVEN flag.
  23
  24 2011-04-18  Julian Brown  <julian@codesourcery.com>
  25
  26         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
  27
  28 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
  29
  30         PR gas/12296
  31         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
  32
  33 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
  34
  35         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
  36         New instruction set flags.
  37         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
  38
  39 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
  40
  41         * mips.h (M_PREF_AB): New enum value.
  42
  43 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
  44
  45         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
  46         M_IU): Define.
  47         (is_macmod_pmove, is_macmod_hmove): New functions.
  48
  49 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
  50
  51         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
  52
  53 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
  54
  55         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
  56         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
  57
  58 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  59
  60         PR gas/11395
  61         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
  62         "bb" entries.
  63
  64 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  65
  66         PR gas/11395
  67         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
  68
  69 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
  70
  71         * mips.h: Update commentary after last commit.
  72
  73 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
  74
  75         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
  76         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
  77         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
  78
  79 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  80
  81         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
  82
  83 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips.h: Fix previous commit.
  86
  87 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
  88
  89         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
  90         (INSN_LOONGSON_3A): Clear bit 31.
  91
  92 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  93
  94         PR gas/12198
  95         * arm.h (ARM_AEXT_V6M_ONLY): New define.
  96         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
  97         (ARM_ARCH_V6M_ONLY): New define.
  98
  99 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 100
 101         * mips.h (INSN_LOONGSON_3A): Defined.
 102         (CPU_LOONGSON_3A): Defined.
 103         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 104
 105 2010-10-09  Matt Rice  <ratmice@gmail.com>
 106
 107         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 108         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 109
 110 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 111
 112         * arm.h (ARM_EXT_VIRT): New define.
 113         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 114         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 115         Extensions.
 116
 117 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 118
 119         * arm.h (ARM_AEXT_ADIV): New define.
 120         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 121
 122 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 123
 124         * arm.h (ARM_EXT_OS): New define.
 125         (ARM_AEXT_V6SM): Likewise.
 126         (ARM_ARCH_V6SM): Likewise.
 127
 128 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 129
 130         * arm.h (ARM_EXT_MP): Add.
 131         (ARM_ARCH_V7A_MP): Likewise.
 132
 133 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 134
 135         * bfin.h: Declare pseudoChr structs/defines.
 136
 137 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 138
 139         * bfin.h: Strip trailing whitespace.
 140
 141 2010-07-29  DJ Delorie  <dj@redhat.com>
 142
 143         * rx.h (RX_Operand_Type): Add TwoReg.
 144         (RX_Opcode_ID): Remove ediv and ediv2.
 145
 146 2010-07-27  DJ Delorie  <dj@redhat.com>
 147
 148         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 149
 150 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 151             Ina Pandit  <ina.pandit@kpitcummins.com>
 152
 153         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 154         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 155         PROCESSOR_V850E2_ALL.
 156         Remove PROCESSOR_V850EA support.
 157         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 158         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 159         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 160         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 161         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 162         V850_OPERAND_PERCENT.
 163         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 164         V850_NOT_R0.
 165         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 166         and V850E_PUSH_POP
 167
 168 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 169
 170         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 171         (MIPS16_INSN_BRANCH): Rename to...
 172         (MIPS16_INSN_COND_BRANCH): ... this.
 173
 174 2010-07-03  Alan Modra  <amodra@gmail.com>
 175
 176         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 177         Renumber other PPC_OPCODE defines.
 178
 179 2010-07-03  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 182
 183 2010-06-29  Alan Modra  <amodra@gmail.com>
 184
 185         * maxq.h: Delete file.
 186
 187 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 188
 189         * ppc.h (PPC_OPCODE_E500): Define.
 190
 191 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 192
 193         * opcode/mips.h (INSN_MIPS16): Remove.
 194
 195 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 196
 197         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 198
 199 2010-04-15  Nick Clifton  <nickc@redhat.com>
 200
 201         * alpha.h: Update copyright notice to use GPLv3.
 202         * arc.h: Likewise.
 203         * arm.h: Likewise.
 204         * avr.h: Likewise.
 205         * bfin.h: Likewise.
 206         * cgen.h: Likewise.
 207         * convex.h: Likewise.
 208         * cr16.h: Likewise.
 209         * cris.h: Likewise.
 210         * crx.h: Likewise.
 211         * d10v.h: Likewise.
 212         * d30v.h: Likewise.
 213         * dlx.h: Likewise.
 214         * h8300.h: Likewise.
 215         * hppa.h: Likewise.
 216         * i370.h: Likewise.
 217         * i386.h: Likewise.
 218         * i860.h: Likewise.
 219         * i960.h: Likewise.
 220         * ia64.h: Likewise.
 221         * m68hc11.h: Likewise.
 222         * m68k.h: Likewise.
 223         * m88k.h: Likewise.
 224         * maxq.h: Likewise.
 225         * mips.h: Likewise.
 226         * mmix.h: Likewise.
 227         * mn10200.h: Likewise.
 228         * mn10300.h: Likewise.
 229         * msp430.h: Likewise.
 230         * np1.h: Likewise.
 231         * ns32k.h: Likewise.
 232         * or32.h: Likewise.
 233         * pdp11.h: Likewise.
 234         * pj.h: Likewise.
 235         * pn.h: Likewise.
 236         * ppc.h: Likewise.
 237         * pyr.h: Likewise.
 238         * rx.h: Likewise.
 239         * s390.h: Likewise.
 240         * score-datadep.h: Likewise.
 241         * score-inst.h: Likewise.
 242         * sparc.h: Likewise.
 243         * spu-insns.h: Likewise.
 244         * spu.h: Likewise.
 245         * tic30.h: Likewise.
 246         * tic4x.h: Likewise.
 247         * tic54x.h: Likewise.
 248         * tic80.h: Likewise.
 249         * v850.h: Likewise.
 250         * vax.h: Likewise.
 251
 252 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 253
 254         * tic6x-control-registers.h, tic6x-insn-formats.h,
 255         tic6x-opcode-table.h, tic6x.h: New.
 256
 257 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 258
 259         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 260
 261 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 262
 263         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 264
 265 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 266
 267         * ia64.h (ia64_find_opcode): Remove argument name.
 268         (ia64_find_next_opcode): Likewise.
 269         (ia64_dis_opcode): Likewise.
 270         (ia64_free_opcode): Likewise.
 271         (ia64_find_dependency): Likewise.
 272
 273 2009-11-22  Doug Evans  <dje@sebabeach.org>
 274
 275         * cgen.h: Include bfd_stdint.h.
 276         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 277
 278 2009-11-18  Paul Brook  <paul@codesourcery.com>
 279
 280         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 281
 282 2009-11-17  Paul Brook  <paul@codesourcery.com>
 283         Daniel Jacobowitz  <dan@codesourcery.com>
 284
 285         * arm.h (ARM_EXT_V6_DSP): Define.
 286         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 287         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 288
 289 2009-11-04  DJ Delorie  <dj@redhat.com>
 290
 291         * rx.h (rx_decode_opcode) (mvtipl): Add.
 292         (mvtcp, mvfcp, opecp): Remove.
 293
 294 2009-11-02  Paul Brook  <paul@codesourcery.com>
 295
 296         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 297         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 298         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 299         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 300         FPU_ARCH_NEON_VFP_V4): Define.
 301
 302 2009-10-23  Doug Evans  <dje@sebabeach.org>
 303
 304         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 305         * cgen.h: Update.  Improve multi-inclusion macro name.
 306
 307 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 308
 309         * ppc.h (PPC_OPCODE_476): Define.
 310
 311 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 312
 313         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 314
 315 2009-09-29  DJ Delorie  <dj@redhat.com>
 316
 317         * rx.h: New file.
 318
 319 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 320
 321         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 322
 323 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 324
 325         * ppc.h (PPC_OPCODE_PPCA2): New.
 326
 327 2009-09-05  Martin Thuresson  <martin@mtme.org>
 328
 329         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 330
 331 2009-08-29  Martin Thuresson  <martin@mtme.org>
 332
 333         * tic30.h (template): Rename type template to
 334         insn_template. Updated code to use new name.
 335         * tic54x.h (template): Rename type template to
 336         insn_template.
 337
 338 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 339
 340         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 341
 342 2009-06-11  Anthony Green  <green@moxielogic.com>
 343
 344         * moxie.h (MOXIE_F3_PCREL): Define.
 345         (moxie_form3_opc_info): Grow.
 346
 347 2009-06-06  Anthony Green  <green@moxielogic.com>
 348
 349         * moxie.h (MOXIE_F1_M): Define.
 350
 351 2009-04-15  Anthony Green  <green@moxielogic.com>
 352
 353         * moxie.h: Created.
 354
 355 2009-04-06  DJ Delorie  <dj@redhat.com>
 356
 357         * h8300.h: Add relaxation attributes to MOVA opcodes.
 358
 359 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 360
 361         * ppc.h (ppc_parse_cpu): Declare.
 362
 363 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 364
 365         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 366         and _IMM11 for mbitclr and mbitset.
 367         * score-datadep.h: Update dependency information.
 368
 369 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 370
 371         * ppc.h (PPC_OPCODE_POWER7): New.
 372
 373 2009-02-06  Doug Evans  <dje@google.com>
 374
 375         * i386.h: Add comment regarding sse* insns and prefixes.
 376
 377 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 378
 379         * mips.h (INSN_XLR): Define.
 380         (INSN_CHIP_MASK): Update.
 381         (CPU_XLR): Define.
 382         (OPCODE_IS_MEMBER): Update.
 383         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 384
 385 2009-01-28  Doug Evans  <dje@google.com>
 386
 387         * opcode/i386.h: Add multiple inclusion protection.
 388         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 389         (EDI_REG_NUM): New macros.
 390         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 391         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 392         (REX_PREFIX_P): New macro.
 393
 394 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 395
 396         * ppc.h (struct powerpc_opcode): New field "deprecated".
 397         (PPC_OPCODE_NOPOWER4): Delete.
 398
 399 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 400
 401         * mips.h: Define CPU_R14000, CPU_R16000.
 402         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 403
 404 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 405
 406         * arm.h (FPU_NEON_FP16): New.
 407         (FPU_ARCH_NEON_FP16): New.
 408
 409 2008-11-06  Chao-ying Fu  <fu@mips.com>
 410
 411         * mips.h: Doucument '1' for 5-bit sync type.
 412
 413 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 416         IA64_RS_CR.
 417
 418 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 419
 420         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 421
 422 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 423
 424         * ppc.h (PPC_OPCODE_405): Define.
 425         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 426
 427 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 428
 429         * ppc.h (ppc_cpu_t): New typedef.
 430         (struct powerpc_opcode <flags>): Use it.
 431         (struct powerpc_operand <insert, extract>): Likewise.
 432         (struct powerpc_macro <flags>): Likewise.
 433
 434 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 435
 436         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 437         Update comment before MIPS16 field descriptors to mention MIPS16.
 438         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 439         BBIT.
 440         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 441         New bit masks and shift counts for cins and exts.
 442
 443         * mips.h: Document new field descriptors +Q.
 444         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 445
 446 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 447
 448         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 449         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 450
 451 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 452
 453         * ppc.h: (PPC_OPCODE_E500MC): New.
 454
 455 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386.h (MAX_OPERANDS): Set to 5.
 458         (MAX_MNEM_SIZE): Changed to 20.
 459
 460 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 461
 462         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 463
 464 2008-03-09  Paul Brook  <paul@codesourcery.com>
 465
 466         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 467
 468 2008-03-04  Paul Brook  <paul@codesourcery.com>
 469
 470         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 471         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 472         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 473
 474 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 475             Nick Clifton  <nickc@redhat.com>
 476
 477         PR 3134
 478         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 479         with a 32-bit displacement but without the top bit of the 4th byte
 480         set.
 481
 482 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 483
 484         * cr16.h (cr16_num_optab): Declared.
 485
 486 2008-02-14  Hakan Ardo  <hakan@debian.org>
 487
 488         PR gas/2626
 489         * avr.h (AVR_ISA_2xxe): Define.
 490
 491 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 492
 493         * mips.h: Update copyright.
 494         (INSN_CHIP_MASK): New macro.
 495         (INSN_OCTEON): New macro.
 496         (CPU_OCTEON): New macro.
 497         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 498
 499 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 500
 501         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 502
 503 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 504
 505         * avr.h (AVR_ISA_USB162): Add new opcode set.
 506         (AVR_ISA_AVR3): Likewise.
 507
 508 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 509
 510         * mips.h (INSN_LOONGSON_2E): New.
 511         (INSN_LOONGSON_2F): New.
 512         (CPU_LOONGSON_2E): New.
 513         (CPU_LOONGSON_2F): New.
 514         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 515
 516 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 517
 518         * mips.h (INSN_ISA*): Redefine certain values as an
 519         enumeration.  Update comments.
 520         (mips_isa_table): New.
 521         (ISA_MIPS*): Redefine to match enumeration.
 522         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 523         values.
 524
 525 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 526
 527         * ppc.h (PPC_OPCODE_PPCPS): New.
 528
 529 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 530
 531         * m68k.h: Document j K & E.
 532
 533 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 534
 535         * cr16.h: New file for CR16 target.
 536
 537 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 538
 539         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 540
 541 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 542
 543         * m68k.h (mcfisa_c): New.
 544         (mcfusp, mcf_mask): Adjust.
 545
 546 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 547
 548         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 549         (num_powerpc_operands): Declare.
 550         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 551         (PPC_OPERAND_PLUS1): Define.
 552
 553 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         * i386.h (REX_MODE64): Renamed to ...
 556         (REX_W): This.
 557         (REX_EXTX): Renamed to ...
 558         (REX_R): This.
 559         (REX_EXTY): Renamed to ...
 560         (REX_X): This.
 561         (REX_EXTZ): Renamed to ...
 562         (REX_B): This.
 563
 564 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 565
 566         * i386.h: Add entries from config/tc-i386.h and move tables
 567         to opcodes/i386-opc.h.
 568
 569 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386.h (FloatDR): Removed.
 572         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 573
 574 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 575
 576         * spu-insns.h: Add soma double-float insns.
 577
 578 2007-02-20  Thiemo Seufer  <ths@mips.com>
 579             Chao-Ying Fu  <fu@mips.com>
 580
 581         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 582         (INSN_DSPR2): Add flag for DSP R2 instructions.
 583         (M_BALIGN): New macro.
 584
 585 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 586
 587         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 588         and Seg3ShortFrom with Shortform.
 589
 590 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 591
 592         PR gas/4027
 593         * i386.h (i386_optab): Put the real "test" before the pseudo
 594         one.
 595
 596 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 597
 598         * m68k.h (m68010up): OR fido_a.
 599
 600 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 601
 602         * m68k.h (fido_a): New.
 603
 604 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 605
 606         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 607         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 608         values.
 609
 610 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 613
 614 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 615
 616         * score-inst.h (enum score_insn_type): Add Insn_internal.
 617
 618 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 619             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 620             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 621             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 622             Alan Modra  <amodra@bigpond.net.au>
 623
 624         * spu-insns.h: New file.
 625         * spu.h: New file.
 626
 627 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 628
 629         * ppc.h (PPC_OPCODE_CELL): Define.
 630
 631 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 632
 633         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 634         in amdfam10 architecture.
 635
 636 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 637
 638         * i386.h: Replace CpuMNI with CpuSSSE3.
 639
 640 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 641             Joseph Myers  <joseph@codesourcery.com>
 642             Ian Lance Taylor  <ian@wasabisystems.com>
 643             Ben Elliston  <bje@wasabisystems.com>
 644
 645         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 646
 647 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 648
 649         * score-datadep.h: New file.
 650         * score-inst.h: New file.
 651
 652 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 655         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 656         movdq2q and movq2dq.
 657
 658 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 659            Michael Meissner             <michael.meissner@amd.com>
 660
 661         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 662
 663 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 664
 665         * i386.h (i386_optab): Add "nop" with memory reference.
 666
 667 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         * i386.h (i386_optab): Update comment for 64bit NOP.
 670
 671 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 672             Anton Blanchard  <anton@samba.org>
 673
 674         * ppc.h (PPC_OPCODE_POWER6): Define.
 675         Adjust whitespace.
 676
 677 2006-06-05  Thiemo Seufer  <ths@mips.com>
 678
 679         * mips.h: Improve description of MT flags.
 680
 681 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 682
 683         * m68k.h (mcf_mask): Define.
 684
 685 2006-05-05  Thiemo Seufer  <ths@mips.com>
 686             David Ung  <davidu@mips.com>
 687
 688         * mips.h (enum): Add macro M_CACHE_AB.
 689
 690 2006-05-04  Thiemo Seufer  <ths@mips.com>
 691             Nigel Stephens  <nigel@mips.com>
 692             David Ung  <davidu@mips.com>
 693
 694         * mips.h: Add INSN_SMARTMIPS define.
 695
 696 2006-04-30  Thiemo Seufer  <ths@mips.com>
 697             David Ung  <davidu@mips.com>
 698
 699         * mips.h: Defines udi bits and masks.  Add description of
 700         characters which may appear in the args field of udi
 701         instructions.
 702
 703 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 704
 705         * mips.h: Improve comments describing the bitfield instruction
 706         fields.
 707
 708 2006-04-26  Julian Brown  <julian@codesourcery.com>
 709
 710         * arm.h (FPU_VFP_EXT_V3): Define constant.
 711         (FPU_NEON_EXT_V1): Likewise.
 712         (FPU_VFP_HARD): Update.
 713         (FPU_VFP_V3): Define macro.
 714         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 715
 716 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 717
 718         * avr.h (AVR_ISA_PWMx): New.
 719
 720 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 721
 722         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 723         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 724         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 725         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 726         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 727
 728 2006-03-10  Paul Brook  <paul@codesourcery.com>
 729
 730         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 731
 732 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 733
 734         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 735         first.  Correct mask of bb "B" opcode.
 736
 737 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 738
 739         * i386.h (i386_optab): Support Intel Merom New Instructions.
 740
 741 2006-02-24  Paul Brook  <paul@codesourcery.com>
 742
 743         * arm.h: Add V7 feature bits.
 744
 745 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 746
 747         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 748
 749 2006-01-31  Paul Brook  <paul@codesourcery.com>
 750         Richard Earnshaw <rearnsha@arm.com>
 751
 752         * arm.h: Use ARM_CPU_FEATURE.
 753         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 754         (arm_feature_set): Change to a structure.
 755         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 756         ARM_FEATURE): New macros.
 757
 758 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 759
 760         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 761         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 762         (ADD_PC_INCR_OPCODE): Don't define.
 763
 764 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         PR gas/1874
 767         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 768
 769 2005-11-14  David Ung  <davidu@mips.com>
 770
 771         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 772         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 773         save/restore encoding of the args field.
 774
 775 2005-10-28  Dave Brolley  <brolley@redhat.com>
 776
 777         Contribute the following changes:
 778         2005-02-16  Dave Brolley  <brolley@redhat.com>
 779
 780         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 781         cgen_isa_mask_* to cgen_bitset_*.
 782         * cgen.h: Likewise.
 783
 784         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 785
 786         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 787         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 788         (CGEN_CPU_TABLE): Make isas a ponter.
 789
 790         2003-09-29  Dave Brolley  <brolley@redhat.com>
 791
 792         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 793         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 794         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 795
 796         2002-12-13  Dave Brolley  <brolley@redhat.com>
 797
 798         * cgen.h (symcat.h): #include it.
 799         (cgen-bitset.h): #include it.
 800         (CGEN_ATTR_VALUE_TYPE): Now a union.
 801         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 802         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 803         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 804         * cgen-bitset.h: New file.
 805
 806 2005-09-30  Catherine Moore  <clm@cm00re.com>
 807
 808         * bfin.h: New file.
 809
 810 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 811
 812         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 813         indirect operands.
 814
 815 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 816
 817         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 818         Add FLAG_STRICT to pa10 ftest opcode.
 819
 820 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 821
 822         * hppa.h (pa_opcodes): Remove lha entries.
 823
 824 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 825
 826         * hppa.h (FLAG_STRICT): Revise comment.
 827         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 828         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 829         entries for "fdc".
 830
 831 2005-09-30  Catherine Moore  <clm@cm00re.com>
 832
 833         * bfin.h: New file.
 834
 835 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 836
 837         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 838
 839 2005-09-06  Chao-ying Fu  <fu@mips.com>
 840
 841         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 842         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 843         define.
 844         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 845         (INSN_ASE_MASK): Update to include INSN_MT.
 846         (INSN_MT): New define for MT ASE.
 847
 848 2005-08-25  Chao-ying Fu  <fu@mips.com>
 849
 850         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 851         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 852         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 853         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 854         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 855         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 856         instructions.
 857         (INSN_DSP): New define for DSP ASE.
 858
 859 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 860
 861         * a29k.h: Delete.
 862
 863 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 864
 865         * ppc.h (PPC_OPCODE_E300): Define.
 866
 867 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 868
 869         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 870
 871 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 872
 873         PR gas/336
 874         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 875         and pitlb.
 876
 877 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 878
 879         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 880         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 881         Add movq-s as 64-bit variants of movd-s.
 882
 883 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 884
 885         * hppa.h: Fix punctuation in comment.
 886
 887         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 888         implicit space-register addressing.  Set space-register bits on opcodes
 889         using implicit space-register addressing.  Add various missing pa20
 890         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 891         space-register addressing.  Use "fE" instead of "fe" in various
 892         fstw opcodes.
 893
 894 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 895
 896         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 897
 898 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 899
 900         * i386.h (i386_optab): Support Intel VMX Instructions.
 901
 902 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 903
 904         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 905
 906 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 907
 908         * i386.h (i386_optab): Add new insns.
 909
 910 2005-07-01  Nick Clifton  <nickc@redhat.com>
 911
 912         * sparc.h: Add typedefs to structure declarations.
 913
 914 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         PR 1013
 917         * i386.h (i386_optab): Update comments for 64bit addressing on
 918         mov. Allow 64bit addressing for mov and movq.
 919
 920 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 921
 922         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 923         respectively, in various floating-point load and store patterns.
 924
 925 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 926
 927         * hppa.h (FLAG_STRICT): Correct comment.
 928         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 929         PA 2.0 mneumonics when equivalent.  Entries with cache control
 930         completers now require PA 1.1.  Adjust whitespace.
 931
 932 2005-05-19  Anton Blanchard  <anton@samba.org>
 933
 934         * ppc.h (PPC_OPCODE_POWER5): Define.
 935
 936 2005-05-10  Nick Clifton  <nickc@redhat.com>
 937
 938         * Update the address and phone number of the FSF organization in
 939         the GPL notices in the following files:
 940         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 941         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 942         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 943         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 944         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 945         tic54x.h, tic80.h, v850.h, vax.h
 946
 947 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 948
 949         * i386.h (i386_optab): Add ht and hnt.
 950
 951 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 952
 953         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 954         Add xcrypt-ctr.  Provide aliases without hyphens.
 955
 956 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         Moved from ../ChangeLog
 959
 960         2005-04-12  Paul Brook  <paul@codesourcery.com>
 961         * m88k.h: Rename psr macros to avoid conflicts.
 962
 963         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 964         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 965         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 966         and ARM_ARCH_V6ZKT2.
 967
 968         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 969         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 970         Remove redundant instruction types.
 971         (struct argument): X_op - new field.
 972         (struct cst4_entry): Remove.
 973         (no_op_insn): Declare.
 974
 975         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 976         * crx.h (enum argtype): Rename types, remove unused types.
 977
 978         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 979         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 980         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 981         (enum operand_type): Rearrange operands, edit comments.
 982         replace us<N> with ui<N> for unsigned immediate.
 983         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 984         displacements (respectively).
 985         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 986         (instruction type): Add NO_TYPE_INS.
 987         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 988         (operand_entry): New field - 'flags'.
 989         (operand flags): New.
 990
 991         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 992         * crx.h (operand_type): Remove redundant types i3, i4,
 993         i5, i8, i12.
 994         Add new unsigned immediate types us3, us4, us5, us16.
 995
 996 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 997
 998         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 999         adjust them accordingly.
1000
1001 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1002
1003         * i386.h (i386_optab): Add rdtscp.
1004
1005 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1008         between memory and segment register. Allow movq for moving between
1009         general-purpose register and segment register.
1010
1011 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1012
1013         PR gas/707
1014         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1015         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1016         fnstsw.
1017
1018 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1019
1020         * m68k.h (m68008, m68ec030, m68882): Remove.
1021         (m68k_mask): New.
1022         (cpu_m68k, cpu_cf): New.
1023         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1024         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1025
1026 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1027
1028         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1029         * cgen.h (enum cgen_parse_operand_type): Add
1030         CGEN_PARSE_OPERAND_SYMBOLIC.
1031
1032 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1033
1034         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1035         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1036         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1037
1038 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1039
1040         * mips.h (struct mips_opcode): Add new pinfo2 member.
1041         (INSN_ALIAS): New define for opcode table entries that are
1042         specific instances of another entry, such as 'move' for an 'or'
1043         with a zero operand.
1044         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1045         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1046
1047 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1048
1049         * mips.h (CPU_RM9000): Define.
1050         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1051
1052 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1053
1054         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1055         to/from test registers are illegal in 64-bit mode. Add missing
1056         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1057         (previously one had to explicitly encode a rex64 prefix). Re-enable
1058         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1059         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1060
1061 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1062
1063         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1064         available only with SSE2. Change the MMX additions introduced by SSE
1065         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1066         instructions by their now designated identifier (since combining i686
1067         and 3DNow! does not really imply 3DNow!A).
1068
1069 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1070
1071         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1072         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1073
1074 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1075             Vineet Sharma      <vineets@noida.hcltech.com>
1076
1077         * maxq.h: New file: Disassembly information for the maxq port.
1078
1079 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1080
1081         * i386.h (i386_optab): Put back "movzb".
1082
1083 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1084
1085         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1086         comments.  Remove member cris_ver_sim.  Add members
1087         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1088         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1089         (struct cris_support_reg, struct cris_cond15): New types.
1090         (cris_conds15): Declare.
1091         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1092         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1093         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1094         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1095         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1096         SIZE_FIELD_UNSIGNED.
1097
1098 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1099
1100         * i386.h (sldx_Suf): Remove.
1101         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1102         (q_FP): Define, implying no REX64.
1103         (x_FP, sl_FP): Imply FloatMF.
1104         (i386_optab): Split reg and mem forms of moving from segment registers
1105         so that the memory forms can ignore the 16-/32-bit operand size
1106         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1107         all non-floating-point instructions. Unite 32- and 64-bit forms of
1108         movsx, movzx, and movd. Adjust floating point operations for the above
1109         changes to the *FP macros. Add DefaultSize to floating point control
1110         insns operating on larger memory ranges. Remove left over comments
1111         hinting at certain insns being Intel-syntax ones where the ones
1112         actually meant are already gone.
1113
1114 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1115
1116         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1117         instruction type.
1118
1119 2004-09-30  Paul Brook  <paul@codesourcery.com>
1120
1121         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1122         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1123
1124 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1125
1126         * avr.h: Add support for
1127         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1128
1129 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1130
1131         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1132
1133 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1134
1135         * msp430.h (msp430_opc): Add new instructions.
1136         (msp430_rcodes): Declare new instructions.
1137         (msp430_hcodes): Likewise..
1138
1139 2004-08-13  Nick Clifton  <nickc@redhat.com>
1140
1141         PR/301
1142         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1143         processors.
1144
1145 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1146
1147         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1148
1149 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1150
1151         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1152
1153 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1154
1155         * i386.h: Adjust instruction descriptions to better match the
1156         specification.
1157
1158 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1159
1160         * arm.h: Remove all old content.  Replace with architecture defines
1161         from gas/config/tc-arm.c.
1162
1163 2004-07-09  Andreas Schwab  <schwab@suse.de>
1164
1165         * m68k.h: Fix comment.
1166
1167 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1168
1169         * crx.h: New file.
1170
1171 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1172
1173         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1174
1175 2004-05-24  Peter Barada  <peter@the-baradas.com>
1176
1177         * m68k.h: Add 'size' to m68k_opcode.
1178
1179 2004-05-05  Peter Barada  <peter@the-baradas.com>
1180
1181         * m68k.h: Switch from ColdFire chip name to core variant.
1182
1183 2004-04-22  Peter Barada  <peter@the-baradas.com>
1184
1185         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1186         descriptions for new EMAC cases.
1187         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1188         handle Motorola MAC syntax.
1189         Allow disassembly of ColdFire V4e object files.
1190
1191 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1192
1193         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1194
1195 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1196
1197         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1198
1199 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1200
1201         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1202
1203 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1204
1205         * i386.h (i386_optab): Added xstore/xcrypt insns.
1206
1207 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1208
1209         * h8300.h (32bit ldc/stc): Add relaxing support.
1210
1211 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1212
1213         * h8300.h (BITOP): Pass MEMRELAX flag.
1214
1215 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1216
1217         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1218         except for the H8S.
1219
1220 For older changes see ChangeLog-9103
1221 \f
1222 Local Variables:
1223 mode: change-log
1224 left-margin: 8
1225 fill-column: 74
1226 version-control: never
1227 End: