1 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h: Fix a typo in description.
5 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
7 * avr.h: (AVR_ISA_XCH): New define.
8 (AVR_ISA_XMEGA): Use it.
9 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
11 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
13 * m68hc11.h: Add XGate definitions.
14 (struct m68hc11_opcode): Add xg_mask field.
16 2012-05-14 Catherine Moore <clm@codesourcery.com>
17 Maciej W. Rozycki <macro@codesourcery.com>
18 Rhonda Wittels <rhonda@codesourcery.com>
20 * ppc.h (PPC_OPCODE_VLE): New definition.
21 (PPC_OP_SA): New macro.
22 (PPC_OP_SE_VLE): New macro.
23 (PPC_OP): Use a variable shift amount.
24 (powerpc_operand): Update comments.
25 (PPC_OPSHIFT_INV): New macro.
26 (PPC_OPERAND_CR): Replace with...
27 (PPC_OPERAND_CR_BIT): ...this and
28 (PPC_OPERAND_CR_REG): ...this.
31 2012-05-03 Sean Keys <skeys@ipdatasys.com>
33 * xgate.h: Header file for XGATE assembler.
35 2012-04-27 David S. Miller <davem@davemloft.net>
37 * sparc.h: Document new arg code' )' for crypto RS3
40 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
41 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
42 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
43 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
44 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
45 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
46 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
47 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
48 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
49 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
50 HWCAP_CBCOND, HWCAP_CRC32): New defines.
52 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
54 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
56 2012-02-27 Alan Modra <amodra@gmail.com>
58 * crx.h (cst4_map): Update declaration.
60 2012-02-25 Walter Lee <walt@tilera.com>
62 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
64 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
65 TILEPRO_OPC_LW_TLS_SN.
67 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
69 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
70 (XRELEASE_PREFIX_OPCODE): Likewise.
72 2011-12-08 Andrew Pinski <apinski@cavium.com>
73 Adam Nemet <anemet@caviumnetworks.com>
75 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
76 (INSN_OCTEON2): New macro.
77 (CPU_OCTEON2): New macro.
78 (OPCODE_IS_MEMBER): Add Octeon2.
80 2011-11-29 Andrew Pinski <apinski@cavium.com>
82 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
83 (INSN_OCTEONP): New macro.
84 (CPU_OCTEONP): New macro.
85 (OPCODE_IS_MEMBER): Add Octeon+.
86 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
88 2011-11-01 DJ Delorie <dj@redhat.com>
92 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
94 * mips.h: Fix a typo in description.
96 2011-09-21 David S. Miller <davem@davemloft.net>
98 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
99 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
100 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
101 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
103 2011-08-09 Chao-ying Fu <fu@mips.com>
104 Maciej W. Rozycki <macro@codesourcery.com>
106 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
107 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
108 (INSN_ASE_MASK): Add the MCU bit.
109 (INSN_MCU): New macro.
110 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
111 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
113 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
115 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
116 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
117 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
118 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
119 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
120 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
121 (INSN2_READ_GPR_MMN): Likewise.
122 (INSN2_READ_FPR_D): Change the bit used.
123 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
124 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
125 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
126 (INSN2_COND_BRANCH): Likewise.
127 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
128 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
129 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
130 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
131 (INSN2_MOD_GPR_MN): Likewise.
133 2011-08-05 David S. Miller <davem@davemloft.net>
135 * sparc.h: Document new format codes '4', '5', and '('.
136 (OPF_LOW4, RS3): New macros.
138 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
140 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
141 order of flags documented.
143 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
145 * mips.h: Clarify the description of microMIPS instruction
147 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
149 2011-07-24 Chao-ying Fu <fu@mips.com>
150 Maciej W. Rozycki <macro@codesourcery.com>
152 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
153 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
154 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
155 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
156 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
157 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
158 (OP_MASK_RS3, OP_SH_RS3): Likewise.
159 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
160 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
161 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
162 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
163 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
164 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
165 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
166 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
167 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
168 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
169 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
170 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
171 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
172 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
173 (INSN_WRITE_GPR_S): New macro.
174 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
175 (INSN2_READ_FPR_D): Likewise.
176 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
177 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
178 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
179 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
180 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
181 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
182 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
183 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
184 (CPU_MICROMIPS): New macro.
185 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
186 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
187 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
188 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
189 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
190 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
191 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
192 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
193 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
194 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
195 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
196 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
197 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
198 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
199 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
200 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
201 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
202 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
203 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
204 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
205 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
206 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
207 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
208 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
209 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
210 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
211 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
212 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
213 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
214 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
215 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
216 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
217 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
218 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
219 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
220 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
221 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
222 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
223 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
224 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
225 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
226 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
227 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
228 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
229 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
230 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
231 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
232 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
233 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
234 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
235 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
236 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
237 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
238 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
239 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
240 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
241 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
242 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
243 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
244 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
245 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
246 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
247 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
248 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
249 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
250 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
251 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
252 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
253 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
254 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
255 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
256 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
257 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
258 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
259 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
260 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
261 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
262 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
263 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
264 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
265 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
266 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
267 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
268 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
269 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
270 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
271 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
272 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
273 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
274 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
275 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
276 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
277 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
278 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
279 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
280 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
281 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
282 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
283 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
284 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
285 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
286 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
287 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
288 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
289 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
290 (micromips_opcodes): New declaration.
291 (bfd_micromips_num_opcodes): Likewise.
293 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
295 * mips.h (INSN_TRAP): Rename to...
296 (INSN_NO_DELAY_SLOT): ... this.
297 (INSN_SYNC): Remove macro.
299 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
301 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
302 a duplicate of AVR_ISA_SPM.
304 2011-07-01 Nick Clifton <nickc@redhat.com>
306 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
308 2011-06-18 Robin Getz <robin.getz@analog.com>
310 * bfin.h (is_macmod_signed): New func
312 2011-06-18 Mike Frysinger <vapier@gentoo.org>
314 * bfin.h (is_macmod_pmove): Add missing space before func args.
315 (is_macmod_hmove): Likewise.
317 2011-06-13 Walter Lee <walt@tilera.com>
319 * tilegx.h: New file.
320 * tilepro.h: New file.
322 2011-05-31 Paul Brook <paul@codesourcery.com>
324 * arm.h (ARM_ARCH_V7R_IDIV): Define.
326 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
328 * s390.h: Replace S390_OPERAND_REG_EVEN with
329 S390_OPERAND_REG_PAIR.
331 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
333 * s390.h: Add S390_OPCODE_REG_EVEN flag.
335 2011-04-18 Julian Brown <julian@codesourcery.com>
337 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
339 2011-04-11 Dan McDonald <dan@wellkeeper.com>
342 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
344 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
346 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
347 New instruction set flags.
348 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
350 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
352 * mips.h (M_PREF_AB): New enum value.
354 2011-02-12 Mike Frysinger <vapier@gentoo.org>
356 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
358 (is_macmod_pmove, is_macmod_hmove): New functions.
360 2011-02-11 Mike Frysinger <vapier@gentoo.org>
362 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
364 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
366 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
367 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
369 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
372 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
375 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
378 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
380 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
382 * mips.h: Update commentary after last commit.
384 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
386 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
387 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
388 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
390 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
392 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
394 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
396 * mips.h: Fix previous commit.
398 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
400 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
401 (INSN_LOONGSON_3A): Clear bit 31.
403 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
406 * arm.h (ARM_AEXT_V6M_ONLY): New define.
407 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
408 (ARM_ARCH_V6M_ONLY): New define.
410 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
412 * mips.h (INSN_LOONGSON_3A): Defined.
413 (CPU_LOONGSON_3A): Defined.
414 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
416 2010-10-09 Matt Rice <ratmice@gmail.com>
418 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
419 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
421 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
423 * arm.h (ARM_EXT_VIRT): New define.
424 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
425 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
428 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
430 * arm.h (ARM_AEXT_ADIV): New define.
431 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
433 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
435 * arm.h (ARM_EXT_OS): New define.
436 (ARM_AEXT_V6SM): Likewise.
437 (ARM_ARCH_V6SM): Likewise.
439 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
441 * arm.h (ARM_EXT_MP): Add.
442 (ARM_ARCH_V7A_MP): Likewise.
444 2010-09-22 Mike Frysinger <vapier@gentoo.org>
446 * bfin.h: Declare pseudoChr structs/defines.
448 2010-09-21 Mike Frysinger <vapier@gentoo.org>
450 * bfin.h: Strip trailing whitespace.
452 2010-07-29 DJ Delorie <dj@redhat.com>
454 * rx.h (RX_Operand_Type): Add TwoReg.
455 (RX_Opcode_ID): Remove ediv and ediv2.
457 2010-07-27 DJ Delorie <dj@redhat.com>
459 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
461 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
462 Ina Pandit <ina.pandit@kpitcummins.com>
464 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
465 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
466 PROCESSOR_V850E2_ALL.
467 Remove PROCESSOR_V850EA support.
468 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
469 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
470 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
471 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
472 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
473 V850_OPERAND_PERCENT.
474 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
476 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
479 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
481 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
482 (MIPS16_INSN_BRANCH): Rename to...
483 (MIPS16_INSN_COND_BRANCH): ... this.
485 2010-07-03 Alan Modra <amodra@gmail.com>
487 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
488 Renumber other PPC_OPCODE defines.
490 2010-07-03 Alan Modra <amodra@gmail.com>
492 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
494 2010-06-29 Alan Modra <amodra@gmail.com>
496 * maxq.h: Delete file.
498 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
500 * ppc.h (PPC_OPCODE_E500): Define.
502 2010-05-26 Catherine Moore <clm@codesourcery.com>
504 * opcode/mips.h (INSN_MIPS16): Remove.
506 2010-04-21 Joseph Myers <joseph@codesourcery.com>
508 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
510 2010-04-15 Nick Clifton <nickc@redhat.com>
512 * alpha.h: Update copyright notice to use GPLv3.
518 * convex.h: Likewise.
532 * m68hc11.h: Likewise.
538 * mn10200.h: Likewise.
539 * mn10300.h: Likewise.
540 * msp430.h: Likewise.
551 * score-datadep.h: Likewise.
552 * score-inst.h: Likewise.
554 * spu-insns.h: Likewise.
558 * tic54x.h: Likewise.
563 2010-03-25 Joseph Myers <joseph@codesourcery.com>
565 * tic6x-control-registers.h, tic6x-insn-formats.h,
566 tic6x-opcode-table.h, tic6x.h: New.
568 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
570 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
572 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
574 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
576 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
578 * ia64.h (ia64_find_opcode): Remove argument name.
579 (ia64_find_next_opcode): Likewise.
580 (ia64_dis_opcode): Likewise.
581 (ia64_free_opcode): Likewise.
582 (ia64_find_dependency): Likewise.
584 2009-11-22 Doug Evans <dje@sebabeach.org>
586 * cgen.h: Include bfd_stdint.h.
587 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
589 2009-11-18 Paul Brook <paul@codesourcery.com>
591 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
593 2009-11-17 Paul Brook <paul@codesourcery.com>
594 Daniel Jacobowitz <dan@codesourcery.com>
596 * arm.h (ARM_EXT_V6_DSP): Define.
597 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
598 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
600 2009-11-04 DJ Delorie <dj@redhat.com>
602 * rx.h (rx_decode_opcode) (mvtipl): Add.
603 (mvtcp, mvfcp, opecp): Remove.
605 2009-11-02 Paul Brook <paul@codesourcery.com>
607 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
608 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
609 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
610 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
611 FPU_ARCH_NEON_VFP_V4): Define.
613 2009-10-23 Doug Evans <dje@sebabeach.org>
615 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
616 * cgen.h: Update. Improve multi-inclusion macro name.
618 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
620 * ppc.h (PPC_OPCODE_476): Define.
622 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
624 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
626 2009-09-29 DJ Delorie <dj@redhat.com>
630 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
632 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
634 2009-09-21 Ben Elliston <bje@au.ibm.com>
636 * ppc.h (PPC_OPCODE_PPCA2): New.
638 2009-09-05 Martin Thuresson <martin@mtme.org>
640 * ia64.h (struct ia64_operand): Renamed member class to op_class.
642 2009-08-29 Martin Thuresson <martin@mtme.org>
644 * tic30.h (template): Rename type template to
645 insn_template. Updated code to use new name.
646 * tic54x.h (template): Rename type template to
649 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
651 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
653 2009-06-11 Anthony Green <green@moxielogic.com>
655 * moxie.h (MOXIE_F3_PCREL): Define.
656 (moxie_form3_opc_info): Grow.
658 2009-06-06 Anthony Green <green@moxielogic.com>
660 * moxie.h (MOXIE_F1_M): Define.
662 2009-04-15 Anthony Green <green@moxielogic.com>
666 2009-04-06 DJ Delorie <dj@redhat.com>
668 * h8300.h: Add relaxation attributes to MOVA opcodes.
670 2009-03-10 Alan Modra <amodra@bigpond.net.au>
672 * ppc.h (ppc_parse_cpu): Declare.
674 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
676 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
677 and _IMM11 for mbitclr and mbitset.
678 * score-datadep.h: Update dependency information.
680 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
682 * ppc.h (PPC_OPCODE_POWER7): New.
684 2009-02-06 Doug Evans <dje@google.com>
686 * i386.h: Add comment regarding sse* insns and prefixes.
688 2009-02-03 Sandip Matte <sandip@rmicorp.com>
690 * mips.h (INSN_XLR): Define.
691 (INSN_CHIP_MASK): Update.
693 (OPCODE_IS_MEMBER): Update.
694 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
696 2009-01-28 Doug Evans <dje@google.com>
698 * opcode/i386.h: Add multiple inclusion protection.
699 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
700 (EDI_REG_NUM): New macros.
701 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
702 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
703 (REX_PREFIX_P): New macro.
705 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
707 * ppc.h (struct powerpc_opcode): New field "deprecated".
708 (PPC_OPCODE_NOPOWER4): Delete.
710 2008-11-28 Joshua Kinard <kumba@gentoo.org>
712 * mips.h: Define CPU_R14000, CPU_R16000.
713 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
715 2008-11-18 Catherine Moore <clm@codesourcery.com>
717 * arm.h (FPU_NEON_FP16): New.
718 (FPU_ARCH_NEON_FP16): New.
720 2008-11-06 Chao-ying Fu <fu@mips.com>
722 * mips.h: Doucument '1' for 5-bit sync type.
724 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
726 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
729 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
731 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
733 2008-07-30 Michael J. Eager <eager@eagercon.com>
735 * ppc.h (PPC_OPCODE_405): Define.
736 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
738 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
740 * ppc.h (ppc_cpu_t): New typedef.
741 (struct powerpc_opcode <flags>): Use it.
742 (struct powerpc_operand <insert, extract>): Likewise.
743 (struct powerpc_macro <flags>): Likewise.
745 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
747 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
748 Update comment before MIPS16 field descriptors to mention MIPS16.
749 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
751 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
752 New bit masks and shift counts for cins and exts.
754 * mips.h: Document new field descriptors +Q.
755 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
757 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
759 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
760 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
762 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
764 * ppc.h: (PPC_OPCODE_E500MC): New.
766 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
768 * i386.h (MAX_OPERANDS): Set to 5.
769 (MAX_MNEM_SIZE): Changed to 20.
771 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
773 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
775 2008-03-09 Paul Brook <paul@codesourcery.com>
777 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
779 2008-03-04 Paul Brook <paul@codesourcery.com>
781 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
782 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
783 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
785 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
786 Nick Clifton <nickc@redhat.com>
789 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
790 with a 32-bit displacement but without the top bit of the 4th byte
793 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
795 * cr16.h (cr16_num_optab): Declared.
797 2008-02-14 Hakan Ardo <hakan@debian.org>
800 * avr.h (AVR_ISA_2xxe): Define.
802 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
804 * mips.h: Update copyright.
805 (INSN_CHIP_MASK): New macro.
806 (INSN_OCTEON): New macro.
807 (CPU_OCTEON): New macro.
808 (OPCODE_IS_MEMBER): Handle Octeon instructions.
810 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
812 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
814 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
816 * avr.h (AVR_ISA_USB162): Add new opcode set.
817 (AVR_ISA_AVR3): Likewise.
819 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
821 * mips.h (INSN_LOONGSON_2E): New.
822 (INSN_LOONGSON_2F): New.
823 (CPU_LOONGSON_2E): New.
824 (CPU_LOONGSON_2F): New.
825 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
827 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
829 * mips.h (INSN_ISA*): Redefine certain values as an
830 enumeration. Update comments.
831 (mips_isa_table): New.
832 (ISA_MIPS*): Redefine to match enumeration.
833 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
836 2007-08-08 Ben Elliston <bje@au.ibm.com>
838 * ppc.h (PPC_OPCODE_PPCPS): New.
840 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
842 * m68k.h: Document j K & E.
844 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
846 * cr16.h: New file for CR16 target.
848 2007-05-02 Alan Modra <amodra@bigpond.net.au>
850 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
852 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
854 * m68k.h (mcfisa_c): New.
855 (mcfusp, mcf_mask): Adjust.
857 2007-04-20 Alan Modra <amodra@bigpond.net.au>
859 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
860 (num_powerpc_operands): Declare.
861 (PPC_OPERAND_SIGNED et al): Redefine as hex.
862 (PPC_OPERAND_PLUS1): Define.
864 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
866 * i386.h (REX_MODE64): Renamed to ...
868 (REX_EXTX): Renamed to ...
870 (REX_EXTY): Renamed to ...
872 (REX_EXTZ): Renamed to ...
875 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
877 * i386.h: Add entries from config/tc-i386.h and move tables
878 to opcodes/i386-opc.h.
880 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
882 * i386.h (FloatDR): Removed.
883 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
885 2007-03-01 Alan Modra <amodra@bigpond.net.au>
887 * spu-insns.h: Add soma double-float insns.
889 2007-02-20 Thiemo Seufer <ths@mips.com>
890 Chao-Ying Fu <fu@mips.com>
892 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
893 (INSN_DSPR2): Add flag for DSP R2 instructions.
894 (M_BALIGN): New macro.
896 2007-02-14 Alan Modra <amodra@bigpond.net.au>
898 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
899 and Seg3ShortFrom with Shortform.
901 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
904 * i386.h (i386_optab): Put the real "test" before the pseudo
907 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
909 * m68k.h (m68010up): OR fido_a.
911 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
913 * m68k.h (fido_a): New.
915 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
917 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
918 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
921 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
923 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
925 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
927 * score-inst.h (enum score_insn_type): Add Insn_internal.
929 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
930 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
931 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
932 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
933 Alan Modra <amodra@bigpond.net.au>
935 * spu-insns.h: New file.
938 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
940 * ppc.h (PPC_OPCODE_CELL): Define.
942 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
944 * i386.h : Modify opcode to support for the change in POPCNT opcode
945 in amdfam10 architecture.
947 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
949 * i386.h: Replace CpuMNI with CpuSSSE3.
951 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
952 Joseph Myers <joseph@codesourcery.com>
953 Ian Lance Taylor <ian@wasabisystems.com>
954 Ben Elliston <bje@wasabisystems.com>
956 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
958 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
960 * score-datadep.h: New file.
961 * score-inst.h: New file.
963 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
965 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
966 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
969 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
970 Michael Meissner <michael.meissner@amd.com>
972 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
974 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
976 * i386.h (i386_optab): Add "nop" with memory reference.
978 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
980 * i386.h (i386_optab): Update comment for 64bit NOP.
982 2006-06-06 Ben Elliston <bje@au.ibm.com>
983 Anton Blanchard <anton@samba.org>
985 * ppc.h (PPC_OPCODE_POWER6): Define.
988 2006-06-05 Thiemo Seufer <ths@mips.com>
990 * mips.h: Improve description of MT flags.
992 2006-05-25 Richard Sandiford <richard@codesourcery.com>
994 * m68k.h (mcf_mask): Define.
996 2006-05-05 Thiemo Seufer <ths@mips.com>
997 David Ung <davidu@mips.com>
999 * mips.h (enum): Add macro M_CACHE_AB.
1001 2006-05-04 Thiemo Seufer <ths@mips.com>
1002 Nigel Stephens <nigel@mips.com>
1003 David Ung <davidu@mips.com>
1005 * mips.h: Add INSN_SMARTMIPS define.
1007 2006-04-30 Thiemo Seufer <ths@mips.com>
1008 David Ung <davidu@mips.com>
1010 * mips.h: Defines udi bits and masks. Add description of
1011 characters which may appear in the args field of udi
1014 2006-04-26 Thiemo Seufer <ths@networkno.de>
1016 * mips.h: Improve comments describing the bitfield instruction
1019 2006-04-26 Julian Brown <julian@codesourcery.com>
1021 * arm.h (FPU_VFP_EXT_V3): Define constant.
1022 (FPU_NEON_EXT_V1): Likewise.
1023 (FPU_VFP_HARD): Update.
1024 (FPU_VFP_V3): Define macro.
1025 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1027 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1029 * avr.h (AVR_ISA_PWMx): New.
1031 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1033 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1034 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1035 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1036 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1037 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1039 2006-03-10 Paul Brook <paul@codesourcery.com>
1041 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1043 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1045 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1046 first. Correct mask of bb "B" opcode.
1048 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1050 * i386.h (i386_optab): Support Intel Merom New Instructions.
1052 2006-02-24 Paul Brook <paul@codesourcery.com>
1054 * arm.h: Add V7 feature bits.
1056 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1058 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1060 2006-01-31 Paul Brook <paul@codesourcery.com>
1061 Richard Earnshaw <rearnsha@arm.com>
1063 * arm.h: Use ARM_CPU_FEATURE.
1064 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1065 (arm_feature_set): Change to a structure.
1066 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1067 ARM_FEATURE): New macros.
1069 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1071 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1072 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1073 (ADD_PC_INCR_OPCODE): Don't define.
1075 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1078 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1080 2005-11-14 David Ung <davidu@mips.com>
1082 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1083 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1084 save/restore encoding of the args field.
1086 2005-10-28 Dave Brolley <brolley@redhat.com>
1088 Contribute the following changes:
1089 2005-02-16 Dave Brolley <brolley@redhat.com>
1091 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1092 cgen_isa_mask_* to cgen_bitset_*.
1095 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1097 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1098 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1099 (CGEN_CPU_TABLE): Make isas a ponter.
1101 2003-09-29 Dave Brolley <brolley@redhat.com>
1103 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1104 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1105 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1107 2002-12-13 Dave Brolley <brolley@redhat.com>
1109 * cgen.h (symcat.h): #include it.
1110 (cgen-bitset.h): #include it.
1111 (CGEN_ATTR_VALUE_TYPE): Now a union.
1112 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1113 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1114 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1115 * cgen-bitset.h: New file.
1117 2005-09-30 Catherine Moore <clm@cm00re.com>
1121 2005-10-24 Jan Beulich <jbeulich@novell.com>
1123 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1126 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1128 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1129 Add FLAG_STRICT to pa10 ftest opcode.
1131 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1133 * hppa.h (pa_opcodes): Remove lha entries.
1135 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1137 * hppa.h (FLAG_STRICT): Revise comment.
1138 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1139 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1142 2005-09-30 Catherine Moore <clm@cm00re.com>
1146 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1148 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1150 2005-09-06 Chao-ying Fu <fu@mips.com>
1152 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1153 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1155 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1156 (INSN_ASE_MASK): Update to include INSN_MT.
1157 (INSN_MT): New define for MT ASE.
1159 2005-08-25 Chao-ying Fu <fu@mips.com>
1161 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1162 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1163 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1164 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1165 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1166 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1168 (INSN_DSP): New define for DSP ASE.
1170 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1174 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1176 * ppc.h (PPC_OPCODE_E300): Define.
1178 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1180 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1182 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1185 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1188 2005-07-27 Jan Beulich <jbeulich@novell.com>
1190 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1191 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1192 Add movq-s as 64-bit variants of movd-s.
1194 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1196 * hppa.h: Fix punctuation in comment.
1198 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1199 implicit space-register addressing. Set space-register bits on opcodes
1200 using implicit space-register addressing. Add various missing pa20
1201 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1202 space-register addressing. Use "fE" instead of "fe" in various
1205 2005-07-18 Jan Beulich <jbeulich@novell.com>
1207 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1209 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1211 * i386.h (i386_optab): Support Intel VMX Instructions.
1213 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1215 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1217 2005-07-05 Jan Beulich <jbeulich@novell.com>
1219 * i386.h (i386_optab): Add new insns.
1221 2005-07-01 Nick Clifton <nickc@redhat.com>
1223 * sparc.h: Add typedefs to structure declarations.
1225 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1228 * i386.h (i386_optab): Update comments for 64bit addressing on
1229 mov. Allow 64bit addressing for mov and movq.
1231 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1233 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1234 respectively, in various floating-point load and store patterns.
1236 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1238 * hppa.h (FLAG_STRICT): Correct comment.
1239 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1240 PA 2.0 mneumonics when equivalent. Entries with cache control
1241 completers now require PA 1.1. Adjust whitespace.
1243 2005-05-19 Anton Blanchard <anton@samba.org>
1245 * ppc.h (PPC_OPCODE_POWER5): Define.
1247 2005-05-10 Nick Clifton <nickc@redhat.com>
1249 * Update the address and phone number of the FSF organization in
1250 the GPL notices in the following files:
1251 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1252 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1253 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1254 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1255 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1256 tic54x.h, tic80.h, v850.h, vax.h
1258 2005-05-09 Jan Beulich <jbeulich@novell.com>
1260 * i386.h (i386_optab): Add ht and hnt.
1262 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1264 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1265 Add xcrypt-ctr. Provide aliases without hyphens.
1267 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1269 Moved from ../ChangeLog
1271 2005-04-12 Paul Brook <paul@codesourcery.com>
1272 * m88k.h: Rename psr macros to avoid conflicts.
1274 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1275 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1276 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1277 and ARM_ARCH_V6ZKT2.
1279 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1280 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1281 Remove redundant instruction types.
1282 (struct argument): X_op - new field.
1283 (struct cst4_entry): Remove.
1284 (no_op_insn): Declare.
1286 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1287 * crx.h (enum argtype): Rename types, remove unused types.
1289 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1290 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1291 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1292 (enum operand_type): Rearrange operands, edit comments.
1293 replace us<N> with ui<N> for unsigned immediate.
1294 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1295 displacements (respectively).
1296 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1297 (instruction type): Add NO_TYPE_INS.
1298 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1299 (operand_entry): New field - 'flags'.
1300 (operand flags): New.
1302 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1303 * crx.h (operand_type): Remove redundant types i3, i4,
1305 Add new unsigned immediate types us3, us4, us5, us16.
1307 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1309 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1310 adjust them accordingly.
1312 2005-04-01 Jan Beulich <jbeulich@novell.com>
1314 * i386.h (i386_optab): Add rdtscp.
1316 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1318 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1319 between memory and segment register. Allow movq for moving between
1320 general-purpose register and segment register.
1322 2005-02-09 Jan Beulich <jbeulich@novell.com>
1325 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1326 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1329 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1331 * m68k.h (m68008, m68ec030, m68882): Remove.
1333 (cpu_m68k, cpu_cf): New.
1334 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1335 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1337 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1339 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1340 * cgen.h (enum cgen_parse_operand_type): Add
1341 CGEN_PARSE_OPERAND_SYMBOLIC.
1343 2005-01-21 Fred Fish <fnf@specifixinc.com>
1345 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1346 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1347 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1349 2005-01-19 Fred Fish <fnf@specifixinc.com>
1351 * mips.h (struct mips_opcode): Add new pinfo2 member.
1352 (INSN_ALIAS): New define for opcode table entries that are
1353 specific instances of another entry, such as 'move' for an 'or'
1354 with a zero operand.
1355 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1356 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1358 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1360 * mips.h (CPU_RM9000): Define.
1361 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1363 2004-11-25 Jan Beulich <jbeulich@novell.com>
1365 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1366 to/from test registers are illegal in 64-bit mode. Add missing
1367 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1368 (previously one had to explicitly encode a rex64 prefix). Re-enable
1369 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1370 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1372 2004-11-23 Jan Beulich <jbeulich@novell.com>
1374 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1375 available only with SSE2. Change the MMX additions introduced by SSE
1376 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1377 instructions by their now designated identifier (since combining i686
1378 and 3DNow! does not really imply 3DNow!A).
1380 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1382 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1383 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1385 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1386 Vineet Sharma <vineets@noida.hcltech.com>
1388 * maxq.h: New file: Disassembly information for the maxq port.
1390 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1392 * i386.h (i386_optab): Put back "movzb".
1394 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1396 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1397 comments. Remove member cris_ver_sim. Add members
1398 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1399 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1400 (struct cris_support_reg, struct cris_cond15): New types.
1401 (cris_conds15): Declare.
1402 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1403 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1404 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1405 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1406 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1407 SIZE_FIELD_UNSIGNED.
1409 2004-11-04 Jan Beulich <jbeulich@novell.com>
1411 * i386.h (sldx_Suf): Remove.
1412 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1413 (q_FP): Define, implying no REX64.
1414 (x_FP, sl_FP): Imply FloatMF.
1415 (i386_optab): Split reg and mem forms of moving from segment registers
1416 so that the memory forms can ignore the 16-/32-bit operand size
1417 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1418 all non-floating-point instructions. Unite 32- and 64-bit forms of
1419 movsx, movzx, and movd. Adjust floating point operations for the above
1420 changes to the *FP macros. Add DefaultSize to floating point control
1421 insns operating on larger memory ranges. Remove left over comments
1422 hinting at certain insns being Intel-syntax ones where the ones
1423 actually meant are already gone.
1425 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1427 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1430 2004-09-30 Paul Brook <paul@codesourcery.com>
1432 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1433 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1435 2004-09-11 Theodore A. Roth <troth@openavr.org>
1437 * avr.h: Add support for
1438 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1440 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1442 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1444 2004-08-24 Dmitry Diky <diwil@spec.ru>
1446 * msp430.h (msp430_opc): Add new instructions.
1447 (msp430_rcodes): Declare new instructions.
1448 (msp430_hcodes): Likewise..
1450 2004-08-13 Nick Clifton <nickc@redhat.com>
1453 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1456 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1458 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1460 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1462 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1464 2004-07-21 Jan Beulich <jbeulich@novell.com>
1466 * i386.h: Adjust instruction descriptions to better match the
1469 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1471 * arm.h: Remove all old content. Replace with architecture defines
1472 from gas/config/tc-arm.c.
1474 2004-07-09 Andreas Schwab <schwab@suse.de>
1476 * m68k.h: Fix comment.
1478 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1482 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1484 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1486 2004-05-24 Peter Barada <peter@the-baradas.com>
1488 * m68k.h: Add 'size' to m68k_opcode.
1490 2004-05-05 Peter Barada <peter@the-baradas.com>
1492 * m68k.h: Switch from ColdFire chip name to core variant.
1494 2004-04-22 Peter Barada <peter@the-baradas.com>
1496 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1497 descriptions for new EMAC cases.
1498 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1499 handle Motorola MAC syntax.
1500 Allow disassembly of ColdFire V4e object files.
1502 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1504 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1506 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1508 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1510 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1512 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1514 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1516 * i386.h (i386_optab): Added xstore/xcrypt insns.
1518 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1520 * h8300.h (32bit ldc/stc): Add relaxing support.
1522 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1524 * h8300.h (BITOP): Pass MEMRELAX flag.
1526 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1528 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1531 For older changes see ChangeLog-9103
1537 version-control: never