1 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (AARCH64_FEATURE_RDMA): New.
5 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
7 * aarch64.h (AARCH64_FEATURE_LOR): New.
9 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
11 * aarch64.h (AARCH64_FEATURE_PAN): New.
12 (aarch64_sys_reg_supported_p): Declare.
13 (aarch64_pstatefield_supported_p): Declare.
15 2015-04-30 DJ Delorie <dj@redhat.com>
17 * rl78.h (RL78_Dis_Isa): New.
18 (rl78_decode_opcode): Add ISA parameter.
20 2015-03-24 Terry Guo <terry.guo@arm.com>
22 * arm.h (arm_feature_set): Extended to provide more available bits.
23 (ARM_ANY): Updated to follow above new definition.
24 (ARM_CPU_HAS_FEATURE): Likewise.
25 (ARM_CPU_IS_ANY): Likewise.
26 (ARM_MERGE_FEATURE_SETS): Likewise.
27 (ARM_CLEAR_FEATURE): Likewise.
28 (ARM_FEATURE): Likewise.
29 (ARM_FEATURE_COPY): New macro.
30 (ARM_FEATURE_EQUAL): Likewise.
31 (ARM_FEATURE_ZERO): Likewise.
32 (ARM_FEATURE_CORE_EQUAL): Likewise.
33 (ARM_FEATURE_LOW): Likewise.
34 (ARM_FEATURE_CORE_LOW): Likewise.
35 (ARM_FEATURE_CORE_COPROC): Likewise.
37 2015-02-19 Pedro Alves <palves@redhat.com>
39 * cgen.h [__cplusplus]: Wrap in extern "C".
40 * msp430-decode.h [__cplusplus]: Likewise.
41 * nios2.h [__cplusplus]: Likewise.
42 * rl78.h [__cplusplus]: Likewise.
43 * rx.h [__cplusplus]: Likewise.
44 * tilegx.h [__cplusplus]: Likewise.
46 2015-01-28 James Bowman <james.bowman@ftdichip.com>
50 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
52 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
54 2015-01-01 Alan Modra <amodra@gmail.com>
56 Update year range in copyright notice of all files.
58 2014-12-27 Anthony Green <green@moxielogic.com>
60 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
61 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
63 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
67 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
69 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
70 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
71 (NIOS2_INSN_OPTARG): Renumber.
73 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
75 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
76 declaration. Fix obsolete comment.
78 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
80 * nios2.h (enum iw_format_type): New.
81 (struct nios2_opcode): Update comments. Add size and format fields.
82 (NIOS2_INSN_OPTARG): New.
83 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
84 (struct nios2_reg): Add regtype field.
85 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
86 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
87 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
88 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
89 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
90 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
91 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
92 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
93 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
94 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
95 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
96 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
97 (OP_MASK_OP, OP_SH_OP): Delete.
98 (OP_MASK_IOP, OP_SH_IOP): Delete.
99 (OP_MASK_IRD, OP_SH_IRD): Delete.
100 (OP_MASK_IRT, OP_SH_IRT): Delete.
101 (OP_MASK_IRS, OP_SH_IRS): Delete.
102 (OP_MASK_ROP, OP_SH_ROP): Delete.
103 (OP_MASK_RRD, OP_SH_RRD): Delete.
104 (OP_MASK_RRT, OP_SH_RRT): Delete.
105 (OP_MASK_RRS, OP_SH_RRS): Delete.
106 (OP_MASK_JOP, OP_SH_JOP): Delete.
107 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
108 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
109 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
110 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
111 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
112 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
113 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
114 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
115 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
116 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
117 (OP_MASK_<insn>, OP_MASK): Delete.
118 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
119 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
120 Include nios2r1.h to define new instruction opcode constants
122 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
123 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
124 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
125 (NUMOPCODES, NUMREGISTERS): Delete.
126 * nios2r1.h: New file.
128 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
130 * sparc.h (HWCAP2_VIS3B): Documentation improved.
132 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
134 * sparc.h (sparc_opcode): new field `hwcaps2'.
135 (HWCAP2_FJATHPLUS): New define.
136 (HWCAP2_VIS3B): Likewise.
137 (HWCAP2_ADP): Likewise.
138 (HWCAP2_SPARC5): Likewise.
139 (HWCAP2_MWAIT): Likewise.
140 (HWCAP2_XMPMUL): Likewise.
141 (HWCAP2_XMONT): Likewise.
142 (HWCAP2_NSEC): Likewise.
143 (HWCAP2_FJATHHPC): Likewise.
144 (HWCAP2_FJDES): Likewise.
145 (HWCAP2_FJAES): Likewise.
146 Document the new operand kind `{', corresponding to the mcdper
147 ancillary state register.
148 Document the new operand kind }, which represents frsd floating
149 point registers (double precision) which must be the same than
150 frs1 in its containing instruction.
152 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
154 * nds32.h: Add new opcode declaration.
156 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
157 Matthew Fortune <matthew.fortune@imgtec.com>
159 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
160 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
161 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
162 +I, +O, +R, +:, +\, +", +;
163 (mips_check_prev_operand): New struct.
164 (INSN2_FORBIDDEN_SLOT): New define.
165 (INSN_ISA32R6): New define.
166 (INSN_ISA64R6): New define.
167 (INSN_UPTO32R6): New define.
168 (INSN_UPTO64R6): New define.
169 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
170 (ISA_MIPS32R6): New define.
171 (ISA_MIPS64R6): New define.
172 (CPU_MIPS32R6): New define.
173 (CPU_MIPS64R6): New define.
174 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
176 2014-09-03 Jiong Wang <jiong.wang@arm.com>
178 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
179 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
180 (aarch64_insn_class): Add lse_atomic.
181 (F_LSE_SZ): New field added.
182 (opcode_has_special_coder): Recognize F_LSE_SZ.
184 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
186 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
189 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
191 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
192 (INSN_LOAD_COPROC): New define.
193 (INSN_COPROC_MOVE_DELAY): Rename to...
194 (INSN_COPROC_MOVE): New define.
196 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
197 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
198 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
199 Soundararajan <Sounderarajan.D@atmel.com>
201 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
202 (AVR_ISA_2xxxa): Define ISA without LPM.
203 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
204 Add doc for contraint used in 16 bit lds/sts.
205 Adjust ISA group for icall, ijmp, pop and push.
206 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
208 2014-05-19 Nick Clifton <nickc@redhat.com>
210 * msp430.h (struct msp430_operand_s): Add vshift field.
212 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
214 * mips.h (INSN_ISA_MASK): Updated.
215 (INSN_ISA32R3): New define.
216 (INSN_ISA32R5): New define.
217 (INSN_ISA64R3): New define.
218 (INSN_ISA64R5): New define.
219 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
220 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
221 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
223 (INSN_UPTO32R3): New define.
224 (INSN_UPTO32R5): New define.
225 (INSN_UPTO64R3): New define.
226 (INSN_UPTO64R5): New define.
227 (ISA_MIPS32R3): New define.
228 (ISA_MIPS32R5): New define.
229 (ISA_MIPS64R3): New define.
230 (ISA_MIPS64R5): New define.
231 (CPU_MIPS32R3): New define.
232 (CPU_MIPS32R5): New define.
233 (CPU_MIPS64R3): New define.
234 (CPU_MIPS64R5): New define.
236 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
238 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
240 2014-04-22 Christian Svensson <blue@cmd.nu>
244 2014-03-05 Alan Modra <amodra@gmail.com>
246 Update copyright years.
248 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
250 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
253 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
254 Wei-Cheng Wang <cole945@gmail.com>
256 * nds32.h: New file for Andes NDS32.
258 2013-12-07 Mike Frysinger <vapier@gentoo.org>
260 * bfin.h: Remove +x file mode.
262 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
264 * aarch64.h (aarch64_pstatefields): Change element type to
267 2013-11-18 Renlin Li <Renlin.Li@arm.com>
269 * arm.h (ARM_AEXT_V7VE): New define.
270 (ARM_ARCH_V7VE): New define.
271 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
273 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
277 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
279 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
280 (aarch64_sys_reg_writeonly_p): Ditto.
282 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
284 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
285 (aarch64_sys_reg_writeonly_p): Ditto.
287 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
289 * aarch64.h (aarch64_sys_reg): New typedef.
290 (aarch64_sys_regs): Change to define with the new type.
291 (aarch64_sys_reg_deprecated_p): Declare.
293 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
295 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
296 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
298 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
300 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
301 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
302 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
303 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
304 For MIPS, update extension character sequences after +.
305 (ASE_MSA): New define.
306 (ASE_MSA64): New define.
307 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
308 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
309 For microMIPS, update extension character sequences after +.
311 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
316 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
318 * mips.h: Remove references to "+I" and imm2_expr.
320 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
322 * mips.h (M_DEXT, M_DINS): Delete.
324 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
326 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
327 (mips_optional_operand_p): New function.
329 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
330 Richard Sandiford <rdsandiford@googlemail.com>
332 * mips.h: Document new VU0 operand characters.
333 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
334 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
335 (OP_REG_R5900_ACC): New mips_reg_operand_types.
336 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
337 (mips_vu0_channel_mask): Declare.
339 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
341 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
342 (mips_int_operand_min, mips_int_operand_max): New functions.
343 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
345 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
347 * mips.h (mips_decode_reg_operand): New function.
348 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
349 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
350 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
352 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
353 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
354 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
355 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
356 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
357 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
358 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
359 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
360 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
361 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
362 macros to cover the gaps.
363 (INSN2_MOD_SP): Replace with...
364 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
365 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
366 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
367 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
368 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
371 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
373 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
374 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
375 (MIPS16_INSN_COND_BRANCH): Delete.
377 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
378 Kirill Yukhin <kirill.yukhin@intel.com>
379 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
381 * i386.h (BND_PREFIX_OPCODE): New.
383 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
385 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
386 OP_SAVE_RESTORE_LIST.
387 (decode_mips16_operand): Declare.
389 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
391 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
392 (mips_operand, mips_int_operand, mips_mapped_int_operand)
393 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
394 (mips_pcrel_operand): New structures.
395 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
396 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
397 (decode_mips_operand, decode_micromips_operand): Declare.
399 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
401 * mips.h: Document MIPS16 "I" opcode.
403 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
405 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
406 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
407 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
408 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
409 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
410 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
411 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
412 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
413 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
414 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
415 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
416 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
417 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
419 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
420 (M_USD_AB): ...these.
422 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
424 * mips.h: Remove documentation of "[" and "]". Update documentation
425 of "k" and the MDMX formats.
427 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
429 * mips.h: Update documentation of "+s" and "+S".
431 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
433 * mips.h: Document "+i".
435 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
437 * mips.h: Remove "mi" documentation. Update "mh" documentation.
438 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
440 (INSN2_WRITE_GPR_MHI): Rename to...
441 (INSN2_WRITE_GPR_MH): ...this.
443 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
445 * mips.h: Remove documentation of "+D" and "+T".
447 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
449 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
450 Use "source" rather than "destination" for microMIPS "G".
452 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
454 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
457 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
459 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
461 2013-06-17 Catherine Moore <clm@codesourcery.com>
462 Maciej W. Rozycki <macro@codesourcery.com>
463 Chao-Ying Fu <fu@mips.com>
465 * mips.h (OP_SH_EVAOFFSET): Define.
466 (OP_MASK_EVAOFFSET): Define.
467 (INSN_ASE_MASK): Delete.
469 (M_CACHEE_AB, M_CACHEE_OB): New.
470 (M_LBE_OB, M_LBE_AB): New.
471 (M_LBUE_OB, M_LBUE_AB): New.
472 (M_LHE_OB, M_LHE_AB): New.
473 (M_LHUE_OB, M_LHUE_AB): New.
474 (M_LLE_AB, M_LLE_OB): New.
475 (M_LWE_OB, M_LWE_AB): New.
476 (M_LWLE_AB, M_LWLE_OB): New.
477 (M_LWRE_AB, M_LWRE_OB): New.
478 (M_PREFE_AB, M_PREFE_OB): New.
479 (M_SCE_AB, M_SCE_OB): New.
480 (M_SBE_OB, M_SBE_AB): New.
481 (M_SHE_OB, M_SHE_AB): New.
482 (M_SWE_OB, M_SWE_AB): New.
483 (M_SWLE_AB, M_SWLE_OB): New.
484 (M_SWRE_AB, M_SWRE_OB): New.
485 (MICROMIPSOP_SH_EVAOFFSET): Define.
486 (MICROMIPSOP_MASK_EVAOFFSET): Define.
488 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
490 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
492 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
494 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
496 2013-05-09 Andrew Pinski <apinski@cavium.com>
498 * mips.h (OP_MASK_CODE10): Correct definition.
499 (OP_SH_CODE10): Likewise.
500 Add a comment that "+J" is used now for OP_*CODE10.
501 (INSN_ASE_MASK): Update.
502 (INSN_VIRT): New macro.
503 (INSN_VIRT64): New macro
505 2013-05-02 Nick Clifton <nickc@redhat.com>
507 * msp430.h: Add patterns for MSP430X instructions.
509 2013-04-06 David S. Miller <davem@davemloft.net>
511 * sparc.h (F_PREFERRED): Define.
512 (F_PREF_ALIAS): Define.
514 2013-04-03 Nick Clifton <nickc@redhat.com>
516 * v850.h (V850_INVERSE_PCREL): Define.
518 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
521 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
523 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
526 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
528 * tic6xc-opcode-table.h: Add 16-bit insns.
529 * tic6x.h: Add support for 16-bit insns.
531 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
533 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
534 and mov.b/w/l Rs,@(d:32,ERd).
536 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
539 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
540 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
541 tic6x_operand_xregpair operand coding type.
542 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
543 opcode field, usu ORXREGD1324 for the src2 operand and remove the
546 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
549 * tic6x.h (enum tic6x_coding_method): Add
550 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
551 separately the msb and lsb of a register pair. This is needed to
552 encode the opcodes in the same way as TI assembler does.
553 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
554 and rsqrdp opcodes to use the new field coding types.
556 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
558 * arm.h (CRC_EXT_ARMV8): New constant.
559 (ARCH_CRC_ARMV8): New macro.
561 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
563 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
565 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
566 Andrew Jenner <andrew@codesourcery.com>
568 Based on patches from Altera Corporation.
572 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
574 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
576 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
579 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
581 2013-01-24 Nick Clifton <nickc@redhat.com>
583 * v850.h: Add e3v5 support.
585 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
587 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
589 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
591 * ppc.h (PPC_OPCODE_POWER8): New define.
592 (PPC_OPCODE_HTM): Likewise.
594 2013-01-10 Will Newton <will.newton@imgtec.com>
598 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
600 * cr16.h (make_instruction): Rename to cr16_make_instruction.
601 (match_opcode): Rename to cr16_match_opcode.
603 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
605 * mips.h: Add support for r5900 instructions including lq and sq.
607 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
609 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
610 (make_instruction,match_opcode): Added function prototypes.
611 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
613 2012-11-23 Alan Modra <amodra@gmail.com>
615 * ppc.h (ppc_parse_cpu): Update prototype.
617 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
619 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
620 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
622 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
624 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
626 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
628 * ia64.h (ia64_opnd): Add new operand types.
630 2012-08-21 David S. Miller <davem@davemloft.net>
632 * sparc.h (F3F4): New macro.
634 2012-08-13 Ian Bolton <ian.bolton@arm.com>
635 Laurent Desnogues <laurent.desnogues@arm.com>
636 Jim MacArthur <jim.macarthur@arm.com>
637 Marcus Shawcroft <marcus.shawcroft@arm.com>
638 Nigel Stephens <nigel.stephens@arm.com>
639 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
640 Richard Earnshaw <rearnsha@arm.com>
641 Sofiane Naci <sofiane.naci@arm.com>
642 Tejas Belagod <tejas.belagod@arm.com>
643 Yufeng Zhang <yufeng.zhang@arm.com>
645 * aarch64.h: New file.
647 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
648 Maciej W. Rozycki <macro@codesourcery.com>
650 * mips.h (mips_opcode): Add the exclusions field.
651 (OPCODE_IS_MEMBER): Remove macro.
652 (cpu_is_member): New inline function.
653 (opcode_is_member): Likewise.
655 2012-07-31 Chao-Ying Fu <fu@mips.com>
656 Catherine Moore <clm@codesourcery.com>
657 Maciej W. Rozycki <macro@codesourcery.com>
659 * mips.h: Document microMIPS DSP ASE usage.
660 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
661 microMIPS DSP ASE support.
662 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
663 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
664 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
665 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
666 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
667 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
668 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
670 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
672 * mips.h: Fix a typo in description.
674 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
676 * avr.h: (AVR_ISA_XCH): New define.
677 (AVR_ISA_XMEGA): Use it.
678 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
680 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
682 * m68hc11.h: Add XGate definitions.
683 (struct m68hc11_opcode): Add xg_mask field.
685 2012-05-14 Catherine Moore <clm@codesourcery.com>
686 Maciej W. Rozycki <macro@codesourcery.com>
687 Rhonda Wittels <rhonda@codesourcery.com>
689 * ppc.h (PPC_OPCODE_VLE): New definition.
690 (PPC_OP_SA): New macro.
691 (PPC_OP_SE_VLE): New macro.
692 (PPC_OP): Use a variable shift amount.
693 (powerpc_operand): Update comments.
694 (PPC_OPSHIFT_INV): New macro.
695 (PPC_OPERAND_CR): Replace with...
696 (PPC_OPERAND_CR_BIT): ...this and
697 (PPC_OPERAND_CR_REG): ...this.
700 2012-05-03 Sean Keys <skeys@ipdatasys.com>
702 * xgate.h: Header file for XGATE assembler.
704 2012-04-27 David S. Miller <davem@davemloft.net>
706 * sparc.h: Document new arg code' )' for crypto RS3
709 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
710 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
711 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
712 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
713 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
714 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
715 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
716 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
717 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
718 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
719 HWCAP_CBCOND, HWCAP_CRC32): New defines.
721 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
723 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
725 2012-02-27 Alan Modra <amodra@gmail.com>
727 * crx.h (cst4_map): Update declaration.
729 2012-02-25 Walter Lee <walt@tilera.com>
731 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
733 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
734 TILEPRO_OPC_LW_TLS_SN.
736 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
738 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
739 (XRELEASE_PREFIX_OPCODE): Likewise.
741 2011-12-08 Andrew Pinski <apinski@cavium.com>
742 Adam Nemet <anemet@caviumnetworks.com>
744 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
745 (INSN_OCTEON2): New macro.
746 (CPU_OCTEON2): New macro.
747 (OPCODE_IS_MEMBER): Add Octeon2.
749 2011-11-29 Andrew Pinski <apinski@cavium.com>
751 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
752 (INSN_OCTEONP): New macro.
753 (CPU_OCTEONP): New macro.
754 (OPCODE_IS_MEMBER): Add Octeon+.
755 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
757 2011-11-01 DJ Delorie <dj@redhat.com>
761 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
763 * mips.h: Fix a typo in description.
765 2011-09-21 David S. Miller <davem@davemloft.net>
767 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
768 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
769 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
770 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
772 2011-08-09 Chao-ying Fu <fu@mips.com>
773 Maciej W. Rozycki <macro@codesourcery.com>
775 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
776 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
777 (INSN_ASE_MASK): Add the MCU bit.
778 (INSN_MCU): New macro.
779 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
780 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
782 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
784 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
785 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
786 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
787 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
788 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
789 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
790 (INSN2_READ_GPR_MMN): Likewise.
791 (INSN2_READ_FPR_D): Change the bit used.
792 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
793 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
794 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
795 (INSN2_COND_BRANCH): Likewise.
796 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
797 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
798 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
799 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
800 (INSN2_MOD_GPR_MN): Likewise.
802 2011-08-05 David S. Miller <davem@davemloft.net>
804 * sparc.h: Document new format codes '4', '5', and '('.
805 (OPF_LOW4, RS3): New macros.
807 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
809 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
810 order of flags documented.
812 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
814 * mips.h: Clarify the description of microMIPS instruction
816 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
818 2011-07-24 Chao-ying Fu <fu@mips.com>
819 Maciej W. Rozycki <macro@codesourcery.com>
821 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
822 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
823 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
824 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
825 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
826 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
827 (OP_MASK_RS3, OP_SH_RS3): Likewise.
828 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
829 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
830 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
831 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
832 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
833 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
834 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
835 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
836 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
837 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
838 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
839 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
840 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
841 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
842 (INSN_WRITE_GPR_S): New macro.
843 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
844 (INSN2_READ_FPR_D): Likewise.
845 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
846 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
847 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
848 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
849 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
850 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
851 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
852 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
853 (CPU_MICROMIPS): New macro.
854 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
855 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
856 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
857 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
858 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
859 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
860 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
861 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
862 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
863 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
864 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
865 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
866 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
867 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
868 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
869 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
870 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
871 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
872 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
873 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
874 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
875 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
876 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
877 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
878 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
879 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
880 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
881 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
882 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
883 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
884 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
885 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
886 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
887 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
888 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
889 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
890 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
891 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
892 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
893 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
894 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
895 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
896 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
897 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
898 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
899 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
900 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
901 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
902 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
903 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
904 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
905 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
906 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
907 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
908 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
909 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
910 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
911 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
912 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
913 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
914 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
915 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
916 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
917 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
918 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
919 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
920 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
921 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
922 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
923 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
924 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
925 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
926 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
927 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
928 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
929 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
930 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
931 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
932 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
933 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
934 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
935 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
936 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
937 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
938 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
939 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
940 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
941 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
942 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
943 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
944 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
945 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
946 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
947 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
948 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
949 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
950 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
951 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
952 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
953 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
954 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
955 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
956 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
957 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
958 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
959 (micromips_opcodes): New declaration.
960 (bfd_micromips_num_opcodes): Likewise.
962 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
964 * mips.h (INSN_TRAP): Rename to...
965 (INSN_NO_DELAY_SLOT): ... this.
966 (INSN_SYNC): Remove macro.
968 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
970 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
971 a duplicate of AVR_ISA_SPM.
973 2011-07-01 Nick Clifton <nickc@redhat.com>
975 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
977 2011-06-18 Robin Getz <robin.getz@analog.com>
979 * bfin.h (is_macmod_signed): New func
981 2011-06-18 Mike Frysinger <vapier@gentoo.org>
983 * bfin.h (is_macmod_pmove): Add missing space before func args.
984 (is_macmod_hmove): Likewise.
986 2011-06-13 Walter Lee <walt@tilera.com>
988 * tilegx.h: New file.
989 * tilepro.h: New file.
991 2011-05-31 Paul Brook <paul@codesourcery.com>
993 * arm.h (ARM_ARCH_V7R_IDIV): Define.
995 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
997 * s390.h: Replace S390_OPERAND_REG_EVEN with
998 S390_OPERAND_REG_PAIR.
1000 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1002 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1004 2011-04-18 Julian Brown <julian@codesourcery.com>
1006 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1008 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1011 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1013 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1015 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1016 New instruction set flags.
1017 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1019 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1021 * mips.h (M_PREF_AB): New enum value.
1023 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1025 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1027 (is_macmod_pmove, is_macmod_hmove): New functions.
1029 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1031 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1033 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1035 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1036 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1038 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1041 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1044 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1047 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1049 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1051 * mips.h: Update commentary after last commit.
1053 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1055 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1056 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1057 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1059 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1061 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1063 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1065 * mips.h: Fix previous commit.
1067 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1069 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1070 (INSN_LOONGSON_3A): Clear bit 31.
1072 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1075 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1076 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1077 (ARM_ARCH_V6M_ONLY): New define.
1079 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1081 * mips.h (INSN_LOONGSON_3A): Defined.
1082 (CPU_LOONGSON_3A): Defined.
1083 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1085 2010-10-09 Matt Rice <ratmice@gmail.com>
1087 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1088 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1090 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1092 * arm.h (ARM_EXT_VIRT): New define.
1093 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1094 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1097 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1099 * arm.h (ARM_AEXT_ADIV): New define.
1100 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1102 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1104 * arm.h (ARM_EXT_OS): New define.
1105 (ARM_AEXT_V6SM): Likewise.
1106 (ARM_ARCH_V6SM): Likewise.
1108 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1110 * arm.h (ARM_EXT_MP): Add.
1111 (ARM_ARCH_V7A_MP): Likewise.
1113 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1115 * bfin.h: Declare pseudoChr structs/defines.
1117 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1119 * bfin.h: Strip trailing whitespace.
1121 2010-07-29 DJ Delorie <dj@redhat.com>
1123 * rx.h (RX_Operand_Type): Add TwoReg.
1124 (RX_Opcode_ID): Remove ediv and ediv2.
1126 2010-07-27 DJ Delorie <dj@redhat.com>
1128 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1130 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1131 Ina Pandit <ina.pandit@kpitcummins.com>
1133 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1134 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1135 PROCESSOR_V850E2_ALL.
1136 Remove PROCESSOR_V850EA support.
1137 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1138 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1139 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1140 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1141 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1142 V850_OPERAND_PERCENT.
1143 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1145 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1148 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1150 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1151 (MIPS16_INSN_BRANCH): Rename to...
1152 (MIPS16_INSN_COND_BRANCH): ... this.
1154 2010-07-03 Alan Modra <amodra@gmail.com>
1156 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1157 Renumber other PPC_OPCODE defines.
1159 2010-07-03 Alan Modra <amodra@gmail.com>
1161 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1163 2010-06-29 Alan Modra <amodra@gmail.com>
1165 * maxq.h: Delete file.
1167 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1169 * ppc.h (PPC_OPCODE_E500): Define.
1171 2010-05-26 Catherine Moore <clm@codesourcery.com>
1173 * opcode/mips.h (INSN_MIPS16): Remove.
1175 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1177 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1179 2010-04-15 Nick Clifton <nickc@redhat.com>
1181 * alpha.h: Update copyright notice to use GPLv3.
1187 * convex.h: Likewise.
1194 * h8300.h: Likewise.
1201 * m68hc11.h: Likewise.
1207 * mn10200.h: Likewise.
1208 * mn10300.h: Likewise.
1209 * msp430.h: Likewise.
1211 * ns32k.h: Likewise.
1213 * pdp11.h: Likewise.
1220 * score-datadep.h: Likewise.
1221 * score-inst.h: Likewise.
1222 * sparc.h: Likewise.
1223 * spu-insns.h: Likewise.
1225 * tic30.h: Likewise.
1226 * tic4x.h: Likewise.
1227 * tic54x.h: Likewise.
1228 * tic80.h: Likewise.
1232 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1234 * tic6x-control-registers.h, tic6x-insn-formats.h,
1235 tic6x-opcode-table.h, tic6x.h: New.
1237 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1239 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1241 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1243 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1245 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1247 * ia64.h (ia64_find_opcode): Remove argument name.
1248 (ia64_find_next_opcode): Likewise.
1249 (ia64_dis_opcode): Likewise.
1250 (ia64_free_opcode): Likewise.
1251 (ia64_find_dependency): Likewise.
1253 2009-11-22 Doug Evans <dje@sebabeach.org>
1255 * cgen.h: Include bfd_stdint.h.
1256 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1258 2009-11-18 Paul Brook <paul@codesourcery.com>
1260 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1262 2009-11-17 Paul Brook <paul@codesourcery.com>
1263 Daniel Jacobowitz <dan@codesourcery.com>
1265 * arm.h (ARM_EXT_V6_DSP): Define.
1266 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1267 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1269 2009-11-04 DJ Delorie <dj@redhat.com>
1271 * rx.h (rx_decode_opcode) (mvtipl): Add.
1272 (mvtcp, mvfcp, opecp): Remove.
1274 2009-11-02 Paul Brook <paul@codesourcery.com>
1276 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1277 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1278 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1279 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1280 FPU_ARCH_NEON_VFP_V4): Define.
1282 2009-10-23 Doug Evans <dje@sebabeach.org>
1284 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1285 * cgen.h: Update. Improve multi-inclusion macro name.
1287 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1289 * ppc.h (PPC_OPCODE_476): Define.
1291 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1293 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1295 2009-09-29 DJ Delorie <dj@redhat.com>
1299 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1301 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1303 2009-09-21 Ben Elliston <bje@au.ibm.com>
1305 * ppc.h (PPC_OPCODE_PPCA2): New.
1307 2009-09-05 Martin Thuresson <martin@mtme.org>
1309 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1311 2009-08-29 Martin Thuresson <martin@mtme.org>
1313 * tic30.h (template): Rename type template to
1314 insn_template. Updated code to use new name.
1315 * tic54x.h (template): Rename type template to
1318 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1320 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1322 2009-06-11 Anthony Green <green@moxielogic.com>
1324 * moxie.h (MOXIE_F3_PCREL): Define.
1325 (moxie_form3_opc_info): Grow.
1327 2009-06-06 Anthony Green <green@moxielogic.com>
1329 * moxie.h (MOXIE_F1_M): Define.
1331 2009-04-15 Anthony Green <green@moxielogic.com>
1335 2009-04-06 DJ Delorie <dj@redhat.com>
1337 * h8300.h: Add relaxation attributes to MOVA opcodes.
1339 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1341 * ppc.h (ppc_parse_cpu): Declare.
1343 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1345 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1346 and _IMM11 for mbitclr and mbitset.
1347 * score-datadep.h: Update dependency information.
1349 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1351 * ppc.h (PPC_OPCODE_POWER7): New.
1353 2009-02-06 Doug Evans <dje@google.com>
1355 * i386.h: Add comment regarding sse* insns and prefixes.
1357 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1359 * mips.h (INSN_XLR): Define.
1360 (INSN_CHIP_MASK): Update.
1362 (OPCODE_IS_MEMBER): Update.
1363 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1365 2009-01-28 Doug Evans <dje@google.com>
1367 * opcode/i386.h: Add multiple inclusion protection.
1368 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1369 (EDI_REG_NUM): New macros.
1370 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1371 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1372 (REX_PREFIX_P): New macro.
1374 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1376 * ppc.h (struct powerpc_opcode): New field "deprecated".
1377 (PPC_OPCODE_NOPOWER4): Delete.
1379 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1381 * mips.h: Define CPU_R14000, CPU_R16000.
1382 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1384 2008-11-18 Catherine Moore <clm@codesourcery.com>
1386 * arm.h (FPU_NEON_FP16): New.
1387 (FPU_ARCH_NEON_FP16): New.
1389 2008-11-06 Chao-ying Fu <fu@mips.com>
1391 * mips.h: Doucument '1' for 5-bit sync type.
1393 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1395 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1398 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1400 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1402 2008-07-30 Michael J. Eager <eager@eagercon.com>
1404 * ppc.h (PPC_OPCODE_405): Define.
1405 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1407 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1409 * ppc.h (ppc_cpu_t): New typedef.
1410 (struct powerpc_opcode <flags>): Use it.
1411 (struct powerpc_operand <insert, extract>): Likewise.
1412 (struct powerpc_macro <flags>): Likewise.
1414 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1416 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1417 Update comment before MIPS16 field descriptors to mention MIPS16.
1418 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1420 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1421 New bit masks and shift counts for cins and exts.
1423 * mips.h: Document new field descriptors +Q.
1424 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1426 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1428 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1429 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1431 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1433 * ppc.h: (PPC_OPCODE_E500MC): New.
1435 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1437 * i386.h (MAX_OPERANDS): Set to 5.
1438 (MAX_MNEM_SIZE): Changed to 20.
1440 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1442 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1444 2008-03-09 Paul Brook <paul@codesourcery.com>
1446 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1448 2008-03-04 Paul Brook <paul@codesourcery.com>
1450 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1451 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1452 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1454 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1455 Nick Clifton <nickc@redhat.com>
1458 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1459 with a 32-bit displacement but without the top bit of the 4th byte
1462 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1464 * cr16.h (cr16_num_optab): Declared.
1466 2008-02-14 Hakan Ardo <hakan@debian.org>
1469 * avr.h (AVR_ISA_2xxe): Define.
1471 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1473 * mips.h: Update copyright.
1474 (INSN_CHIP_MASK): New macro.
1475 (INSN_OCTEON): New macro.
1476 (CPU_OCTEON): New macro.
1477 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1479 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1481 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1483 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1485 * avr.h (AVR_ISA_USB162): Add new opcode set.
1486 (AVR_ISA_AVR3): Likewise.
1488 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1490 * mips.h (INSN_LOONGSON_2E): New.
1491 (INSN_LOONGSON_2F): New.
1492 (CPU_LOONGSON_2E): New.
1493 (CPU_LOONGSON_2F): New.
1494 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1496 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1498 * mips.h (INSN_ISA*): Redefine certain values as an
1499 enumeration. Update comments.
1500 (mips_isa_table): New.
1501 (ISA_MIPS*): Redefine to match enumeration.
1502 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1505 2007-08-08 Ben Elliston <bje@au.ibm.com>
1507 * ppc.h (PPC_OPCODE_PPCPS): New.
1509 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1511 * m68k.h: Document j K & E.
1513 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1515 * cr16.h: New file for CR16 target.
1517 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1519 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1521 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1523 * m68k.h (mcfisa_c): New.
1524 (mcfusp, mcf_mask): Adjust.
1526 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1528 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1529 (num_powerpc_operands): Declare.
1530 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1531 (PPC_OPERAND_PLUS1): Define.
1533 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1535 * i386.h (REX_MODE64): Renamed to ...
1537 (REX_EXTX): Renamed to ...
1539 (REX_EXTY): Renamed to ...
1541 (REX_EXTZ): Renamed to ...
1544 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1546 * i386.h: Add entries from config/tc-i386.h and move tables
1547 to opcodes/i386-opc.h.
1549 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1551 * i386.h (FloatDR): Removed.
1552 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1554 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1556 * spu-insns.h: Add soma double-float insns.
1558 2007-02-20 Thiemo Seufer <ths@mips.com>
1559 Chao-Ying Fu <fu@mips.com>
1561 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1562 (INSN_DSPR2): Add flag for DSP R2 instructions.
1563 (M_BALIGN): New macro.
1565 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1567 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1568 and Seg3ShortFrom with Shortform.
1570 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1573 * i386.h (i386_optab): Put the real "test" before the pseudo
1576 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1578 * m68k.h (m68010up): OR fido_a.
1580 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1582 * m68k.h (fido_a): New.
1584 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1586 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1587 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1590 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1594 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1596 * score-inst.h (enum score_insn_type): Add Insn_internal.
1598 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1599 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1600 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1601 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1602 Alan Modra <amodra@bigpond.net.au>
1604 * spu-insns.h: New file.
1607 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1609 * ppc.h (PPC_OPCODE_CELL): Define.
1611 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1613 * i386.h : Modify opcode to support for the change in POPCNT opcode
1614 in amdfam10 architecture.
1616 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1618 * i386.h: Replace CpuMNI with CpuSSSE3.
1620 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1621 Joseph Myers <joseph@codesourcery.com>
1622 Ian Lance Taylor <ian@wasabisystems.com>
1623 Ben Elliston <bje@wasabisystems.com>
1625 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1627 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1629 * score-datadep.h: New file.
1630 * score-inst.h: New file.
1632 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1634 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1635 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1636 movdq2q and movq2dq.
1638 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1639 Michael Meissner <michael.meissner@amd.com>
1641 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1643 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1645 * i386.h (i386_optab): Add "nop" with memory reference.
1647 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1649 * i386.h (i386_optab): Update comment for 64bit NOP.
1651 2006-06-06 Ben Elliston <bje@au.ibm.com>
1652 Anton Blanchard <anton@samba.org>
1654 * ppc.h (PPC_OPCODE_POWER6): Define.
1657 2006-06-05 Thiemo Seufer <ths@mips.com>
1659 * mips.h: Improve description of MT flags.
1661 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1663 * m68k.h (mcf_mask): Define.
1665 2006-05-05 Thiemo Seufer <ths@mips.com>
1666 David Ung <davidu@mips.com>
1668 * mips.h (enum): Add macro M_CACHE_AB.
1670 2006-05-04 Thiemo Seufer <ths@mips.com>
1671 Nigel Stephens <nigel@mips.com>
1672 David Ung <davidu@mips.com>
1674 * mips.h: Add INSN_SMARTMIPS define.
1676 2006-04-30 Thiemo Seufer <ths@mips.com>
1677 David Ung <davidu@mips.com>
1679 * mips.h: Defines udi bits and masks. Add description of
1680 characters which may appear in the args field of udi
1683 2006-04-26 Thiemo Seufer <ths@networkno.de>
1685 * mips.h: Improve comments describing the bitfield instruction
1688 2006-04-26 Julian Brown <julian@codesourcery.com>
1690 * arm.h (FPU_VFP_EXT_V3): Define constant.
1691 (FPU_NEON_EXT_V1): Likewise.
1692 (FPU_VFP_HARD): Update.
1693 (FPU_VFP_V3): Define macro.
1694 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1696 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1698 * avr.h (AVR_ISA_PWMx): New.
1700 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1702 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1703 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1704 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1705 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1706 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1708 2006-03-10 Paul Brook <paul@codesourcery.com>
1710 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1712 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1714 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1715 first. Correct mask of bb "B" opcode.
1717 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1719 * i386.h (i386_optab): Support Intel Merom New Instructions.
1721 2006-02-24 Paul Brook <paul@codesourcery.com>
1723 * arm.h: Add V7 feature bits.
1725 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1727 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1729 2006-01-31 Paul Brook <paul@codesourcery.com>
1730 Richard Earnshaw <rearnsha@arm.com>
1732 * arm.h: Use ARM_CPU_FEATURE.
1733 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1734 (arm_feature_set): Change to a structure.
1735 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1736 ARM_FEATURE): New macros.
1738 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1740 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1741 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1742 (ADD_PC_INCR_OPCODE): Don't define.
1744 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1749 2005-11-14 David Ung <davidu@mips.com>
1751 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1752 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1753 save/restore encoding of the args field.
1755 2005-10-28 Dave Brolley <brolley@redhat.com>
1757 Contribute the following changes:
1758 2005-02-16 Dave Brolley <brolley@redhat.com>
1760 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1761 cgen_isa_mask_* to cgen_bitset_*.
1764 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1766 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1767 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1768 (CGEN_CPU_TABLE): Make isas a ponter.
1770 2003-09-29 Dave Brolley <brolley@redhat.com>
1772 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1773 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1774 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1776 2002-12-13 Dave Brolley <brolley@redhat.com>
1778 * cgen.h (symcat.h): #include it.
1779 (cgen-bitset.h): #include it.
1780 (CGEN_ATTR_VALUE_TYPE): Now a union.
1781 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1782 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1783 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1784 * cgen-bitset.h: New file.
1786 2005-09-30 Catherine Moore <clm@cm00re.com>
1790 2005-10-24 Jan Beulich <jbeulich@novell.com>
1792 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1795 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1797 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1798 Add FLAG_STRICT to pa10 ftest opcode.
1800 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1802 * hppa.h (pa_opcodes): Remove lha entries.
1804 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1806 * hppa.h (FLAG_STRICT): Revise comment.
1807 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1808 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1811 2005-09-30 Catherine Moore <clm@cm00re.com>
1815 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1817 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1819 2005-09-06 Chao-ying Fu <fu@mips.com>
1821 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1822 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1824 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1825 (INSN_ASE_MASK): Update to include INSN_MT.
1826 (INSN_MT): New define for MT ASE.
1828 2005-08-25 Chao-ying Fu <fu@mips.com>
1830 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1831 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1832 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1833 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1834 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1835 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1837 (INSN_DSP): New define for DSP ASE.
1839 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1843 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1845 * ppc.h (PPC_OPCODE_E300): Define.
1847 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1849 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1851 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1854 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1857 2005-07-27 Jan Beulich <jbeulich@novell.com>
1859 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1860 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1861 Add movq-s as 64-bit variants of movd-s.
1863 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1865 * hppa.h: Fix punctuation in comment.
1867 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1868 implicit space-register addressing. Set space-register bits on opcodes
1869 using implicit space-register addressing. Add various missing pa20
1870 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1871 space-register addressing. Use "fE" instead of "fe" in various
1874 2005-07-18 Jan Beulich <jbeulich@novell.com>
1876 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1878 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1880 * i386.h (i386_optab): Support Intel VMX Instructions.
1882 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1884 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1886 2005-07-05 Jan Beulich <jbeulich@novell.com>
1888 * i386.h (i386_optab): Add new insns.
1890 2005-07-01 Nick Clifton <nickc@redhat.com>
1892 * sparc.h: Add typedefs to structure declarations.
1894 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1897 * i386.h (i386_optab): Update comments for 64bit addressing on
1898 mov. Allow 64bit addressing for mov and movq.
1900 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1902 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1903 respectively, in various floating-point load and store patterns.
1905 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1907 * hppa.h (FLAG_STRICT): Correct comment.
1908 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1909 PA 2.0 mneumonics when equivalent. Entries with cache control
1910 completers now require PA 1.1. Adjust whitespace.
1912 2005-05-19 Anton Blanchard <anton@samba.org>
1914 * ppc.h (PPC_OPCODE_POWER5): Define.
1916 2005-05-10 Nick Clifton <nickc@redhat.com>
1918 * Update the address and phone number of the FSF organization in
1919 the GPL notices in the following files:
1920 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1921 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1922 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1923 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1924 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1925 tic54x.h, tic80.h, v850.h, vax.h
1927 2005-05-09 Jan Beulich <jbeulich@novell.com>
1929 * i386.h (i386_optab): Add ht and hnt.
1931 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1933 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1934 Add xcrypt-ctr. Provide aliases without hyphens.
1936 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1938 Moved from ../ChangeLog
1940 2005-04-12 Paul Brook <paul@codesourcery.com>
1941 * m88k.h: Rename psr macros to avoid conflicts.
1943 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1944 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1945 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1946 and ARM_ARCH_V6ZKT2.
1948 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1949 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1950 Remove redundant instruction types.
1951 (struct argument): X_op - new field.
1952 (struct cst4_entry): Remove.
1953 (no_op_insn): Declare.
1955 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1956 * crx.h (enum argtype): Rename types, remove unused types.
1958 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1959 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1960 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1961 (enum operand_type): Rearrange operands, edit comments.
1962 replace us<N> with ui<N> for unsigned immediate.
1963 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1964 displacements (respectively).
1965 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1966 (instruction type): Add NO_TYPE_INS.
1967 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1968 (operand_entry): New field - 'flags'.
1969 (operand flags): New.
1971 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1972 * crx.h (operand_type): Remove redundant types i3, i4,
1974 Add new unsigned immediate types us3, us4, us5, us16.
1976 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1978 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1979 adjust them accordingly.
1981 2005-04-01 Jan Beulich <jbeulich@novell.com>
1983 * i386.h (i386_optab): Add rdtscp.
1985 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1987 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1988 between memory and segment register. Allow movq for moving between
1989 general-purpose register and segment register.
1991 2005-02-09 Jan Beulich <jbeulich@novell.com>
1994 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1995 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1998 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2000 * m68k.h (m68008, m68ec030, m68882): Remove.
2002 (cpu_m68k, cpu_cf): New.
2003 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2004 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2006 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2008 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2009 * cgen.h (enum cgen_parse_operand_type): Add
2010 CGEN_PARSE_OPERAND_SYMBOLIC.
2012 2005-01-21 Fred Fish <fnf@specifixinc.com>
2014 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2015 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2016 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2018 2005-01-19 Fred Fish <fnf@specifixinc.com>
2020 * mips.h (struct mips_opcode): Add new pinfo2 member.
2021 (INSN_ALIAS): New define for opcode table entries that are
2022 specific instances of another entry, such as 'move' for an 'or'
2023 with a zero operand.
2024 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2025 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2027 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2029 * mips.h (CPU_RM9000): Define.
2030 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2032 2004-11-25 Jan Beulich <jbeulich@novell.com>
2034 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2035 to/from test registers are illegal in 64-bit mode. Add missing
2036 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2037 (previously one had to explicitly encode a rex64 prefix). Re-enable
2038 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2039 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2041 2004-11-23 Jan Beulich <jbeulich@novell.com>
2043 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2044 available only with SSE2. Change the MMX additions introduced by SSE
2045 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2046 instructions by their now designated identifier (since combining i686
2047 and 3DNow! does not really imply 3DNow!A).
2049 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2051 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2052 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2054 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2055 Vineet Sharma <vineets@noida.hcltech.com>
2057 * maxq.h: New file: Disassembly information for the maxq port.
2059 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2061 * i386.h (i386_optab): Put back "movzb".
2063 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2065 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2066 comments. Remove member cris_ver_sim. Add members
2067 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2068 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2069 (struct cris_support_reg, struct cris_cond15): New types.
2070 (cris_conds15): Declare.
2071 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2072 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2073 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2074 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2075 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2076 SIZE_FIELD_UNSIGNED.
2078 2004-11-04 Jan Beulich <jbeulich@novell.com>
2080 * i386.h (sldx_Suf): Remove.
2081 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2082 (q_FP): Define, implying no REX64.
2083 (x_FP, sl_FP): Imply FloatMF.
2084 (i386_optab): Split reg and mem forms of moving from segment registers
2085 so that the memory forms can ignore the 16-/32-bit operand size
2086 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2087 all non-floating-point instructions. Unite 32- and 64-bit forms of
2088 movsx, movzx, and movd. Adjust floating point operations for the above
2089 changes to the *FP macros. Add DefaultSize to floating point control
2090 insns operating on larger memory ranges. Remove left over comments
2091 hinting at certain insns being Intel-syntax ones where the ones
2092 actually meant are already gone.
2094 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2096 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2099 2004-09-30 Paul Brook <paul@codesourcery.com>
2101 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2102 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2104 2004-09-11 Theodore A. Roth <troth@openavr.org>
2106 * avr.h: Add support for
2107 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2109 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2111 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2113 2004-08-24 Dmitry Diky <diwil@spec.ru>
2115 * msp430.h (msp430_opc): Add new instructions.
2116 (msp430_rcodes): Declare new instructions.
2117 (msp430_hcodes): Likewise..
2119 2004-08-13 Nick Clifton <nickc@redhat.com>
2122 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2125 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2127 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2129 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2131 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2133 2004-07-21 Jan Beulich <jbeulich@novell.com>
2135 * i386.h: Adjust instruction descriptions to better match the
2138 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2140 * arm.h: Remove all old content. Replace with architecture defines
2141 from gas/config/tc-arm.c.
2143 2004-07-09 Andreas Schwab <schwab@suse.de>
2145 * m68k.h: Fix comment.
2147 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2151 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2153 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2155 2004-05-24 Peter Barada <peter@the-baradas.com>
2157 * m68k.h: Add 'size' to m68k_opcode.
2159 2004-05-05 Peter Barada <peter@the-baradas.com>
2161 * m68k.h: Switch from ColdFire chip name to core variant.
2163 2004-04-22 Peter Barada <peter@the-baradas.com>
2165 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2166 descriptions for new EMAC cases.
2167 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2168 handle Motorola MAC syntax.
2169 Allow disassembly of ColdFire V4e object files.
2171 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2173 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2175 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2177 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2179 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2181 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2183 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2185 * i386.h (i386_optab): Added xstore/xcrypt insns.
2187 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2189 * h8300.h (32bit ldc/stc): Add relaxing support.
2191 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2193 * h8300.h (BITOP): Pass MEMRELAX flag.
2195 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2197 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2200 For older changes see ChangeLog-9103
2202 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2204 Copying and distribution of this file, with or without modification,
2205 are permitted in any medium without royalty provided the copyright
2206 notice and this notice are preserved.
2212 version-control: never