1 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
3 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
4 declaration. Fix obsolete comment.
6 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
8 * nios2.h (enum iw_format_type): New.
9 (struct nios2_opcode): Update comments. Add size and format fields.
10 (NIOS2_INSN_OPTARG): New.
11 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
12 (struct nios2_reg): Add regtype field.
13 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
14 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
15 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
16 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
17 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
18 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
19 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
20 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
21 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
22 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
23 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
24 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
25 (OP_MASK_OP, OP_SH_OP): Delete.
26 (OP_MASK_IOP, OP_SH_IOP): Delete.
27 (OP_MASK_IRD, OP_SH_IRD): Delete.
28 (OP_MASK_IRT, OP_SH_IRT): Delete.
29 (OP_MASK_IRS, OP_SH_IRS): Delete.
30 (OP_MASK_ROP, OP_SH_ROP): Delete.
31 (OP_MASK_RRD, OP_SH_RRD): Delete.
32 (OP_MASK_RRT, OP_SH_RRT): Delete.
33 (OP_MASK_RRS, OP_SH_RRS): Delete.
34 (OP_MASK_JOP, OP_SH_JOP): Delete.
35 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
36 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
37 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
38 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
39 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
40 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
41 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
42 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
43 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
44 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
45 (OP_MASK_<insn>, OP_MASK): Delete.
46 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
47 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
48 Include nios2r1.h to define new instruction opcode constants
50 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
51 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
52 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
53 (NUMOPCODES, NUMREGISTERS): Delete.
54 * nios2r1.h: New file.
56 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
58 * sparc.h (HWCAP2_VIS3B): Documentation improved.
60 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
62 * sparc.h (sparc_opcode): new field `hwcaps2'.
63 (HWCAP2_FJATHPLUS): New define.
64 (HWCAP2_VIS3B): Likewise.
65 (HWCAP2_ADP): Likewise.
66 (HWCAP2_SPARC5): Likewise.
67 (HWCAP2_MWAIT): Likewise.
68 (HWCAP2_XMPMUL): Likewise.
69 (HWCAP2_XMONT): Likewise.
70 (HWCAP2_NSEC): Likewise.
71 (HWCAP2_FJATHHPC): Likewise.
72 (HWCAP2_FJDES): Likewise.
73 (HWCAP2_FJAES): Likewise.
74 Document the new operand kind `{', corresponding to the mcdper
75 ancillary state register.
76 Document the new operand kind }, which represents frsd floating
77 point registers (double precision) which must be the same than
78 frs1 in its containing instruction.
80 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
82 * nds32.h: Add new opcode declaration.
84 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
85 Matthew Fortune <matthew.fortune@imgtec.com>
87 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
88 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
89 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
90 +I, +O, +R, +:, +\, +", +;
91 (mips_check_prev_operand): New struct.
92 (INSN2_FORBIDDEN_SLOT): New define.
93 (INSN_ISA32R6): New define.
94 (INSN_ISA64R6): New define.
95 (INSN_UPTO32R6): New define.
96 (INSN_UPTO64R6): New define.
97 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
98 (ISA_MIPS32R6): New define.
99 (ISA_MIPS64R6): New define.
100 (CPU_MIPS32R6): New define.
101 (CPU_MIPS64R6): New define.
102 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
104 2014-09-03 Jiong Wang <jiong.wang@arm.com>
106 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
107 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
108 (aarch64_insn_class): Add lse_atomic.
109 (F_LSE_SZ): New field added.
110 (opcode_has_special_coder): Recognize F_LSE_SZ.
112 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
114 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
117 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
119 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
120 (INSN_LOAD_COPROC): New define.
121 (INSN_COPROC_MOVE_DELAY): Rename to...
122 (INSN_COPROC_MOVE): New define.
124 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
125 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
126 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
127 Soundararajan <Sounderarajan.D@atmel.com>
129 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
130 (AVR_ISA_2xxxa): Define ISA without LPM.
131 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
132 Add doc for contraint used in 16 bit lds/sts.
133 Adjust ISA group for icall, ijmp, pop and push.
134 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
136 2014-05-19 Nick Clifton <nickc@redhat.com>
138 * msp430.h (struct msp430_operand_s): Add vshift field.
140 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
142 * mips.h (INSN_ISA_MASK): Updated.
143 (INSN_ISA32R3): New define.
144 (INSN_ISA32R5): New define.
145 (INSN_ISA64R3): New define.
146 (INSN_ISA64R5): New define.
147 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
148 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
149 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
151 (INSN_UPTO32R3): New define.
152 (INSN_UPTO32R5): New define.
153 (INSN_UPTO64R3): New define.
154 (INSN_UPTO64R5): New define.
155 (ISA_MIPS32R3): New define.
156 (ISA_MIPS32R5): New define.
157 (ISA_MIPS64R3): New define.
158 (ISA_MIPS64R5): New define.
159 (CPU_MIPS32R3): New define.
160 (CPU_MIPS32R5): New define.
161 (CPU_MIPS64R3): New define.
162 (CPU_MIPS64R5): New define.
164 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
166 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
168 2014-04-22 Christian Svensson <blue@cmd.nu>
172 2014-03-05 Alan Modra <amodra@gmail.com>
174 Update copyright years.
176 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
178 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
181 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
182 Wei-Cheng Wang <cole945@gmail.com>
184 * nds32.h: New file for Andes NDS32.
186 2013-12-07 Mike Frysinger <vapier@gentoo.org>
188 * bfin.h: Remove +x file mode.
190 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
192 * aarch64.h (aarch64_pstatefields): Change element type to
195 2013-11-18 Renlin Li <Renlin.Li@arm.com>
197 * arm.h (ARM_AEXT_V7VE): New define.
198 (ARM_ARCH_V7VE): New define.
199 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
201 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
205 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
207 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
208 (aarch64_sys_reg_writeonly_p): Ditto.
210 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
212 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
213 (aarch64_sys_reg_writeonly_p): Ditto.
215 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
217 * aarch64.h (aarch64_sys_reg): New typedef.
218 (aarch64_sys_regs): Change to define with the new type.
219 (aarch64_sys_reg_deprecated_p): Declare.
221 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
223 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
224 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
226 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
228 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
229 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
230 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
231 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
232 For MIPS, update extension character sequences after +.
233 (ASE_MSA): New define.
234 (ASE_MSA64): New define.
235 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
236 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
237 For microMIPS, update extension character sequences after +.
239 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
244 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
246 * mips.h: Remove references to "+I" and imm2_expr.
248 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
250 * mips.h (M_DEXT, M_DINS): Delete.
252 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
254 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
255 (mips_optional_operand_p): New function.
257 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
258 Richard Sandiford <rdsandiford@googlemail.com>
260 * mips.h: Document new VU0 operand characters.
261 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
262 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
263 (OP_REG_R5900_ACC): New mips_reg_operand_types.
264 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
265 (mips_vu0_channel_mask): Declare.
267 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
269 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
270 (mips_int_operand_min, mips_int_operand_max): New functions.
271 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
273 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
275 * mips.h (mips_decode_reg_operand): New function.
276 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
277 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
278 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
280 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
281 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
282 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
283 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
284 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
285 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
286 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
287 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
288 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
289 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
290 macros to cover the gaps.
291 (INSN2_MOD_SP): Replace with...
292 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
293 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
294 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
295 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
296 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
299 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
301 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
302 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
303 (MIPS16_INSN_COND_BRANCH): Delete.
305 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
306 Kirill Yukhin <kirill.yukhin@intel.com>
307 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
309 * i386.h (BND_PREFIX_OPCODE): New.
311 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
313 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
314 OP_SAVE_RESTORE_LIST.
315 (decode_mips16_operand): Declare.
317 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
319 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
320 (mips_operand, mips_int_operand, mips_mapped_int_operand)
321 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
322 (mips_pcrel_operand): New structures.
323 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
324 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
325 (decode_mips_operand, decode_micromips_operand): Declare.
327 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
329 * mips.h: Document MIPS16 "I" opcode.
331 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
333 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
334 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
335 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
336 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
337 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
338 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
339 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
340 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
341 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
342 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
343 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
344 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
345 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
347 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
348 (M_USD_AB): ...these.
350 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
352 * mips.h: Remove documentation of "[" and "]". Update documentation
353 of "k" and the MDMX formats.
355 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
357 * mips.h: Update documentation of "+s" and "+S".
359 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
361 * mips.h: Document "+i".
363 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
365 * mips.h: Remove "mi" documentation. Update "mh" documentation.
366 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
368 (INSN2_WRITE_GPR_MHI): Rename to...
369 (INSN2_WRITE_GPR_MH): ...this.
371 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
373 * mips.h: Remove documentation of "+D" and "+T".
375 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
377 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
378 Use "source" rather than "destination" for microMIPS "G".
380 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
382 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
385 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
387 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
389 2013-06-17 Catherine Moore <clm@codesourcery.com>
390 Maciej W. Rozycki <macro@codesourcery.com>
391 Chao-Ying Fu <fu@mips.com>
393 * mips.h (OP_SH_EVAOFFSET): Define.
394 (OP_MASK_EVAOFFSET): Define.
395 (INSN_ASE_MASK): Delete.
397 (M_CACHEE_AB, M_CACHEE_OB): New.
398 (M_LBE_OB, M_LBE_AB): New.
399 (M_LBUE_OB, M_LBUE_AB): New.
400 (M_LHE_OB, M_LHE_AB): New.
401 (M_LHUE_OB, M_LHUE_AB): New.
402 (M_LLE_AB, M_LLE_OB): New.
403 (M_LWE_OB, M_LWE_AB): New.
404 (M_LWLE_AB, M_LWLE_OB): New.
405 (M_LWRE_AB, M_LWRE_OB): New.
406 (M_PREFE_AB, M_PREFE_OB): New.
407 (M_SCE_AB, M_SCE_OB): New.
408 (M_SBE_OB, M_SBE_AB): New.
409 (M_SHE_OB, M_SHE_AB): New.
410 (M_SWE_OB, M_SWE_AB): New.
411 (M_SWLE_AB, M_SWLE_OB): New.
412 (M_SWRE_AB, M_SWRE_OB): New.
413 (MICROMIPSOP_SH_EVAOFFSET): Define.
414 (MICROMIPSOP_MASK_EVAOFFSET): Define.
416 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
418 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
420 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
422 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
424 2013-05-09 Andrew Pinski <apinski@cavium.com>
426 * mips.h (OP_MASK_CODE10): Correct definition.
427 (OP_SH_CODE10): Likewise.
428 Add a comment that "+J" is used now for OP_*CODE10.
429 (INSN_ASE_MASK): Update.
430 (INSN_VIRT): New macro.
431 (INSN_VIRT64): New macro
433 2013-05-02 Nick Clifton <nickc@redhat.com>
435 * msp430.h: Add patterns for MSP430X instructions.
437 2013-04-06 David S. Miller <davem@davemloft.net>
439 * sparc.h (F_PREFERRED): Define.
440 (F_PREF_ALIAS): Define.
442 2013-04-03 Nick Clifton <nickc@redhat.com>
444 * v850.h (V850_INVERSE_PCREL): Define.
446 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
449 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
451 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
454 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
456 * tic6xc-opcode-table.h: Add 16-bit insns.
457 * tic6x.h: Add support for 16-bit insns.
459 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
461 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
462 and mov.b/w/l Rs,@(d:32,ERd).
464 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
467 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
468 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
469 tic6x_operand_xregpair operand coding type.
470 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
471 opcode field, usu ORXREGD1324 for the src2 operand and remove the
474 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
477 * tic6x.h (enum tic6x_coding_method): Add
478 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
479 separately the msb and lsb of a register pair. This is needed to
480 encode the opcodes in the same way as TI assembler does.
481 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
482 and rsqrdp opcodes to use the new field coding types.
484 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
486 * arm.h (CRC_EXT_ARMV8): New constant.
487 (ARCH_CRC_ARMV8): New macro.
489 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
491 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
493 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
494 Andrew Jenner <andrew@codesourcery.com>
496 Based on patches from Altera Corporation.
500 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
502 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
504 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
507 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
509 2013-01-24 Nick Clifton <nickc@redhat.com>
511 * v850.h: Add e3v5 support.
513 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
515 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
517 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
519 * ppc.h (PPC_OPCODE_POWER8): New define.
520 (PPC_OPCODE_HTM): Likewise.
522 2013-01-10 Will Newton <will.newton@imgtec.com>
526 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
528 * cr16.h (make_instruction): Rename to cr16_make_instruction.
529 (match_opcode): Rename to cr16_match_opcode.
531 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
533 * mips.h: Add support for r5900 instructions including lq and sq.
535 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
537 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
538 (make_instruction,match_opcode): Added function prototypes.
539 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
541 2012-11-23 Alan Modra <amodra@gmail.com>
543 * ppc.h (ppc_parse_cpu): Update prototype.
545 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
547 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
548 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
550 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
552 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
554 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
556 * ia64.h (ia64_opnd): Add new operand types.
558 2012-08-21 David S. Miller <davem@davemloft.net>
560 * sparc.h (F3F4): New macro.
562 2012-08-13 Ian Bolton <ian.bolton@arm.com>
563 Laurent Desnogues <laurent.desnogues@arm.com>
564 Jim MacArthur <jim.macarthur@arm.com>
565 Marcus Shawcroft <marcus.shawcroft@arm.com>
566 Nigel Stephens <nigel.stephens@arm.com>
567 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
568 Richard Earnshaw <rearnsha@arm.com>
569 Sofiane Naci <sofiane.naci@arm.com>
570 Tejas Belagod <tejas.belagod@arm.com>
571 Yufeng Zhang <yufeng.zhang@arm.com>
573 * aarch64.h: New file.
575 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
576 Maciej W. Rozycki <macro@codesourcery.com>
578 * mips.h (mips_opcode): Add the exclusions field.
579 (OPCODE_IS_MEMBER): Remove macro.
580 (cpu_is_member): New inline function.
581 (opcode_is_member): Likewise.
583 2012-07-31 Chao-Ying Fu <fu@mips.com>
584 Catherine Moore <clm@codesourcery.com>
585 Maciej W. Rozycki <macro@codesourcery.com>
587 * mips.h: Document microMIPS DSP ASE usage.
588 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
589 microMIPS DSP ASE support.
590 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
591 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
592 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
593 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
594 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
595 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
596 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
598 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
600 * mips.h: Fix a typo in description.
602 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
604 * avr.h: (AVR_ISA_XCH): New define.
605 (AVR_ISA_XMEGA): Use it.
606 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
608 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
610 * m68hc11.h: Add XGate definitions.
611 (struct m68hc11_opcode): Add xg_mask field.
613 2012-05-14 Catherine Moore <clm@codesourcery.com>
614 Maciej W. Rozycki <macro@codesourcery.com>
615 Rhonda Wittels <rhonda@codesourcery.com>
617 * ppc.h (PPC_OPCODE_VLE): New definition.
618 (PPC_OP_SA): New macro.
619 (PPC_OP_SE_VLE): New macro.
620 (PPC_OP): Use a variable shift amount.
621 (powerpc_operand): Update comments.
622 (PPC_OPSHIFT_INV): New macro.
623 (PPC_OPERAND_CR): Replace with...
624 (PPC_OPERAND_CR_BIT): ...this and
625 (PPC_OPERAND_CR_REG): ...this.
628 2012-05-03 Sean Keys <skeys@ipdatasys.com>
630 * xgate.h: Header file for XGATE assembler.
632 2012-04-27 David S. Miller <davem@davemloft.net>
634 * sparc.h: Document new arg code' )' for crypto RS3
637 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
638 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
639 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
640 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
641 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
642 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
643 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
644 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
645 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
646 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
647 HWCAP_CBCOND, HWCAP_CRC32): New defines.
649 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
651 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
653 2012-02-27 Alan Modra <amodra@gmail.com>
655 * crx.h (cst4_map): Update declaration.
657 2012-02-25 Walter Lee <walt@tilera.com>
659 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
661 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
662 TILEPRO_OPC_LW_TLS_SN.
664 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
666 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
667 (XRELEASE_PREFIX_OPCODE): Likewise.
669 2011-12-08 Andrew Pinski <apinski@cavium.com>
670 Adam Nemet <anemet@caviumnetworks.com>
672 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
673 (INSN_OCTEON2): New macro.
674 (CPU_OCTEON2): New macro.
675 (OPCODE_IS_MEMBER): Add Octeon2.
677 2011-11-29 Andrew Pinski <apinski@cavium.com>
679 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
680 (INSN_OCTEONP): New macro.
681 (CPU_OCTEONP): New macro.
682 (OPCODE_IS_MEMBER): Add Octeon+.
683 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
685 2011-11-01 DJ Delorie <dj@redhat.com>
689 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
691 * mips.h: Fix a typo in description.
693 2011-09-21 David S. Miller <davem@davemloft.net>
695 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
696 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
697 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
698 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
700 2011-08-09 Chao-ying Fu <fu@mips.com>
701 Maciej W. Rozycki <macro@codesourcery.com>
703 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
704 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
705 (INSN_ASE_MASK): Add the MCU bit.
706 (INSN_MCU): New macro.
707 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
708 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
710 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
712 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
713 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
714 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
715 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
716 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
717 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
718 (INSN2_READ_GPR_MMN): Likewise.
719 (INSN2_READ_FPR_D): Change the bit used.
720 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
721 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
722 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
723 (INSN2_COND_BRANCH): Likewise.
724 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
725 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
726 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
727 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
728 (INSN2_MOD_GPR_MN): Likewise.
730 2011-08-05 David S. Miller <davem@davemloft.net>
732 * sparc.h: Document new format codes '4', '5', and '('.
733 (OPF_LOW4, RS3): New macros.
735 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
737 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
738 order of flags documented.
740 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
742 * mips.h: Clarify the description of microMIPS instruction
744 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
746 2011-07-24 Chao-ying Fu <fu@mips.com>
747 Maciej W. Rozycki <macro@codesourcery.com>
749 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
750 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
751 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
752 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
753 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
754 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
755 (OP_MASK_RS3, OP_SH_RS3): Likewise.
756 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
757 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
758 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
759 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
760 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
761 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
762 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
763 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
764 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
765 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
766 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
767 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
768 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
769 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
770 (INSN_WRITE_GPR_S): New macro.
771 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
772 (INSN2_READ_FPR_D): Likewise.
773 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
774 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
775 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
776 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
777 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
778 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
779 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
780 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
781 (CPU_MICROMIPS): New macro.
782 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
783 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
784 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
785 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
786 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
787 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
788 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
789 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
790 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
791 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
792 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
793 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
794 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
795 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
796 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
797 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
798 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
799 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
800 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
801 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
802 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
803 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
804 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
805 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
806 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
807 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
808 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
809 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
810 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
811 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
812 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
813 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
814 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
815 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
816 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
817 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
818 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
819 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
820 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
821 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
822 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
823 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
824 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
825 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
826 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
827 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
828 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
829 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
830 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
831 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
832 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
833 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
834 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
835 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
836 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
837 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
838 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
839 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
840 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
841 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
842 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
843 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
844 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
845 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
846 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
847 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
848 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
849 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
850 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
851 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
852 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
853 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
854 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
855 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
856 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
857 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
858 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
859 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
860 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
861 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
862 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
863 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
864 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
865 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
866 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
867 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
868 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
869 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
870 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
871 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
872 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
873 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
874 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
875 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
876 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
877 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
878 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
879 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
880 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
881 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
882 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
883 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
884 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
885 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
886 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
887 (micromips_opcodes): New declaration.
888 (bfd_micromips_num_opcodes): Likewise.
890 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
892 * mips.h (INSN_TRAP): Rename to...
893 (INSN_NO_DELAY_SLOT): ... this.
894 (INSN_SYNC): Remove macro.
896 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
898 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
899 a duplicate of AVR_ISA_SPM.
901 2011-07-01 Nick Clifton <nickc@redhat.com>
903 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
905 2011-06-18 Robin Getz <robin.getz@analog.com>
907 * bfin.h (is_macmod_signed): New func
909 2011-06-18 Mike Frysinger <vapier@gentoo.org>
911 * bfin.h (is_macmod_pmove): Add missing space before func args.
912 (is_macmod_hmove): Likewise.
914 2011-06-13 Walter Lee <walt@tilera.com>
916 * tilegx.h: New file.
917 * tilepro.h: New file.
919 2011-05-31 Paul Brook <paul@codesourcery.com>
921 * arm.h (ARM_ARCH_V7R_IDIV): Define.
923 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
925 * s390.h: Replace S390_OPERAND_REG_EVEN with
926 S390_OPERAND_REG_PAIR.
928 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
930 * s390.h: Add S390_OPCODE_REG_EVEN flag.
932 2011-04-18 Julian Brown <julian@codesourcery.com>
934 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
936 2011-04-11 Dan McDonald <dan@wellkeeper.com>
939 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
941 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
943 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
944 New instruction set flags.
945 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
947 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
949 * mips.h (M_PREF_AB): New enum value.
951 2011-02-12 Mike Frysinger <vapier@gentoo.org>
953 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
955 (is_macmod_pmove, is_macmod_hmove): New functions.
957 2011-02-11 Mike Frysinger <vapier@gentoo.org>
959 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
961 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
963 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
964 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
966 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
969 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
972 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
975 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
977 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
979 * mips.h: Update commentary after last commit.
981 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
983 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
984 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
985 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
987 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
989 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
991 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
993 * mips.h: Fix previous commit.
995 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
997 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
998 (INSN_LOONGSON_3A): Clear bit 31.
1000 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1003 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1004 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1005 (ARM_ARCH_V6M_ONLY): New define.
1007 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1009 * mips.h (INSN_LOONGSON_3A): Defined.
1010 (CPU_LOONGSON_3A): Defined.
1011 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1013 2010-10-09 Matt Rice <ratmice@gmail.com>
1015 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1016 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1018 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1020 * arm.h (ARM_EXT_VIRT): New define.
1021 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1022 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1025 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1027 * arm.h (ARM_AEXT_ADIV): New define.
1028 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1030 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1032 * arm.h (ARM_EXT_OS): New define.
1033 (ARM_AEXT_V6SM): Likewise.
1034 (ARM_ARCH_V6SM): Likewise.
1036 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1038 * arm.h (ARM_EXT_MP): Add.
1039 (ARM_ARCH_V7A_MP): Likewise.
1041 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1043 * bfin.h: Declare pseudoChr structs/defines.
1045 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1047 * bfin.h: Strip trailing whitespace.
1049 2010-07-29 DJ Delorie <dj@redhat.com>
1051 * rx.h (RX_Operand_Type): Add TwoReg.
1052 (RX_Opcode_ID): Remove ediv and ediv2.
1054 2010-07-27 DJ Delorie <dj@redhat.com>
1056 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1058 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1059 Ina Pandit <ina.pandit@kpitcummins.com>
1061 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1062 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1063 PROCESSOR_V850E2_ALL.
1064 Remove PROCESSOR_V850EA support.
1065 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1066 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1067 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1068 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1069 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1070 V850_OPERAND_PERCENT.
1071 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1073 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1076 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1078 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1079 (MIPS16_INSN_BRANCH): Rename to...
1080 (MIPS16_INSN_COND_BRANCH): ... this.
1082 2010-07-03 Alan Modra <amodra@gmail.com>
1084 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1085 Renumber other PPC_OPCODE defines.
1087 2010-07-03 Alan Modra <amodra@gmail.com>
1089 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1091 2010-06-29 Alan Modra <amodra@gmail.com>
1093 * maxq.h: Delete file.
1095 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1097 * ppc.h (PPC_OPCODE_E500): Define.
1099 2010-05-26 Catherine Moore <clm@codesourcery.com>
1101 * opcode/mips.h (INSN_MIPS16): Remove.
1103 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1105 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1107 2010-04-15 Nick Clifton <nickc@redhat.com>
1109 * alpha.h: Update copyright notice to use GPLv3.
1115 * convex.h: Likewise.
1122 * h8300.h: Likewise.
1129 * m68hc11.h: Likewise.
1135 * mn10200.h: Likewise.
1136 * mn10300.h: Likewise.
1137 * msp430.h: Likewise.
1139 * ns32k.h: Likewise.
1141 * pdp11.h: Likewise.
1148 * score-datadep.h: Likewise.
1149 * score-inst.h: Likewise.
1150 * sparc.h: Likewise.
1151 * spu-insns.h: Likewise.
1153 * tic30.h: Likewise.
1154 * tic4x.h: Likewise.
1155 * tic54x.h: Likewise.
1156 * tic80.h: Likewise.
1160 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1162 * tic6x-control-registers.h, tic6x-insn-formats.h,
1163 tic6x-opcode-table.h, tic6x.h: New.
1165 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1167 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1169 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1171 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1173 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1175 * ia64.h (ia64_find_opcode): Remove argument name.
1176 (ia64_find_next_opcode): Likewise.
1177 (ia64_dis_opcode): Likewise.
1178 (ia64_free_opcode): Likewise.
1179 (ia64_find_dependency): Likewise.
1181 2009-11-22 Doug Evans <dje@sebabeach.org>
1183 * cgen.h: Include bfd_stdint.h.
1184 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1186 2009-11-18 Paul Brook <paul@codesourcery.com>
1188 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1190 2009-11-17 Paul Brook <paul@codesourcery.com>
1191 Daniel Jacobowitz <dan@codesourcery.com>
1193 * arm.h (ARM_EXT_V6_DSP): Define.
1194 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1195 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1197 2009-11-04 DJ Delorie <dj@redhat.com>
1199 * rx.h (rx_decode_opcode) (mvtipl): Add.
1200 (mvtcp, mvfcp, opecp): Remove.
1202 2009-11-02 Paul Brook <paul@codesourcery.com>
1204 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1205 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1206 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1207 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1208 FPU_ARCH_NEON_VFP_V4): Define.
1210 2009-10-23 Doug Evans <dje@sebabeach.org>
1212 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1213 * cgen.h: Update. Improve multi-inclusion macro name.
1215 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1217 * ppc.h (PPC_OPCODE_476): Define.
1219 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1221 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1223 2009-09-29 DJ Delorie <dj@redhat.com>
1227 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1229 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1231 2009-09-21 Ben Elliston <bje@au.ibm.com>
1233 * ppc.h (PPC_OPCODE_PPCA2): New.
1235 2009-09-05 Martin Thuresson <martin@mtme.org>
1237 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1239 2009-08-29 Martin Thuresson <martin@mtme.org>
1241 * tic30.h (template): Rename type template to
1242 insn_template. Updated code to use new name.
1243 * tic54x.h (template): Rename type template to
1246 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1248 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1250 2009-06-11 Anthony Green <green@moxielogic.com>
1252 * moxie.h (MOXIE_F3_PCREL): Define.
1253 (moxie_form3_opc_info): Grow.
1255 2009-06-06 Anthony Green <green@moxielogic.com>
1257 * moxie.h (MOXIE_F1_M): Define.
1259 2009-04-15 Anthony Green <green@moxielogic.com>
1263 2009-04-06 DJ Delorie <dj@redhat.com>
1265 * h8300.h: Add relaxation attributes to MOVA opcodes.
1267 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1269 * ppc.h (ppc_parse_cpu): Declare.
1271 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1273 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1274 and _IMM11 for mbitclr and mbitset.
1275 * score-datadep.h: Update dependency information.
1277 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1279 * ppc.h (PPC_OPCODE_POWER7): New.
1281 2009-02-06 Doug Evans <dje@google.com>
1283 * i386.h: Add comment regarding sse* insns and prefixes.
1285 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1287 * mips.h (INSN_XLR): Define.
1288 (INSN_CHIP_MASK): Update.
1290 (OPCODE_IS_MEMBER): Update.
1291 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1293 2009-01-28 Doug Evans <dje@google.com>
1295 * opcode/i386.h: Add multiple inclusion protection.
1296 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1297 (EDI_REG_NUM): New macros.
1298 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1299 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1300 (REX_PREFIX_P): New macro.
1302 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1304 * ppc.h (struct powerpc_opcode): New field "deprecated".
1305 (PPC_OPCODE_NOPOWER4): Delete.
1307 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1309 * mips.h: Define CPU_R14000, CPU_R16000.
1310 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1312 2008-11-18 Catherine Moore <clm@codesourcery.com>
1314 * arm.h (FPU_NEON_FP16): New.
1315 (FPU_ARCH_NEON_FP16): New.
1317 2008-11-06 Chao-ying Fu <fu@mips.com>
1319 * mips.h: Doucument '1' for 5-bit sync type.
1321 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1323 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1326 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1328 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1330 2008-07-30 Michael J. Eager <eager@eagercon.com>
1332 * ppc.h (PPC_OPCODE_405): Define.
1333 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1335 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1337 * ppc.h (ppc_cpu_t): New typedef.
1338 (struct powerpc_opcode <flags>): Use it.
1339 (struct powerpc_operand <insert, extract>): Likewise.
1340 (struct powerpc_macro <flags>): Likewise.
1342 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1344 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1345 Update comment before MIPS16 field descriptors to mention MIPS16.
1346 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1348 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1349 New bit masks and shift counts for cins and exts.
1351 * mips.h: Document new field descriptors +Q.
1352 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1354 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1356 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1357 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1359 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1361 * ppc.h: (PPC_OPCODE_E500MC): New.
1363 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1365 * i386.h (MAX_OPERANDS): Set to 5.
1366 (MAX_MNEM_SIZE): Changed to 20.
1368 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1370 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1372 2008-03-09 Paul Brook <paul@codesourcery.com>
1374 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1376 2008-03-04 Paul Brook <paul@codesourcery.com>
1378 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1379 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1380 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1382 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1383 Nick Clifton <nickc@redhat.com>
1386 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1387 with a 32-bit displacement but without the top bit of the 4th byte
1390 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1392 * cr16.h (cr16_num_optab): Declared.
1394 2008-02-14 Hakan Ardo <hakan@debian.org>
1397 * avr.h (AVR_ISA_2xxe): Define.
1399 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1401 * mips.h: Update copyright.
1402 (INSN_CHIP_MASK): New macro.
1403 (INSN_OCTEON): New macro.
1404 (CPU_OCTEON): New macro.
1405 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1407 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1409 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1411 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1413 * avr.h (AVR_ISA_USB162): Add new opcode set.
1414 (AVR_ISA_AVR3): Likewise.
1416 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1418 * mips.h (INSN_LOONGSON_2E): New.
1419 (INSN_LOONGSON_2F): New.
1420 (CPU_LOONGSON_2E): New.
1421 (CPU_LOONGSON_2F): New.
1422 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1424 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1426 * mips.h (INSN_ISA*): Redefine certain values as an
1427 enumeration. Update comments.
1428 (mips_isa_table): New.
1429 (ISA_MIPS*): Redefine to match enumeration.
1430 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1433 2007-08-08 Ben Elliston <bje@au.ibm.com>
1435 * ppc.h (PPC_OPCODE_PPCPS): New.
1437 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1439 * m68k.h: Document j K & E.
1441 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1443 * cr16.h: New file for CR16 target.
1445 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1447 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1449 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1451 * m68k.h (mcfisa_c): New.
1452 (mcfusp, mcf_mask): Adjust.
1454 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1456 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1457 (num_powerpc_operands): Declare.
1458 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1459 (PPC_OPERAND_PLUS1): Define.
1461 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1463 * i386.h (REX_MODE64): Renamed to ...
1465 (REX_EXTX): Renamed to ...
1467 (REX_EXTY): Renamed to ...
1469 (REX_EXTZ): Renamed to ...
1472 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1474 * i386.h: Add entries from config/tc-i386.h and move tables
1475 to opcodes/i386-opc.h.
1477 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1479 * i386.h (FloatDR): Removed.
1480 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1482 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1484 * spu-insns.h: Add soma double-float insns.
1486 2007-02-20 Thiemo Seufer <ths@mips.com>
1487 Chao-Ying Fu <fu@mips.com>
1489 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1490 (INSN_DSPR2): Add flag for DSP R2 instructions.
1491 (M_BALIGN): New macro.
1493 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1495 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1496 and Seg3ShortFrom with Shortform.
1498 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1501 * i386.h (i386_optab): Put the real "test" before the pseudo
1504 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1506 * m68k.h (m68010up): OR fido_a.
1508 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1510 * m68k.h (fido_a): New.
1512 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1514 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1515 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1518 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1520 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1522 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1524 * score-inst.h (enum score_insn_type): Add Insn_internal.
1526 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1527 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1528 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1529 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1530 Alan Modra <amodra@bigpond.net.au>
1532 * spu-insns.h: New file.
1535 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1537 * ppc.h (PPC_OPCODE_CELL): Define.
1539 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1541 * i386.h : Modify opcode to support for the change in POPCNT opcode
1542 in amdfam10 architecture.
1544 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1546 * i386.h: Replace CpuMNI with CpuSSSE3.
1548 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1549 Joseph Myers <joseph@codesourcery.com>
1550 Ian Lance Taylor <ian@wasabisystems.com>
1551 Ben Elliston <bje@wasabisystems.com>
1553 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1555 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1557 * score-datadep.h: New file.
1558 * score-inst.h: New file.
1560 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1562 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1563 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1564 movdq2q and movq2dq.
1566 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1567 Michael Meissner <michael.meissner@amd.com>
1569 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1571 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1573 * i386.h (i386_optab): Add "nop" with memory reference.
1575 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1577 * i386.h (i386_optab): Update comment for 64bit NOP.
1579 2006-06-06 Ben Elliston <bje@au.ibm.com>
1580 Anton Blanchard <anton@samba.org>
1582 * ppc.h (PPC_OPCODE_POWER6): Define.
1585 2006-06-05 Thiemo Seufer <ths@mips.com>
1587 * mips.h: Improve description of MT flags.
1589 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1591 * m68k.h (mcf_mask): Define.
1593 2006-05-05 Thiemo Seufer <ths@mips.com>
1594 David Ung <davidu@mips.com>
1596 * mips.h (enum): Add macro M_CACHE_AB.
1598 2006-05-04 Thiemo Seufer <ths@mips.com>
1599 Nigel Stephens <nigel@mips.com>
1600 David Ung <davidu@mips.com>
1602 * mips.h: Add INSN_SMARTMIPS define.
1604 2006-04-30 Thiemo Seufer <ths@mips.com>
1605 David Ung <davidu@mips.com>
1607 * mips.h: Defines udi bits and masks. Add description of
1608 characters which may appear in the args field of udi
1611 2006-04-26 Thiemo Seufer <ths@networkno.de>
1613 * mips.h: Improve comments describing the bitfield instruction
1616 2006-04-26 Julian Brown <julian@codesourcery.com>
1618 * arm.h (FPU_VFP_EXT_V3): Define constant.
1619 (FPU_NEON_EXT_V1): Likewise.
1620 (FPU_VFP_HARD): Update.
1621 (FPU_VFP_V3): Define macro.
1622 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1624 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1626 * avr.h (AVR_ISA_PWMx): New.
1628 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1630 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1631 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1632 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1633 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1634 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1636 2006-03-10 Paul Brook <paul@codesourcery.com>
1638 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1640 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1642 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1643 first. Correct mask of bb "B" opcode.
1645 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1647 * i386.h (i386_optab): Support Intel Merom New Instructions.
1649 2006-02-24 Paul Brook <paul@codesourcery.com>
1651 * arm.h: Add V7 feature bits.
1653 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1655 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1657 2006-01-31 Paul Brook <paul@codesourcery.com>
1658 Richard Earnshaw <rearnsha@arm.com>
1660 * arm.h: Use ARM_CPU_FEATURE.
1661 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1662 (arm_feature_set): Change to a structure.
1663 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1664 ARM_FEATURE): New macros.
1666 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1668 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1669 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1670 (ADD_PC_INCR_OPCODE): Don't define.
1672 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1675 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1677 2005-11-14 David Ung <davidu@mips.com>
1679 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1680 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1681 save/restore encoding of the args field.
1683 2005-10-28 Dave Brolley <brolley@redhat.com>
1685 Contribute the following changes:
1686 2005-02-16 Dave Brolley <brolley@redhat.com>
1688 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1689 cgen_isa_mask_* to cgen_bitset_*.
1692 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1694 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1695 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1696 (CGEN_CPU_TABLE): Make isas a ponter.
1698 2003-09-29 Dave Brolley <brolley@redhat.com>
1700 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1701 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1702 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1704 2002-12-13 Dave Brolley <brolley@redhat.com>
1706 * cgen.h (symcat.h): #include it.
1707 (cgen-bitset.h): #include it.
1708 (CGEN_ATTR_VALUE_TYPE): Now a union.
1709 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1710 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1711 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1712 * cgen-bitset.h: New file.
1714 2005-09-30 Catherine Moore <clm@cm00re.com>
1718 2005-10-24 Jan Beulich <jbeulich@novell.com>
1720 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1723 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1725 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1726 Add FLAG_STRICT to pa10 ftest opcode.
1728 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1730 * hppa.h (pa_opcodes): Remove lha entries.
1732 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1734 * hppa.h (FLAG_STRICT): Revise comment.
1735 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1736 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1739 2005-09-30 Catherine Moore <clm@cm00re.com>
1743 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1745 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1747 2005-09-06 Chao-ying Fu <fu@mips.com>
1749 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1750 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1752 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1753 (INSN_ASE_MASK): Update to include INSN_MT.
1754 (INSN_MT): New define for MT ASE.
1756 2005-08-25 Chao-ying Fu <fu@mips.com>
1758 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1759 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1760 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1761 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1762 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1763 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1765 (INSN_DSP): New define for DSP ASE.
1767 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1771 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1773 * ppc.h (PPC_OPCODE_E300): Define.
1775 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1777 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1779 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1782 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1785 2005-07-27 Jan Beulich <jbeulich@novell.com>
1787 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1788 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1789 Add movq-s as 64-bit variants of movd-s.
1791 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1793 * hppa.h: Fix punctuation in comment.
1795 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1796 implicit space-register addressing. Set space-register bits on opcodes
1797 using implicit space-register addressing. Add various missing pa20
1798 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1799 space-register addressing. Use "fE" instead of "fe" in various
1802 2005-07-18 Jan Beulich <jbeulich@novell.com>
1804 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1806 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1808 * i386.h (i386_optab): Support Intel VMX Instructions.
1810 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1812 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1814 2005-07-05 Jan Beulich <jbeulich@novell.com>
1816 * i386.h (i386_optab): Add new insns.
1818 2005-07-01 Nick Clifton <nickc@redhat.com>
1820 * sparc.h: Add typedefs to structure declarations.
1822 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1825 * i386.h (i386_optab): Update comments for 64bit addressing on
1826 mov. Allow 64bit addressing for mov and movq.
1828 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1830 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1831 respectively, in various floating-point load and store patterns.
1833 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1835 * hppa.h (FLAG_STRICT): Correct comment.
1836 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1837 PA 2.0 mneumonics when equivalent. Entries with cache control
1838 completers now require PA 1.1. Adjust whitespace.
1840 2005-05-19 Anton Blanchard <anton@samba.org>
1842 * ppc.h (PPC_OPCODE_POWER5): Define.
1844 2005-05-10 Nick Clifton <nickc@redhat.com>
1846 * Update the address and phone number of the FSF organization in
1847 the GPL notices in the following files:
1848 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1849 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1850 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1851 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1852 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1853 tic54x.h, tic80.h, v850.h, vax.h
1855 2005-05-09 Jan Beulich <jbeulich@novell.com>
1857 * i386.h (i386_optab): Add ht and hnt.
1859 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1861 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1862 Add xcrypt-ctr. Provide aliases without hyphens.
1864 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1866 Moved from ../ChangeLog
1868 2005-04-12 Paul Brook <paul@codesourcery.com>
1869 * m88k.h: Rename psr macros to avoid conflicts.
1871 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1872 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1873 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1874 and ARM_ARCH_V6ZKT2.
1876 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1877 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1878 Remove redundant instruction types.
1879 (struct argument): X_op - new field.
1880 (struct cst4_entry): Remove.
1881 (no_op_insn): Declare.
1883 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1884 * crx.h (enum argtype): Rename types, remove unused types.
1886 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1887 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1888 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1889 (enum operand_type): Rearrange operands, edit comments.
1890 replace us<N> with ui<N> for unsigned immediate.
1891 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1892 displacements (respectively).
1893 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1894 (instruction type): Add NO_TYPE_INS.
1895 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1896 (operand_entry): New field - 'flags'.
1897 (operand flags): New.
1899 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1900 * crx.h (operand_type): Remove redundant types i3, i4,
1902 Add new unsigned immediate types us3, us4, us5, us16.
1904 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1906 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1907 adjust them accordingly.
1909 2005-04-01 Jan Beulich <jbeulich@novell.com>
1911 * i386.h (i386_optab): Add rdtscp.
1913 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1915 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1916 between memory and segment register. Allow movq for moving between
1917 general-purpose register and segment register.
1919 2005-02-09 Jan Beulich <jbeulich@novell.com>
1922 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1923 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1926 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1928 * m68k.h (m68008, m68ec030, m68882): Remove.
1930 (cpu_m68k, cpu_cf): New.
1931 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1932 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1934 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1936 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1937 * cgen.h (enum cgen_parse_operand_type): Add
1938 CGEN_PARSE_OPERAND_SYMBOLIC.
1940 2005-01-21 Fred Fish <fnf@specifixinc.com>
1942 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1943 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1944 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1946 2005-01-19 Fred Fish <fnf@specifixinc.com>
1948 * mips.h (struct mips_opcode): Add new pinfo2 member.
1949 (INSN_ALIAS): New define for opcode table entries that are
1950 specific instances of another entry, such as 'move' for an 'or'
1951 with a zero operand.
1952 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1953 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1955 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1957 * mips.h (CPU_RM9000): Define.
1958 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1960 2004-11-25 Jan Beulich <jbeulich@novell.com>
1962 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1963 to/from test registers are illegal in 64-bit mode. Add missing
1964 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1965 (previously one had to explicitly encode a rex64 prefix). Re-enable
1966 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1967 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1969 2004-11-23 Jan Beulich <jbeulich@novell.com>
1971 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1972 available only with SSE2. Change the MMX additions introduced by SSE
1973 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1974 instructions by their now designated identifier (since combining i686
1975 and 3DNow! does not really imply 3DNow!A).
1977 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1979 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1980 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1982 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1983 Vineet Sharma <vineets@noida.hcltech.com>
1985 * maxq.h: New file: Disassembly information for the maxq port.
1987 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1989 * i386.h (i386_optab): Put back "movzb".
1991 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1993 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1994 comments. Remove member cris_ver_sim. Add members
1995 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1996 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1997 (struct cris_support_reg, struct cris_cond15): New types.
1998 (cris_conds15): Declare.
1999 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2000 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2001 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2002 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2003 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2004 SIZE_FIELD_UNSIGNED.
2006 2004-11-04 Jan Beulich <jbeulich@novell.com>
2008 * i386.h (sldx_Suf): Remove.
2009 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2010 (q_FP): Define, implying no REX64.
2011 (x_FP, sl_FP): Imply FloatMF.
2012 (i386_optab): Split reg and mem forms of moving from segment registers
2013 so that the memory forms can ignore the 16-/32-bit operand size
2014 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2015 all non-floating-point instructions. Unite 32- and 64-bit forms of
2016 movsx, movzx, and movd. Adjust floating point operations for the above
2017 changes to the *FP macros. Add DefaultSize to floating point control
2018 insns operating on larger memory ranges. Remove left over comments
2019 hinting at certain insns being Intel-syntax ones where the ones
2020 actually meant are already gone.
2022 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2024 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2027 2004-09-30 Paul Brook <paul@codesourcery.com>
2029 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2030 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2032 2004-09-11 Theodore A. Roth <troth@openavr.org>
2034 * avr.h: Add support for
2035 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2037 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2039 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2041 2004-08-24 Dmitry Diky <diwil@spec.ru>
2043 * msp430.h (msp430_opc): Add new instructions.
2044 (msp430_rcodes): Declare new instructions.
2045 (msp430_hcodes): Likewise..
2047 2004-08-13 Nick Clifton <nickc@redhat.com>
2050 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2053 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2055 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2057 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2059 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2061 2004-07-21 Jan Beulich <jbeulich@novell.com>
2063 * i386.h: Adjust instruction descriptions to better match the
2066 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2068 * arm.h: Remove all old content. Replace with architecture defines
2069 from gas/config/tc-arm.c.
2071 2004-07-09 Andreas Schwab <schwab@suse.de>
2073 * m68k.h: Fix comment.
2075 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2079 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2081 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2083 2004-05-24 Peter Barada <peter@the-baradas.com>
2085 * m68k.h: Add 'size' to m68k_opcode.
2087 2004-05-05 Peter Barada <peter@the-baradas.com>
2089 * m68k.h: Switch from ColdFire chip name to core variant.
2091 2004-04-22 Peter Barada <peter@the-baradas.com>
2093 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2094 descriptions for new EMAC cases.
2095 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2096 handle Motorola MAC syntax.
2097 Allow disassembly of ColdFire V4e object files.
2099 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2101 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2103 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2105 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2107 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2109 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2111 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2113 * i386.h (i386_optab): Added xstore/xcrypt insns.
2115 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2117 * h8300.h (32bit ldc/stc): Add relaxing support.
2119 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2121 * h8300.h (BITOP): Pass MEMRELAX flag.
2123 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2125 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2128 For older changes see ChangeLog-9103
2130 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2132 Copying and distribution of this file, with or without modification,
2133 are permitted in any medium without royalty provided the copyright
2134 notice and this notice are preserved.
2140 version-control: never
projects / deliverable / binutils-gdb.git / blob