1 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (AARCH64_FEATURE_V8_1): New.
4 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
6 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
8 * arm.h (ARM_EXT2_V8_2A): New.
11 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
13 * aarch64.h (AARCH64_FEATURE_V8_2): New.
14 (AARCH64_ARCH_V8_2): New.
16 2015-11-11 Alan Modra <amodra@gmail.com>
17 Peter Bergner <bergner@vnet.ibm.com>
19 * ppc.h (PPC_OPCODE_POWER9): New define.
20 (PPC_OPCODE_VSX3): Likewise.
22 2015-11-02 Nick Clifton <nickc@redhat.com>
24 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
26 2015-11-02 Nick Clifton <nickc@redhat.com>
28 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
30 2015-10-28 Yao Qi <yao.qi@linaro.org>
32 * aarch64.h (aarch64_decode_insn): Update declaration.
34 2015-10-07 Yao Qi <yao.qi@linaro.org>
36 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
39 2015-10-07 Yao Qi <yao.qi@linaro.org>
41 * aarch64.h [__cplusplus]: Wrap in extern "C".
43 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
44 Cupertino Miranda <cmiranda@synopsys.com>
46 * arc-func.h: New file.
49 2015-10-02 Yao Qi <yao.qi@linaro.org>
51 * aarch64.h (aarch64_zero_register_p): Move the declaration
54 2015-10-02 Yao Qi <yao.qi@linaro.org>
56 * aarch64.h (aarch64_decode_insn): Declare it.
58 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
60 * s390.h (S390_INSTR_FLAG_HTM): New flag.
61 (S390_INSTR_FLAG_VX): New flag.
62 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
64 2015-09-23 Nick Clifton <nickc@redhat.com>
66 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
69 2015-09-22 Nick Clifton <nickc@redhat.com>
71 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
73 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
75 * visium.h (gen_reg_table): Make static.
76 (fp_reg_table): Likewise.
79 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
81 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
82 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
83 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
84 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
86 2015-07-03 Alan Modra <amodra@gmail.com>
88 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
90 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
91 Cesar Philippidis <cesar@codesourcery.com>
93 * nios2.h (enum iw_format_type): Add R2 formats.
94 (enum overflow_type): Add signed_immed12_overflow and
95 enumeration_overflow for R2.
96 (struct nios2_opcode): Document new argument letters for R2.
97 (REG_3BIT, REG_LDWM, REG_POP): Define.
98 (includes): Include nios2r2.h.
99 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
100 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
101 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
102 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
103 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
104 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
106 * nios2r2.h: New file.
108 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
110 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
111 (ppc_optional_operand_value): New inline function.
113 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
115 * aarch64.h (AARCH64_V8_1): New.
117 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
119 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
120 (ARM_ARCH_V8_1A): New.
121 (ARM_ARCH_V8_1A_FP): New.
122 (ARM_ARCH_V8_1A_SIMD): New.
123 (ARM_ARCH_V8_1A_CRYPTOV1): New.
124 (ARM_FEATURE_CORE): New.
126 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
128 * arm.h (ARM_EXT2_PAN): New.
129 (ARM_FEATURE_CORE_HIGH): New.
131 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
133 * arm.h (ARM_FEATURE_ALL): New.
135 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
137 * aarch64.h (AARCH64_FEATURE_RDMA): New.
139 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
141 * aarch64.h (AARCH64_FEATURE_LOR): New.
143 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
145 * aarch64.h (AARCH64_FEATURE_PAN): New.
146 (aarch64_sys_reg_supported_p): Declare.
147 (aarch64_pstatefield_supported_p): Declare.
149 2015-04-30 DJ Delorie <dj@redhat.com>
151 * rl78.h (RL78_Dis_Isa): New.
152 (rl78_decode_opcode): Add ISA parameter.
154 2015-03-24 Terry Guo <terry.guo@arm.com>
156 * arm.h (arm_feature_set): Extended to provide more available bits.
157 (ARM_ANY): Updated to follow above new definition.
158 (ARM_CPU_HAS_FEATURE): Likewise.
159 (ARM_CPU_IS_ANY): Likewise.
160 (ARM_MERGE_FEATURE_SETS): Likewise.
161 (ARM_CLEAR_FEATURE): Likewise.
162 (ARM_FEATURE): Likewise.
163 (ARM_FEATURE_COPY): New macro.
164 (ARM_FEATURE_EQUAL): Likewise.
165 (ARM_FEATURE_ZERO): Likewise.
166 (ARM_FEATURE_CORE_EQUAL): Likewise.
167 (ARM_FEATURE_LOW): Likewise.
168 (ARM_FEATURE_CORE_LOW): Likewise.
169 (ARM_FEATURE_CORE_COPROC): Likewise.
171 2015-02-19 Pedro Alves <palves@redhat.com>
173 * cgen.h [__cplusplus]: Wrap in extern "C".
174 * msp430-decode.h [__cplusplus]: Likewise.
175 * nios2.h [__cplusplus]: Likewise.
176 * rl78.h [__cplusplus]: Likewise.
177 * rx.h [__cplusplus]: Likewise.
178 * tilegx.h [__cplusplus]: Likewise.
180 2015-01-28 James Bowman <james.bowman@ftdichip.com>
184 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
186 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
188 2015-01-01 Alan Modra <amodra@gmail.com>
190 Update year range in copyright notice of all files.
192 2014-12-27 Anthony Green <green@moxielogic.com>
194 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
195 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
197 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
199 * visium.h: New file.
201 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
203 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
204 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
205 (NIOS2_INSN_OPTARG): Renumber.
207 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
209 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
210 declaration. Fix obsolete comment.
212 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
214 * nios2.h (enum iw_format_type): New.
215 (struct nios2_opcode): Update comments. Add size and format fields.
216 (NIOS2_INSN_OPTARG): New.
217 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
218 (struct nios2_reg): Add regtype field.
219 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
220 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
221 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
222 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
223 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
224 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
225 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
226 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
227 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
228 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
229 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
230 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
231 (OP_MASK_OP, OP_SH_OP): Delete.
232 (OP_MASK_IOP, OP_SH_IOP): Delete.
233 (OP_MASK_IRD, OP_SH_IRD): Delete.
234 (OP_MASK_IRT, OP_SH_IRT): Delete.
235 (OP_MASK_IRS, OP_SH_IRS): Delete.
236 (OP_MASK_ROP, OP_SH_ROP): Delete.
237 (OP_MASK_RRD, OP_SH_RRD): Delete.
238 (OP_MASK_RRT, OP_SH_RRT): Delete.
239 (OP_MASK_RRS, OP_SH_RRS): Delete.
240 (OP_MASK_JOP, OP_SH_JOP): Delete.
241 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
242 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
243 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
244 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
245 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
246 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
247 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
248 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
249 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
250 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
251 (OP_MASK_<insn>, OP_MASK): Delete.
252 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
253 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
254 Include nios2r1.h to define new instruction opcode constants
256 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
257 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
258 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
259 (NUMOPCODES, NUMREGISTERS): Delete.
260 * nios2r1.h: New file.
262 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
264 * sparc.h (HWCAP2_VIS3B): Documentation improved.
266 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
268 * sparc.h (sparc_opcode): new field `hwcaps2'.
269 (HWCAP2_FJATHPLUS): New define.
270 (HWCAP2_VIS3B): Likewise.
271 (HWCAP2_ADP): Likewise.
272 (HWCAP2_SPARC5): Likewise.
273 (HWCAP2_MWAIT): Likewise.
274 (HWCAP2_XMPMUL): Likewise.
275 (HWCAP2_XMONT): Likewise.
276 (HWCAP2_NSEC): Likewise.
277 (HWCAP2_FJATHHPC): Likewise.
278 (HWCAP2_FJDES): Likewise.
279 (HWCAP2_FJAES): Likewise.
280 Document the new operand kind `{', corresponding to the mcdper
281 ancillary state register.
282 Document the new operand kind }, which represents frsd floating
283 point registers (double precision) which must be the same than
284 frs1 in its containing instruction.
286 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
288 * nds32.h: Add new opcode declaration.
290 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
291 Matthew Fortune <matthew.fortune@imgtec.com>
293 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
294 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
295 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
296 +I, +O, +R, +:, +\, +", +;
297 (mips_check_prev_operand): New struct.
298 (INSN2_FORBIDDEN_SLOT): New define.
299 (INSN_ISA32R6): New define.
300 (INSN_ISA64R6): New define.
301 (INSN_UPTO32R6): New define.
302 (INSN_UPTO64R6): New define.
303 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
304 (ISA_MIPS32R6): New define.
305 (ISA_MIPS64R6): New define.
306 (CPU_MIPS32R6): New define.
307 (CPU_MIPS64R6): New define.
308 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
310 2014-09-03 Jiong Wang <jiong.wang@arm.com>
312 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
313 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
314 (aarch64_insn_class): Add lse_atomic.
315 (F_LSE_SZ): New field added.
316 (opcode_has_special_coder): Recognize F_LSE_SZ.
318 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
320 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
323 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
325 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
326 (INSN_LOAD_COPROC): New define.
327 (INSN_COPROC_MOVE_DELAY): Rename to...
328 (INSN_COPROC_MOVE): New define.
330 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
331 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
332 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
333 Soundararajan <Sounderarajan.D@atmel.com>
335 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
336 (AVR_ISA_2xxxa): Define ISA without LPM.
337 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
338 Add doc for contraint used in 16 bit lds/sts.
339 Adjust ISA group for icall, ijmp, pop and push.
340 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
342 2014-05-19 Nick Clifton <nickc@redhat.com>
344 * msp430.h (struct msp430_operand_s): Add vshift field.
346 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
348 * mips.h (INSN_ISA_MASK): Updated.
349 (INSN_ISA32R3): New define.
350 (INSN_ISA32R5): New define.
351 (INSN_ISA64R3): New define.
352 (INSN_ISA64R5): New define.
353 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
354 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
355 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
357 (INSN_UPTO32R3): New define.
358 (INSN_UPTO32R5): New define.
359 (INSN_UPTO64R3): New define.
360 (INSN_UPTO64R5): New define.
361 (ISA_MIPS32R3): New define.
362 (ISA_MIPS32R5): New define.
363 (ISA_MIPS64R3): New define.
364 (ISA_MIPS64R5): New define.
365 (CPU_MIPS32R3): New define.
366 (CPU_MIPS32R5): New define.
367 (CPU_MIPS64R3): New define.
368 (CPU_MIPS64R5): New define.
370 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
372 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
374 2014-04-22 Christian Svensson <blue@cmd.nu>
378 2014-03-05 Alan Modra <amodra@gmail.com>
380 Update copyright years.
382 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
384 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
387 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
388 Wei-Cheng Wang <cole945@gmail.com>
390 * nds32.h: New file for Andes NDS32.
392 2013-12-07 Mike Frysinger <vapier@gentoo.org>
394 * bfin.h: Remove +x file mode.
396 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
398 * aarch64.h (aarch64_pstatefields): Change element type to
401 2013-11-18 Renlin Li <Renlin.Li@arm.com>
403 * arm.h (ARM_AEXT_V7VE): New define.
404 (ARM_ARCH_V7VE): New define.
405 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
407 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
411 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
413 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
414 (aarch64_sys_reg_writeonly_p): Ditto.
416 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
418 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
419 (aarch64_sys_reg_writeonly_p): Ditto.
421 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
423 * aarch64.h (aarch64_sys_reg): New typedef.
424 (aarch64_sys_regs): Change to define with the new type.
425 (aarch64_sys_reg_deprecated_p): Declare.
427 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
429 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
430 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
432 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
434 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
435 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
436 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
437 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
438 For MIPS, update extension character sequences after +.
439 (ASE_MSA): New define.
440 (ASE_MSA64): New define.
441 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
442 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
443 For microMIPS, update extension character sequences after +.
445 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
450 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
452 * mips.h: Remove references to "+I" and imm2_expr.
454 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
456 * mips.h (M_DEXT, M_DINS): Delete.
458 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
460 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
461 (mips_optional_operand_p): New function.
463 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
464 Richard Sandiford <rdsandiford@googlemail.com>
466 * mips.h: Document new VU0 operand characters.
467 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
468 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
469 (OP_REG_R5900_ACC): New mips_reg_operand_types.
470 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
471 (mips_vu0_channel_mask): Declare.
473 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
475 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
476 (mips_int_operand_min, mips_int_operand_max): New functions.
477 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
479 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
481 * mips.h (mips_decode_reg_operand): New function.
482 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
483 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
484 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
486 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
487 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
488 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
489 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
490 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
491 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
492 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
493 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
494 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
495 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
496 macros to cover the gaps.
497 (INSN2_MOD_SP): Replace with...
498 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
499 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
500 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
501 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
502 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
505 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
507 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
508 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
509 (MIPS16_INSN_COND_BRANCH): Delete.
511 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
512 Kirill Yukhin <kirill.yukhin@intel.com>
513 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
515 * i386.h (BND_PREFIX_OPCODE): New.
517 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
519 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
520 OP_SAVE_RESTORE_LIST.
521 (decode_mips16_operand): Declare.
523 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
525 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
526 (mips_operand, mips_int_operand, mips_mapped_int_operand)
527 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
528 (mips_pcrel_operand): New structures.
529 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
530 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
531 (decode_mips_operand, decode_micromips_operand): Declare.
533 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
535 * mips.h: Document MIPS16 "I" opcode.
537 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
539 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
540 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
541 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
542 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
543 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
544 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
545 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
546 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
547 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
548 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
549 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
550 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
551 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
553 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
554 (M_USD_AB): ...these.
556 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
558 * mips.h: Remove documentation of "[" and "]". Update documentation
559 of "k" and the MDMX formats.
561 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
563 * mips.h: Update documentation of "+s" and "+S".
565 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
567 * mips.h: Document "+i".
569 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
571 * mips.h: Remove "mi" documentation. Update "mh" documentation.
572 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
574 (INSN2_WRITE_GPR_MHI): Rename to...
575 (INSN2_WRITE_GPR_MH): ...this.
577 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
579 * mips.h: Remove documentation of "+D" and "+T".
581 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
583 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
584 Use "source" rather than "destination" for microMIPS "G".
586 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
588 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
591 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
593 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
595 2013-06-17 Catherine Moore <clm@codesourcery.com>
596 Maciej W. Rozycki <macro@codesourcery.com>
597 Chao-Ying Fu <fu@mips.com>
599 * mips.h (OP_SH_EVAOFFSET): Define.
600 (OP_MASK_EVAOFFSET): Define.
601 (INSN_ASE_MASK): Delete.
603 (M_CACHEE_AB, M_CACHEE_OB): New.
604 (M_LBE_OB, M_LBE_AB): New.
605 (M_LBUE_OB, M_LBUE_AB): New.
606 (M_LHE_OB, M_LHE_AB): New.
607 (M_LHUE_OB, M_LHUE_AB): New.
608 (M_LLE_AB, M_LLE_OB): New.
609 (M_LWE_OB, M_LWE_AB): New.
610 (M_LWLE_AB, M_LWLE_OB): New.
611 (M_LWRE_AB, M_LWRE_OB): New.
612 (M_PREFE_AB, M_PREFE_OB): New.
613 (M_SCE_AB, M_SCE_OB): New.
614 (M_SBE_OB, M_SBE_AB): New.
615 (M_SHE_OB, M_SHE_AB): New.
616 (M_SWE_OB, M_SWE_AB): New.
617 (M_SWLE_AB, M_SWLE_OB): New.
618 (M_SWRE_AB, M_SWRE_OB): New.
619 (MICROMIPSOP_SH_EVAOFFSET): Define.
620 (MICROMIPSOP_MASK_EVAOFFSET): Define.
622 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
624 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
626 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
628 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
630 2013-05-09 Andrew Pinski <apinski@cavium.com>
632 * mips.h (OP_MASK_CODE10): Correct definition.
633 (OP_SH_CODE10): Likewise.
634 Add a comment that "+J" is used now for OP_*CODE10.
635 (INSN_ASE_MASK): Update.
636 (INSN_VIRT): New macro.
637 (INSN_VIRT64): New macro
639 2013-05-02 Nick Clifton <nickc@redhat.com>
641 * msp430.h: Add patterns for MSP430X instructions.
643 2013-04-06 David S. Miller <davem@davemloft.net>
645 * sparc.h (F_PREFERRED): Define.
646 (F_PREF_ALIAS): Define.
648 2013-04-03 Nick Clifton <nickc@redhat.com>
650 * v850.h (V850_INVERSE_PCREL): Define.
652 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
655 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
657 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
660 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
662 * tic6xc-opcode-table.h: Add 16-bit insns.
663 * tic6x.h: Add support for 16-bit insns.
665 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
667 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
668 and mov.b/w/l Rs,@(d:32,ERd).
670 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
673 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
674 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
675 tic6x_operand_xregpair operand coding type.
676 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
677 opcode field, usu ORXREGD1324 for the src2 operand and remove the
680 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
683 * tic6x.h (enum tic6x_coding_method): Add
684 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
685 separately the msb and lsb of a register pair. This is needed to
686 encode the opcodes in the same way as TI assembler does.
687 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
688 and rsqrdp opcodes to use the new field coding types.
690 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
692 * arm.h (CRC_EXT_ARMV8): New constant.
693 (ARCH_CRC_ARMV8): New macro.
695 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
697 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
699 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
700 Andrew Jenner <andrew@codesourcery.com>
702 Based on patches from Altera Corporation.
706 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
708 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
710 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
713 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
715 2013-01-24 Nick Clifton <nickc@redhat.com>
717 * v850.h: Add e3v5 support.
719 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
721 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
723 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
725 * ppc.h (PPC_OPCODE_POWER8): New define.
726 (PPC_OPCODE_HTM): Likewise.
728 2013-01-10 Will Newton <will.newton@imgtec.com>
732 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
734 * cr16.h (make_instruction): Rename to cr16_make_instruction.
735 (match_opcode): Rename to cr16_match_opcode.
737 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
739 * mips.h: Add support for r5900 instructions including lq and sq.
741 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
743 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
744 (make_instruction,match_opcode): Added function prototypes.
745 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
747 2012-11-23 Alan Modra <amodra@gmail.com>
749 * ppc.h (ppc_parse_cpu): Update prototype.
751 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
753 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
754 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
756 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
758 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
760 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
762 * ia64.h (ia64_opnd): Add new operand types.
764 2012-08-21 David S. Miller <davem@davemloft.net>
766 * sparc.h (F3F4): New macro.
768 2012-08-13 Ian Bolton <ian.bolton@arm.com>
769 Laurent Desnogues <laurent.desnogues@arm.com>
770 Jim MacArthur <jim.macarthur@arm.com>
771 Marcus Shawcroft <marcus.shawcroft@arm.com>
772 Nigel Stephens <nigel.stephens@arm.com>
773 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
774 Richard Earnshaw <rearnsha@arm.com>
775 Sofiane Naci <sofiane.naci@arm.com>
776 Tejas Belagod <tejas.belagod@arm.com>
777 Yufeng Zhang <yufeng.zhang@arm.com>
779 * aarch64.h: New file.
781 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
782 Maciej W. Rozycki <macro@codesourcery.com>
784 * mips.h (mips_opcode): Add the exclusions field.
785 (OPCODE_IS_MEMBER): Remove macro.
786 (cpu_is_member): New inline function.
787 (opcode_is_member): Likewise.
789 2012-07-31 Chao-Ying Fu <fu@mips.com>
790 Catherine Moore <clm@codesourcery.com>
791 Maciej W. Rozycki <macro@codesourcery.com>
793 * mips.h: Document microMIPS DSP ASE usage.
794 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
795 microMIPS DSP ASE support.
796 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
797 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
798 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
799 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
800 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
801 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
802 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
804 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
806 * mips.h: Fix a typo in description.
808 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
810 * avr.h: (AVR_ISA_XCH): New define.
811 (AVR_ISA_XMEGA): Use it.
812 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
814 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
816 * m68hc11.h: Add XGate definitions.
817 (struct m68hc11_opcode): Add xg_mask field.
819 2012-05-14 Catherine Moore <clm@codesourcery.com>
820 Maciej W. Rozycki <macro@codesourcery.com>
821 Rhonda Wittels <rhonda@codesourcery.com>
823 * ppc.h (PPC_OPCODE_VLE): New definition.
824 (PPC_OP_SA): New macro.
825 (PPC_OP_SE_VLE): New macro.
826 (PPC_OP): Use a variable shift amount.
827 (powerpc_operand): Update comments.
828 (PPC_OPSHIFT_INV): New macro.
829 (PPC_OPERAND_CR): Replace with...
830 (PPC_OPERAND_CR_BIT): ...this and
831 (PPC_OPERAND_CR_REG): ...this.
834 2012-05-03 Sean Keys <skeys@ipdatasys.com>
836 * xgate.h: Header file for XGATE assembler.
838 2012-04-27 David S. Miller <davem@davemloft.net>
840 * sparc.h: Document new arg code' )' for crypto RS3
843 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
844 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
845 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
846 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
847 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
848 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
849 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
850 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
851 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
852 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
853 HWCAP_CBCOND, HWCAP_CRC32): New defines.
855 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
857 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
859 2012-02-27 Alan Modra <amodra@gmail.com>
861 * crx.h (cst4_map): Update declaration.
863 2012-02-25 Walter Lee <walt@tilera.com>
865 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
867 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
868 TILEPRO_OPC_LW_TLS_SN.
870 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
872 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
873 (XRELEASE_PREFIX_OPCODE): Likewise.
875 2011-12-08 Andrew Pinski <apinski@cavium.com>
876 Adam Nemet <anemet@caviumnetworks.com>
878 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
879 (INSN_OCTEON2): New macro.
880 (CPU_OCTEON2): New macro.
881 (OPCODE_IS_MEMBER): Add Octeon2.
883 2011-11-29 Andrew Pinski <apinski@cavium.com>
885 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
886 (INSN_OCTEONP): New macro.
887 (CPU_OCTEONP): New macro.
888 (OPCODE_IS_MEMBER): Add Octeon+.
889 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
891 2011-11-01 DJ Delorie <dj@redhat.com>
895 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
897 * mips.h: Fix a typo in description.
899 2011-09-21 David S. Miller <davem@davemloft.net>
901 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
902 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
903 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
904 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
906 2011-08-09 Chao-ying Fu <fu@mips.com>
907 Maciej W. Rozycki <macro@codesourcery.com>
909 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
910 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
911 (INSN_ASE_MASK): Add the MCU bit.
912 (INSN_MCU): New macro.
913 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
914 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
916 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
918 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
919 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
920 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
921 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
922 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
923 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
924 (INSN2_READ_GPR_MMN): Likewise.
925 (INSN2_READ_FPR_D): Change the bit used.
926 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
927 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
928 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
929 (INSN2_COND_BRANCH): Likewise.
930 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
931 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
932 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
933 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
934 (INSN2_MOD_GPR_MN): Likewise.
936 2011-08-05 David S. Miller <davem@davemloft.net>
938 * sparc.h: Document new format codes '4', '5', and '('.
939 (OPF_LOW4, RS3): New macros.
941 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
943 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
944 order of flags documented.
946 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
948 * mips.h: Clarify the description of microMIPS instruction
950 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
952 2011-07-24 Chao-ying Fu <fu@mips.com>
953 Maciej W. Rozycki <macro@codesourcery.com>
955 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
956 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
957 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
958 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
959 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
960 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
961 (OP_MASK_RS3, OP_SH_RS3): Likewise.
962 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
963 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
964 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
965 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
966 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
967 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
968 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
969 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
970 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
971 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
972 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
973 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
974 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
975 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
976 (INSN_WRITE_GPR_S): New macro.
977 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
978 (INSN2_READ_FPR_D): Likewise.
979 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
980 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
981 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
982 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
983 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
984 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
985 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
986 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
987 (CPU_MICROMIPS): New macro.
988 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
989 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
990 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
991 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
992 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
993 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
994 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
995 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
996 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
997 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
998 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
999 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1000 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1001 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1002 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1003 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1004 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1005 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1006 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1007 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1008 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1009 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1010 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1011 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1012 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1013 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1014 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1015 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1016 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1017 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1018 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1019 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1020 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1021 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1022 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1023 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1024 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1025 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1026 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1027 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1028 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1029 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1030 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1031 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1032 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1033 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1034 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1035 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1036 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1037 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1038 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1039 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1040 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1041 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1042 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1043 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1044 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1045 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1046 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1047 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1048 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1049 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1050 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1051 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1052 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1053 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1054 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1055 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1056 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1057 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1058 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1059 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1060 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1061 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1062 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1063 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1064 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1065 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1066 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1067 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1068 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1069 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1070 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1071 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1072 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1073 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1074 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1075 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1076 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1077 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1078 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1079 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1080 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1081 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1082 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1083 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1084 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1085 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1086 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1087 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1088 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1089 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1090 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1091 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1092 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1093 (micromips_opcodes): New declaration.
1094 (bfd_micromips_num_opcodes): Likewise.
1096 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1098 * mips.h (INSN_TRAP): Rename to...
1099 (INSN_NO_DELAY_SLOT): ... this.
1100 (INSN_SYNC): Remove macro.
1102 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1104 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1105 a duplicate of AVR_ISA_SPM.
1107 2011-07-01 Nick Clifton <nickc@redhat.com>
1109 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1111 2011-06-18 Robin Getz <robin.getz@analog.com>
1113 * bfin.h (is_macmod_signed): New func
1115 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1117 * bfin.h (is_macmod_pmove): Add missing space before func args.
1118 (is_macmod_hmove): Likewise.
1120 2011-06-13 Walter Lee <walt@tilera.com>
1122 * tilegx.h: New file.
1123 * tilepro.h: New file.
1125 2011-05-31 Paul Brook <paul@codesourcery.com>
1127 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1129 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1131 * s390.h: Replace S390_OPERAND_REG_EVEN with
1132 S390_OPERAND_REG_PAIR.
1134 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1136 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1138 2011-04-18 Julian Brown <julian@codesourcery.com>
1140 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1142 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1145 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1147 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1149 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1150 New instruction set flags.
1151 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1153 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1155 * mips.h (M_PREF_AB): New enum value.
1157 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1159 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1161 (is_macmod_pmove, is_macmod_hmove): New functions.
1163 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1165 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1167 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1169 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1170 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1172 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1175 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1178 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1181 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1183 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1185 * mips.h: Update commentary after last commit.
1187 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1189 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1190 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1191 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1193 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1195 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1197 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1199 * mips.h: Fix previous commit.
1201 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1203 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1204 (INSN_LOONGSON_3A): Clear bit 31.
1206 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1209 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1210 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1211 (ARM_ARCH_V6M_ONLY): New define.
1213 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1215 * mips.h (INSN_LOONGSON_3A): Defined.
1216 (CPU_LOONGSON_3A): Defined.
1217 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1219 2010-10-09 Matt Rice <ratmice@gmail.com>
1221 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1222 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1224 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1226 * arm.h (ARM_EXT_VIRT): New define.
1227 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1228 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1231 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1233 * arm.h (ARM_AEXT_ADIV): New define.
1234 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1236 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1238 * arm.h (ARM_EXT_OS): New define.
1239 (ARM_AEXT_V6SM): Likewise.
1240 (ARM_ARCH_V6SM): Likewise.
1242 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1244 * arm.h (ARM_EXT_MP): Add.
1245 (ARM_ARCH_V7A_MP): Likewise.
1247 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1249 * bfin.h: Declare pseudoChr structs/defines.
1251 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1253 * bfin.h: Strip trailing whitespace.
1255 2010-07-29 DJ Delorie <dj@redhat.com>
1257 * rx.h (RX_Operand_Type): Add TwoReg.
1258 (RX_Opcode_ID): Remove ediv and ediv2.
1260 2010-07-27 DJ Delorie <dj@redhat.com>
1262 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1264 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1265 Ina Pandit <ina.pandit@kpitcummins.com>
1267 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1268 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1269 PROCESSOR_V850E2_ALL.
1270 Remove PROCESSOR_V850EA support.
1271 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1272 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1273 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1274 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1275 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1276 V850_OPERAND_PERCENT.
1277 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1279 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1282 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1284 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1285 (MIPS16_INSN_BRANCH): Rename to...
1286 (MIPS16_INSN_COND_BRANCH): ... this.
1288 2010-07-03 Alan Modra <amodra@gmail.com>
1290 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1291 Renumber other PPC_OPCODE defines.
1293 2010-07-03 Alan Modra <amodra@gmail.com>
1295 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1297 2010-06-29 Alan Modra <amodra@gmail.com>
1299 * maxq.h: Delete file.
1301 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1303 * ppc.h (PPC_OPCODE_E500): Define.
1305 2010-05-26 Catherine Moore <clm@codesourcery.com>
1307 * opcode/mips.h (INSN_MIPS16): Remove.
1309 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1311 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1313 2010-04-15 Nick Clifton <nickc@redhat.com>
1315 * alpha.h: Update copyright notice to use GPLv3.
1321 * convex.h: Likewise.
1328 * h8300.h: Likewise.
1335 * m68hc11.h: Likewise.
1341 * mn10200.h: Likewise.
1342 * mn10300.h: Likewise.
1343 * msp430.h: Likewise.
1345 * ns32k.h: Likewise.
1347 * pdp11.h: Likewise.
1354 * score-datadep.h: Likewise.
1355 * score-inst.h: Likewise.
1356 * sparc.h: Likewise.
1357 * spu-insns.h: Likewise.
1359 * tic30.h: Likewise.
1360 * tic4x.h: Likewise.
1361 * tic54x.h: Likewise.
1362 * tic80.h: Likewise.
1366 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1368 * tic6x-control-registers.h, tic6x-insn-formats.h,
1369 tic6x-opcode-table.h, tic6x.h: New.
1371 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1373 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1375 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1377 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1379 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1381 * ia64.h (ia64_find_opcode): Remove argument name.
1382 (ia64_find_next_opcode): Likewise.
1383 (ia64_dis_opcode): Likewise.
1384 (ia64_free_opcode): Likewise.
1385 (ia64_find_dependency): Likewise.
1387 2009-11-22 Doug Evans <dje@sebabeach.org>
1389 * cgen.h: Include bfd_stdint.h.
1390 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1392 2009-11-18 Paul Brook <paul@codesourcery.com>
1394 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1396 2009-11-17 Paul Brook <paul@codesourcery.com>
1397 Daniel Jacobowitz <dan@codesourcery.com>
1399 * arm.h (ARM_EXT_V6_DSP): Define.
1400 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1401 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1403 2009-11-04 DJ Delorie <dj@redhat.com>
1405 * rx.h (rx_decode_opcode) (mvtipl): Add.
1406 (mvtcp, mvfcp, opecp): Remove.
1408 2009-11-02 Paul Brook <paul@codesourcery.com>
1410 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1411 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1412 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1413 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1414 FPU_ARCH_NEON_VFP_V4): Define.
1416 2009-10-23 Doug Evans <dje@sebabeach.org>
1418 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1419 * cgen.h: Update. Improve multi-inclusion macro name.
1421 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1423 * ppc.h (PPC_OPCODE_476): Define.
1425 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1427 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1429 2009-09-29 DJ Delorie <dj@redhat.com>
1433 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1435 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1437 2009-09-21 Ben Elliston <bje@au.ibm.com>
1439 * ppc.h (PPC_OPCODE_PPCA2): New.
1441 2009-09-05 Martin Thuresson <martin@mtme.org>
1443 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1445 2009-08-29 Martin Thuresson <martin@mtme.org>
1447 * tic30.h (template): Rename type template to
1448 insn_template. Updated code to use new name.
1449 * tic54x.h (template): Rename type template to
1452 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1454 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1456 2009-06-11 Anthony Green <green@moxielogic.com>
1458 * moxie.h (MOXIE_F3_PCREL): Define.
1459 (moxie_form3_opc_info): Grow.
1461 2009-06-06 Anthony Green <green@moxielogic.com>
1463 * moxie.h (MOXIE_F1_M): Define.
1465 2009-04-15 Anthony Green <green@moxielogic.com>
1469 2009-04-06 DJ Delorie <dj@redhat.com>
1471 * h8300.h: Add relaxation attributes to MOVA opcodes.
1473 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1475 * ppc.h (ppc_parse_cpu): Declare.
1477 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1479 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1480 and _IMM11 for mbitclr and mbitset.
1481 * score-datadep.h: Update dependency information.
1483 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1485 * ppc.h (PPC_OPCODE_POWER7): New.
1487 2009-02-06 Doug Evans <dje@google.com>
1489 * i386.h: Add comment regarding sse* insns and prefixes.
1491 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1493 * mips.h (INSN_XLR): Define.
1494 (INSN_CHIP_MASK): Update.
1496 (OPCODE_IS_MEMBER): Update.
1497 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1499 2009-01-28 Doug Evans <dje@google.com>
1501 * opcode/i386.h: Add multiple inclusion protection.
1502 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1503 (EDI_REG_NUM): New macros.
1504 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1505 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1506 (REX_PREFIX_P): New macro.
1508 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1510 * ppc.h (struct powerpc_opcode): New field "deprecated".
1511 (PPC_OPCODE_NOPOWER4): Delete.
1513 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1515 * mips.h: Define CPU_R14000, CPU_R16000.
1516 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1518 2008-11-18 Catherine Moore <clm@codesourcery.com>
1520 * arm.h (FPU_NEON_FP16): New.
1521 (FPU_ARCH_NEON_FP16): New.
1523 2008-11-06 Chao-ying Fu <fu@mips.com>
1525 * mips.h: Doucument '1' for 5-bit sync type.
1527 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1529 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1532 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1534 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1536 2008-07-30 Michael J. Eager <eager@eagercon.com>
1538 * ppc.h (PPC_OPCODE_405): Define.
1539 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1541 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1543 * ppc.h (ppc_cpu_t): New typedef.
1544 (struct powerpc_opcode <flags>): Use it.
1545 (struct powerpc_operand <insert, extract>): Likewise.
1546 (struct powerpc_macro <flags>): Likewise.
1548 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1550 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1551 Update comment before MIPS16 field descriptors to mention MIPS16.
1552 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1554 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1555 New bit masks and shift counts for cins and exts.
1557 * mips.h: Document new field descriptors +Q.
1558 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1560 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1562 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1563 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1565 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1567 * ppc.h: (PPC_OPCODE_E500MC): New.
1569 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1571 * i386.h (MAX_OPERANDS): Set to 5.
1572 (MAX_MNEM_SIZE): Changed to 20.
1574 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1576 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1578 2008-03-09 Paul Brook <paul@codesourcery.com>
1580 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1582 2008-03-04 Paul Brook <paul@codesourcery.com>
1584 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1585 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1586 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1588 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1589 Nick Clifton <nickc@redhat.com>
1592 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1593 with a 32-bit displacement but without the top bit of the 4th byte
1596 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1598 * cr16.h (cr16_num_optab): Declared.
1600 2008-02-14 Hakan Ardo <hakan@debian.org>
1603 * avr.h (AVR_ISA_2xxe): Define.
1605 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1607 * mips.h: Update copyright.
1608 (INSN_CHIP_MASK): New macro.
1609 (INSN_OCTEON): New macro.
1610 (CPU_OCTEON): New macro.
1611 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1613 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1615 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1617 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1619 * avr.h (AVR_ISA_USB162): Add new opcode set.
1620 (AVR_ISA_AVR3): Likewise.
1622 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1624 * mips.h (INSN_LOONGSON_2E): New.
1625 (INSN_LOONGSON_2F): New.
1626 (CPU_LOONGSON_2E): New.
1627 (CPU_LOONGSON_2F): New.
1628 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1630 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1632 * mips.h (INSN_ISA*): Redefine certain values as an
1633 enumeration. Update comments.
1634 (mips_isa_table): New.
1635 (ISA_MIPS*): Redefine to match enumeration.
1636 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1639 2007-08-08 Ben Elliston <bje@au.ibm.com>
1641 * ppc.h (PPC_OPCODE_PPCPS): New.
1643 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1645 * m68k.h: Document j K & E.
1647 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1649 * cr16.h: New file for CR16 target.
1651 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1653 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1655 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1657 * m68k.h (mcfisa_c): New.
1658 (mcfusp, mcf_mask): Adjust.
1660 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1662 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1663 (num_powerpc_operands): Declare.
1664 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1665 (PPC_OPERAND_PLUS1): Define.
1667 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1669 * i386.h (REX_MODE64): Renamed to ...
1671 (REX_EXTX): Renamed to ...
1673 (REX_EXTY): Renamed to ...
1675 (REX_EXTZ): Renamed to ...
1678 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1680 * i386.h: Add entries from config/tc-i386.h and move tables
1681 to opcodes/i386-opc.h.
1683 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1685 * i386.h (FloatDR): Removed.
1686 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1688 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1690 * spu-insns.h: Add soma double-float insns.
1692 2007-02-20 Thiemo Seufer <ths@mips.com>
1693 Chao-Ying Fu <fu@mips.com>
1695 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1696 (INSN_DSPR2): Add flag for DSP R2 instructions.
1697 (M_BALIGN): New macro.
1699 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1701 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1702 and Seg3ShortFrom with Shortform.
1704 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1707 * i386.h (i386_optab): Put the real "test" before the pseudo
1710 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1712 * m68k.h (m68010up): OR fido_a.
1714 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1716 * m68k.h (fido_a): New.
1718 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1720 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1721 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1724 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1726 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1728 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1730 * score-inst.h (enum score_insn_type): Add Insn_internal.
1732 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1733 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1734 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1735 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1736 Alan Modra <amodra@bigpond.net.au>
1738 * spu-insns.h: New file.
1741 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1743 * ppc.h (PPC_OPCODE_CELL): Define.
1745 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1747 * i386.h : Modify opcode to support for the change in POPCNT opcode
1748 in amdfam10 architecture.
1750 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1752 * i386.h: Replace CpuMNI with CpuSSSE3.
1754 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1755 Joseph Myers <joseph@codesourcery.com>
1756 Ian Lance Taylor <ian@wasabisystems.com>
1757 Ben Elliston <bje@wasabisystems.com>
1759 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1761 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1763 * score-datadep.h: New file.
1764 * score-inst.h: New file.
1766 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1768 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1769 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1770 movdq2q and movq2dq.
1772 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1773 Michael Meissner <michael.meissner@amd.com>
1775 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1777 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1779 * i386.h (i386_optab): Add "nop" with memory reference.
1781 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1783 * i386.h (i386_optab): Update comment for 64bit NOP.
1785 2006-06-06 Ben Elliston <bje@au.ibm.com>
1786 Anton Blanchard <anton@samba.org>
1788 * ppc.h (PPC_OPCODE_POWER6): Define.
1791 2006-06-05 Thiemo Seufer <ths@mips.com>
1793 * mips.h: Improve description of MT flags.
1795 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1797 * m68k.h (mcf_mask): Define.
1799 2006-05-05 Thiemo Seufer <ths@mips.com>
1800 David Ung <davidu@mips.com>
1802 * mips.h (enum): Add macro M_CACHE_AB.
1804 2006-05-04 Thiemo Seufer <ths@mips.com>
1805 Nigel Stephens <nigel@mips.com>
1806 David Ung <davidu@mips.com>
1808 * mips.h: Add INSN_SMARTMIPS define.
1810 2006-04-30 Thiemo Seufer <ths@mips.com>
1811 David Ung <davidu@mips.com>
1813 * mips.h: Defines udi bits and masks. Add description of
1814 characters which may appear in the args field of udi
1817 2006-04-26 Thiemo Seufer <ths@networkno.de>
1819 * mips.h: Improve comments describing the bitfield instruction
1822 2006-04-26 Julian Brown <julian@codesourcery.com>
1824 * arm.h (FPU_VFP_EXT_V3): Define constant.
1825 (FPU_NEON_EXT_V1): Likewise.
1826 (FPU_VFP_HARD): Update.
1827 (FPU_VFP_V3): Define macro.
1828 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1830 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1832 * avr.h (AVR_ISA_PWMx): New.
1834 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1836 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1837 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1838 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1839 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1840 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1842 2006-03-10 Paul Brook <paul@codesourcery.com>
1844 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1846 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1848 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1849 first. Correct mask of bb "B" opcode.
1851 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1853 * i386.h (i386_optab): Support Intel Merom New Instructions.
1855 2006-02-24 Paul Brook <paul@codesourcery.com>
1857 * arm.h: Add V7 feature bits.
1859 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1861 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1863 2006-01-31 Paul Brook <paul@codesourcery.com>
1864 Richard Earnshaw <rearnsha@arm.com>
1866 * arm.h: Use ARM_CPU_FEATURE.
1867 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1868 (arm_feature_set): Change to a structure.
1869 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1870 ARM_FEATURE): New macros.
1872 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1874 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1875 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1876 (ADD_PC_INCR_OPCODE): Don't define.
1878 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1881 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1883 2005-11-14 David Ung <davidu@mips.com>
1885 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1886 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1887 save/restore encoding of the args field.
1889 2005-10-28 Dave Brolley <brolley@redhat.com>
1891 Contribute the following changes:
1892 2005-02-16 Dave Brolley <brolley@redhat.com>
1894 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1895 cgen_isa_mask_* to cgen_bitset_*.
1898 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1900 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1901 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1902 (CGEN_CPU_TABLE): Make isas a ponter.
1904 2003-09-29 Dave Brolley <brolley@redhat.com>
1906 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1907 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1908 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1910 2002-12-13 Dave Brolley <brolley@redhat.com>
1912 * cgen.h (symcat.h): #include it.
1913 (cgen-bitset.h): #include it.
1914 (CGEN_ATTR_VALUE_TYPE): Now a union.
1915 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1916 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1917 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1918 * cgen-bitset.h: New file.
1920 2005-09-30 Catherine Moore <clm@cm00re.com>
1924 2005-10-24 Jan Beulich <jbeulich@novell.com>
1926 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1929 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1931 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1932 Add FLAG_STRICT to pa10 ftest opcode.
1934 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1936 * hppa.h (pa_opcodes): Remove lha entries.
1938 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1940 * hppa.h (FLAG_STRICT): Revise comment.
1941 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1942 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1945 2005-09-30 Catherine Moore <clm@cm00re.com>
1949 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1951 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1953 2005-09-06 Chao-ying Fu <fu@mips.com>
1955 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1956 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1958 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1959 (INSN_ASE_MASK): Update to include INSN_MT.
1960 (INSN_MT): New define for MT ASE.
1962 2005-08-25 Chao-ying Fu <fu@mips.com>
1964 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1965 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1966 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1967 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1968 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1969 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1971 (INSN_DSP): New define for DSP ASE.
1973 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1977 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1979 * ppc.h (PPC_OPCODE_E300): Define.
1981 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1983 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1985 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1988 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1991 2005-07-27 Jan Beulich <jbeulich@novell.com>
1993 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1994 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1995 Add movq-s as 64-bit variants of movd-s.
1997 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1999 * hppa.h: Fix punctuation in comment.
2001 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2002 implicit space-register addressing. Set space-register bits on opcodes
2003 using implicit space-register addressing. Add various missing pa20
2004 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2005 space-register addressing. Use "fE" instead of "fe" in various
2008 2005-07-18 Jan Beulich <jbeulich@novell.com>
2010 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2012 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2014 * i386.h (i386_optab): Support Intel VMX Instructions.
2016 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2018 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2020 2005-07-05 Jan Beulich <jbeulich@novell.com>
2022 * i386.h (i386_optab): Add new insns.
2024 2005-07-01 Nick Clifton <nickc@redhat.com>
2026 * sparc.h: Add typedefs to structure declarations.
2028 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2031 * i386.h (i386_optab): Update comments for 64bit addressing on
2032 mov. Allow 64bit addressing for mov and movq.
2034 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2036 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2037 respectively, in various floating-point load and store patterns.
2039 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2041 * hppa.h (FLAG_STRICT): Correct comment.
2042 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2043 PA 2.0 mneumonics when equivalent. Entries with cache control
2044 completers now require PA 1.1. Adjust whitespace.
2046 2005-05-19 Anton Blanchard <anton@samba.org>
2048 * ppc.h (PPC_OPCODE_POWER5): Define.
2050 2005-05-10 Nick Clifton <nickc@redhat.com>
2052 * Update the address and phone number of the FSF organization in
2053 the GPL notices in the following files:
2054 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2055 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2056 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2057 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2058 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2059 tic54x.h, tic80.h, v850.h, vax.h
2061 2005-05-09 Jan Beulich <jbeulich@novell.com>
2063 * i386.h (i386_optab): Add ht and hnt.
2065 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2067 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2068 Add xcrypt-ctr. Provide aliases without hyphens.
2070 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2072 Moved from ../ChangeLog
2074 2005-04-12 Paul Brook <paul@codesourcery.com>
2075 * m88k.h: Rename psr macros to avoid conflicts.
2077 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2078 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2079 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2080 and ARM_ARCH_V6ZKT2.
2082 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2083 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2084 Remove redundant instruction types.
2085 (struct argument): X_op - new field.
2086 (struct cst4_entry): Remove.
2087 (no_op_insn): Declare.
2089 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2090 * crx.h (enum argtype): Rename types, remove unused types.
2092 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2093 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2094 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2095 (enum operand_type): Rearrange operands, edit comments.
2096 replace us<N> with ui<N> for unsigned immediate.
2097 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2098 displacements (respectively).
2099 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2100 (instruction type): Add NO_TYPE_INS.
2101 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2102 (operand_entry): New field - 'flags'.
2103 (operand flags): New.
2105 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2106 * crx.h (operand_type): Remove redundant types i3, i4,
2108 Add new unsigned immediate types us3, us4, us5, us16.
2110 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2112 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2113 adjust them accordingly.
2115 2005-04-01 Jan Beulich <jbeulich@novell.com>
2117 * i386.h (i386_optab): Add rdtscp.
2119 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2121 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2122 between memory and segment register. Allow movq for moving between
2123 general-purpose register and segment register.
2125 2005-02-09 Jan Beulich <jbeulich@novell.com>
2128 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2129 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2132 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2134 * m68k.h (m68008, m68ec030, m68882): Remove.
2136 (cpu_m68k, cpu_cf): New.
2137 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2138 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2140 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2142 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2143 * cgen.h (enum cgen_parse_operand_type): Add
2144 CGEN_PARSE_OPERAND_SYMBOLIC.
2146 2005-01-21 Fred Fish <fnf@specifixinc.com>
2148 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2149 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2150 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2152 2005-01-19 Fred Fish <fnf@specifixinc.com>
2154 * mips.h (struct mips_opcode): Add new pinfo2 member.
2155 (INSN_ALIAS): New define for opcode table entries that are
2156 specific instances of another entry, such as 'move' for an 'or'
2157 with a zero operand.
2158 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2159 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2161 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2163 * mips.h (CPU_RM9000): Define.
2164 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2166 2004-11-25 Jan Beulich <jbeulich@novell.com>
2168 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2169 to/from test registers are illegal in 64-bit mode. Add missing
2170 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2171 (previously one had to explicitly encode a rex64 prefix). Re-enable
2172 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2173 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2175 2004-11-23 Jan Beulich <jbeulich@novell.com>
2177 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2178 available only with SSE2. Change the MMX additions introduced by SSE
2179 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2180 instructions by their now designated identifier (since combining i686
2181 and 3DNow! does not really imply 3DNow!A).
2183 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2185 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2186 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2188 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2189 Vineet Sharma <vineets@noida.hcltech.com>
2191 * maxq.h: New file: Disassembly information for the maxq port.
2193 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2195 * i386.h (i386_optab): Put back "movzb".
2197 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2199 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2200 comments. Remove member cris_ver_sim. Add members
2201 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2202 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2203 (struct cris_support_reg, struct cris_cond15): New types.
2204 (cris_conds15): Declare.
2205 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2206 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2207 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2208 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2209 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2210 SIZE_FIELD_UNSIGNED.
2212 2004-11-04 Jan Beulich <jbeulich@novell.com>
2214 * i386.h (sldx_Suf): Remove.
2215 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2216 (q_FP): Define, implying no REX64.
2217 (x_FP, sl_FP): Imply FloatMF.
2218 (i386_optab): Split reg and mem forms of moving from segment registers
2219 so that the memory forms can ignore the 16-/32-bit operand size
2220 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2221 all non-floating-point instructions. Unite 32- and 64-bit forms of
2222 movsx, movzx, and movd. Adjust floating point operations for the above
2223 changes to the *FP macros. Add DefaultSize to floating point control
2224 insns operating on larger memory ranges. Remove left over comments
2225 hinting at certain insns being Intel-syntax ones where the ones
2226 actually meant are already gone.
2228 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2230 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2233 2004-09-30 Paul Brook <paul@codesourcery.com>
2235 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2236 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2238 2004-09-11 Theodore A. Roth <troth@openavr.org>
2240 * avr.h: Add support for
2241 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2243 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2245 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2247 2004-08-24 Dmitry Diky <diwil@spec.ru>
2249 * msp430.h (msp430_opc): Add new instructions.
2250 (msp430_rcodes): Declare new instructions.
2251 (msp430_hcodes): Likewise..
2253 2004-08-13 Nick Clifton <nickc@redhat.com>
2256 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2259 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2261 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2263 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2265 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2267 2004-07-21 Jan Beulich <jbeulich@novell.com>
2269 * i386.h: Adjust instruction descriptions to better match the
2272 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2274 * arm.h: Remove all old content. Replace with architecture defines
2275 from gas/config/tc-arm.c.
2277 2004-07-09 Andreas Schwab <schwab@suse.de>
2279 * m68k.h: Fix comment.
2281 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2285 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2287 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2289 2004-05-24 Peter Barada <peter@the-baradas.com>
2291 * m68k.h: Add 'size' to m68k_opcode.
2293 2004-05-05 Peter Barada <peter@the-baradas.com>
2295 * m68k.h: Switch from ColdFire chip name to core variant.
2297 2004-04-22 Peter Barada <peter@the-baradas.com>
2299 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2300 descriptions for new EMAC cases.
2301 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2302 handle Motorola MAC syntax.
2303 Allow disassembly of ColdFire V4e object files.
2305 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2307 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2309 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2311 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2313 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2315 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2317 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2319 * i386.h (i386_optab): Added xstore/xcrypt insns.
2321 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2323 * h8300.h (32bit ldc/stc): Add relaxing support.
2325 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2327 * h8300.h (BITOP): Pass MEMRELAX flag.
2329 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2331 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2334 For older changes see ChangeLog-9103
2336 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2338 Copying and distribution of this file, with or without modification,
2339 are permitted in any medium without royalty provided the copyright
2340 notice and this notice are preserved.
2346 version-control: never
projects / deliverable / binutils-gdb.git / blob