include/opcode/ChangeLog

   1 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
   2
   3         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
   4         Update comment before MIPS16 field descriptors to mention MIPS16.
   5         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
   6         BBIT.
   7         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
   8         New bit masks and shift counts for cins and exts.
   9
  10 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  11
  12         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  13         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
  14
  15 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
  16
  17         * ppc.h: (PPC_OPCODE_E500MC): New.
  18
  19 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         * i386.h (MAX_OPERANDS): Set to 5.
  22         (MAX_MNEM_SIZE): Changed to 20.
  23
  24 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
  25
  26         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
  27
  28 2008-03-09  Paul Brook  <paul@codesourcery.com>
  29
  30         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
  31
  32 2008-03-04  Paul Brook  <paul@codesourcery.com>
  33
  34         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
  35         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
  36         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
  37
  38 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
  39             Nick Clifton  <nickc@redhat.com>
  40
  41         PR 3134
  42         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
  43         with a 32-bit displacement but without the top bit of the 4th byte
  44         set.
  45
  46 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  47
  48         * cr16.h (cr16_num_optab): Declared.
  49
  50 2008-02-14  Hakan Ardo  <hakan@debian.org>
  51
  52         PR gas/2626
  53         * avr.h (AVR_ISA_2xxe): Define.
  54
  55 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
  56
  57         * mips.h: Update copyright.
  58         (INSN_CHIP_MASK): New macro.
  59         (INSN_OCTEON): New macro.
  60         (CPU_OCTEON): New macro.
  61         (OPCODE_IS_MEMBER): Handle Octeon instructions.
  62
  63 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
  64
  65         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
  66
  67 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
  68
  69         * avr.h (AVR_ISA_USB162): Add new opcode set.
  70         (AVR_ISA_AVR3): Likewise.
  71
  72 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  73
  74         * mips.h (INSN_LOONGSON_2E): New.
  75         (INSN_LOONGSON_2F): New.
  76         (CPU_LOONGSON_2E): New.
  77         (CPU_LOONGSON_2F): New.
  78         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
  79
  80 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  81
  82         * mips.h (INSN_ISA*): Redefine certain values as an
  83         enumeration.  Update comments.
  84         (mips_isa_table): New.
  85         (ISA_MIPS*): Redefine to match enumeration.
  86         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  87         values.
  88
  89 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  90
  91         * ppc.h (PPC_OPCODE_PPCPS): New.
  92
  93 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  94
  95         * m68k.h: Document j K & E.
  96
  97 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  98
  99         * cr16.h: New file for CR16 target.
 100
 101 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 102
 103         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 104
 105 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 106
 107         * m68k.h (mcfisa_c): New.
 108         (mcfusp, mcf_mask): Adjust.
 109
 110 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 111
 112         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 113         (num_powerpc_operands): Declare.
 114         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 115         (PPC_OPERAND_PLUS1): Define.
 116
 117 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 118
 119         * i386.h (REX_MODE64): Renamed to ...
 120         (REX_W): This.
 121         (REX_EXTX): Renamed to ...
 122         (REX_R): This.
 123         (REX_EXTY): Renamed to ...
 124         (REX_X): This.
 125         (REX_EXTZ): Renamed to ...
 126         (REX_B): This.
 127
 128 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * i386.h: Add entries from config/tc-i386.h and move tables
 131         to opcodes/i386-opc.h.
 132
 133 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         * i386.h (FloatDR): Removed.
 136         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 137
 138 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 139
 140         * spu-insns.h: Add soma double-float insns.
 141
 142 2007-02-20  Thiemo Seufer  <ths@mips.com>
 143             Chao-Ying Fu  <fu@mips.com>
 144
 145         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 146         (INSN_DSPR2): Add flag for DSP R2 instructions.
 147         (M_BALIGN): New macro.
 148
 149 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 150
 151         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 152         and Seg3ShortFrom with Shortform.
 153
 154 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         PR gas/4027
 157         * i386.h (i386_optab): Put the real "test" before the pseudo
 158         one.
 159
 160 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 161
 162         * m68k.h (m68010up): OR fido_a.
 163
 164 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 165
 166         * m68k.h (fido_a): New.
 167
 168 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 169
 170         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 171         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 172         values.
 173
 174 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 177
 178 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 179
 180         * score-inst.h (enum score_insn_type): Add Insn_internal.
 181
 182 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 183             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 184             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 185             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 186             Alan Modra  <amodra@bigpond.net.au>
 187
 188         * spu-insns.h: New file.
 189         * spu.h: New file.
 190
 191 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 192
 193         * ppc.h (PPC_OPCODE_CELL): Define.
 194
 195 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 196
 197         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 198         in amdfam10 architecture.
 199
 200 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 201
 202         * i386.h: Replace CpuMNI with CpuSSSE3.
 203
 204 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 205             Joseph Myers  <joseph@codesourcery.com>
 206             Ian Lance Taylor  <ian@wasabisystems.com>
 207             Ben Elliston  <bje@wasabisystems.com>
 208
 209         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 210
 211 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 212
 213         * score-datadep.h: New file.
 214         * score-inst.h: New file.
 215
 216 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 219         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 220         movdq2q and movq2dq.
 221
 222 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 223            Michael Meissner             <michael.meissner@amd.com>
 224
 225         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 226
 227 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386.h (i386_optab): Add "nop" with memory reference.
 230
 231 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386.h (i386_optab): Update comment for 64bit NOP.
 234
 235 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 236             Anton Blanchard  <anton@samba.org>
 237
 238         * ppc.h (PPC_OPCODE_POWER6): Define.
 239         Adjust whitespace.
 240
 241 2006-06-05  Thiemo Seufer  <ths@mips.com>
 242
 243         * mips.h: Improve description of MT flags.
 244
 245 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 246
 247         * m68k.h (mcf_mask): Define.
 248
 249 2006-05-05  Thiemo Seufer  <ths@mips.com>
 250             David Ung  <davidu@mips.com>
 251
 252         * mips.h (enum): Add macro M_CACHE_AB.
 253
 254 2006-05-04  Thiemo Seufer  <ths@mips.com>
 255             Nigel Stephens  <nigel@mips.com>
 256             David Ung  <davidu@mips.com>
 257
 258         * mips.h: Add INSN_SMARTMIPS define.
 259
 260 2006-04-30  Thiemo Seufer  <ths@mips.com>
 261             David Ung  <davidu@mips.com>
 262
 263         * mips.h: Defines udi bits and masks.  Add description of
 264         characters which may appear in the args field of udi
 265         instructions.
 266
 267 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 268
 269         * mips.h: Improve comments describing the bitfield instruction
 270         fields.
 271
 272 2006-04-26  Julian Brown  <julian@codesourcery.com>
 273
 274         * arm.h (FPU_VFP_EXT_V3): Define constant.
 275         (FPU_NEON_EXT_V1): Likewise.
 276         (FPU_VFP_HARD): Update.
 277         (FPU_VFP_V3): Define macro.
 278         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 279
 280 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 281
 282         * avr.h (AVR_ISA_PWMx): New.
 283
 284 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 285
 286         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 287         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 288         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 289         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 290         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 291
 292 2006-03-10  Paul Brook  <paul@codesourcery.com>
 293
 294         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 295
 296 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 297
 298         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 299         first.  Correct mask of bb "B" opcode.
 300
 301 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 302
 303         * i386.h (i386_optab): Support Intel Merom New Instructions.
 304
 305 2006-02-24  Paul Brook  <paul@codesourcery.com>
 306
 307         * arm.h: Add V7 feature bits.
 308
 309 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 312
 313 2006-01-31  Paul Brook  <paul@codesourcery.com>
 314         Richard Earnshaw <rearnsha@arm.com>
 315
 316         * arm.h: Use ARM_CPU_FEATURE.
 317         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 318         (arm_feature_set): Change to a structure.
 319         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 320         ARM_FEATURE): New macros.
 321
 322 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 323
 324         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 325         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 326         (ADD_PC_INCR_OPCODE): Don't define.
 327
 328 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR gas/1874
 331         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 332
 333 2005-11-14  David Ung  <davidu@mips.com>
 334
 335         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 336         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 337         save/restore encoding of the args field.
 338
 339 2005-10-28  Dave Brolley  <brolley@redhat.com>
 340
 341         Contribute the following changes:
 342         2005-02-16  Dave Brolley  <brolley@redhat.com>
 343
 344         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 345         cgen_isa_mask_* to cgen_bitset_*.
 346         * cgen.h: Likewise.
 347
 348         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 349
 350         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 351         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 352         (CGEN_CPU_TABLE): Make isas a ponter.
 353
 354         2003-09-29  Dave Brolley  <brolley@redhat.com>
 355
 356         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 357         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 358         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 359
 360         2002-12-13  Dave Brolley  <brolley@redhat.com>
 361
 362         * cgen.h (symcat.h): #include it.
 363         (cgen-bitset.h): #include it.
 364         (CGEN_ATTR_VALUE_TYPE): Now a union.
 365         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 366         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 367         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 368         * cgen-bitset.h: New file.
 369
 370 2005-09-30  Catherine Moore  <clm@cm00re.com>
 371
 372         * bfin.h: New file.
 373
 374 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 375
 376         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 377         indirect operands.
 378
 379 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 380
 381         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 382         Add FLAG_STRICT to pa10 ftest opcode.
 383
 384 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 385
 386         * hppa.h (pa_opcodes): Remove lha entries.
 387
 388 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 389
 390         * hppa.h (FLAG_STRICT): Revise comment.
 391         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 392         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 393         entries for "fdc".
 394
 395 2005-09-30  Catherine Moore  <clm@cm00re.com>
 396
 397         * bfin.h: New file.
 398
 399 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 400
 401         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 402
 403 2005-09-06  Chao-ying Fu  <fu@mips.com>
 404
 405         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 406         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 407         define.
 408         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 409         (INSN_ASE_MASK): Update to include INSN_MT.
 410         (INSN_MT): New define for MT ASE.
 411
 412 2005-08-25  Chao-ying Fu  <fu@mips.com>
 413
 414         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 415         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 416         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 417         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 418         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 419         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 420         instructions.
 421         (INSN_DSP): New define for DSP ASE.
 422
 423 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 424
 425         * a29k.h: Delete.
 426
 427 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 428
 429         * ppc.h (PPC_OPCODE_E300): Define.
 430
 431 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 432
 433         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 434
 435 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 436
 437         PR gas/336
 438         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 439         and pitlb.
 440
 441 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 442
 443         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 444         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 445         Add movq-s as 64-bit variants of movd-s.
 446
 447 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 448
 449         * hppa.h: Fix punctuation in comment.
 450
 451         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 452         implicit space-register addressing.  Set space-register bits on opcodes
 453         using implicit space-register addressing.  Add various missing pa20
 454         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 455         space-register addressing.  Use "fE" instead of "fe" in various
 456         fstw opcodes.
 457
 458 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 459
 460         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 461
 462 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 463
 464         * i386.h (i386_optab): Support Intel VMX Instructions.
 465
 466 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 467
 468         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 469
 470 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 471
 472         * i386.h (i386_optab): Add new insns.
 473
 474 2005-07-01  Nick Clifton  <nickc@redhat.com>
 475
 476         * sparc.h: Add typedefs to structure declarations.
 477
 478 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         PR 1013
 481         * i386.h (i386_optab): Update comments for 64bit addressing on
 482         mov. Allow 64bit addressing for mov and movq.
 483
 484 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 485
 486         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 487         respectively, in various floating-point load and store patterns.
 488
 489 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 490
 491         * hppa.h (FLAG_STRICT): Correct comment.
 492         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 493         PA 2.0 mneumonics when equivalent.  Entries with cache control
 494         completers now require PA 1.1.  Adjust whitespace.
 495
 496 2005-05-19  Anton Blanchard  <anton@samba.org>
 497
 498         * ppc.h (PPC_OPCODE_POWER5): Define.
 499
 500 2005-05-10  Nick Clifton  <nickc@redhat.com>
 501
 502         * Update the address and phone number of the FSF organization in
 503         the GPL notices in the following files:
 504         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 505         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 506         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 507         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 508         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 509         tic54x.h, tic80.h, v850.h, vax.h
 510
 511 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 512
 513         * i386.h (i386_optab): Add ht and hnt.
 514
 515 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 516
 517         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 518         Add xcrypt-ctr.  Provide aliases without hyphens.
 519
 520 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 521
 522         Moved from ../ChangeLog
 523
 524         2005-04-12  Paul Brook  <paul@codesourcery.com>
 525         * m88k.h: Rename psr macros to avoid conflicts.
 526
 527         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 528         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 529         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 530         and ARM_ARCH_V6ZKT2.
 531
 532         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 533         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 534         Remove redundant instruction types.
 535         (struct argument): X_op - new field.
 536         (struct cst4_entry): Remove.
 537         (no_op_insn): Declare.
 538
 539         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 540         * crx.h (enum argtype): Rename types, remove unused types.
 541
 542         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 543         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 544         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 545         (enum operand_type): Rearrange operands, edit comments.
 546         replace us<N> with ui<N> for unsigned immediate.
 547         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 548         displacements (respectively).
 549         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 550         (instruction type): Add NO_TYPE_INS.
 551         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 552         (operand_entry): New field - 'flags'.
 553         (operand flags): New.
 554
 555         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 556         * crx.h (operand_type): Remove redundant types i3, i4,
 557         i5, i8, i12.
 558         Add new unsigned immediate types us3, us4, us5, us16.
 559
 560 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 561
 562         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 563         adjust them accordingly.
 564
 565 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 566
 567         * i386.h (i386_optab): Add rdtscp.
 568
 569 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 572         between memory and segment register. Allow movq for moving between
 573         general-purpose register and segment register.
 574
 575 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 576
 577         PR gas/707
 578         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 579         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 580         fnstsw.
 581
 582 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 583
 584         * m68k.h (m68008, m68ec030, m68882): Remove.
 585         (m68k_mask): New.
 586         (cpu_m68k, cpu_cf): New.
 587         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 588         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 589
 590 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 591
 592         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 593         * cgen.h (enum cgen_parse_operand_type): Add
 594         CGEN_PARSE_OPERAND_SYMBOLIC.
 595
 596 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 597
 598         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 599         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 600         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 601
 602 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 603
 604         * mips.h (struct mips_opcode): Add new pinfo2 member.
 605         (INSN_ALIAS): New define for opcode table entries that are
 606         specific instances of another entry, such as 'move' for an 'or'
 607         with a zero operand.
 608         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 609         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 610
 611 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 612
 613         * mips.h (CPU_RM9000): Define.
 614         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 615
 616 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 617
 618         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 619         to/from test registers are illegal in 64-bit mode. Add missing
 620         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 621         (previously one had to explicitly encode a rex64 prefix). Re-enable
 622         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 623         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 624
 625 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 626
 627         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 628         available only with SSE2. Change the MMX additions introduced by SSE
 629         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 630         instructions by their now designated identifier (since combining i686
 631         and 3DNow! does not really imply 3DNow!A).
 632
 633 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 634
 635         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 636         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 637
 638 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 639             Vineet Sharma      <vineets@noida.hcltech.com>
 640
 641         * maxq.h: New file: Disassembly information for the maxq port.
 642
 643 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386.h (i386_optab): Put back "movzb".
 646
 647 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 648
 649         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 650         comments.  Remove member cris_ver_sim.  Add members
 651         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 652         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 653         (struct cris_support_reg, struct cris_cond15): New types.
 654         (cris_conds15): Declare.
 655         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 656         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 657         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 658         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 659         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 660         SIZE_FIELD_UNSIGNED.
 661
 662 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 663
 664         * i386.h (sldx_Suf): Remove.
 665         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 666         (q_FP): Define, implying no REX64.
 667         (x_FP, sl_FP): Imply FloatMF.
 668         (i386_optab): Split reg and mem forms of moving from segment registers
 669         so that the memory forms can ignore the 16-/32-bit operand size
 670         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 671         all non-floating-point instructions. Unite 32- and 64-bit forms of
 672         movsx, movzx, and movd. Adjust floating point operations for the above
 673         changes to the *FP macros. Add DefaultSize to floating point control
 674         insns operating on larger memory ranges. Remove left over comments
 675         hinting at certain insns being Intel-syntax ones where the ones
 676         actually meant are already gone.
 677
 678 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 679
 680         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 681         instruction type.
 682
 683 2004-09-30  Paul Brook  <paul@codesourcery.com>
 684
 685         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 686         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 687
 688 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 689
 690         * avr.h: Add support for
 691         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 692
 693 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 694
 695         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 696
 697 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 698
 699         * msp430.h (msp430_opc): Add new instructions.
 700         (msp430_rcodes): Declare new instructions.
 701         (msp430_hcodes): Likewise..
 702
 703 2004-08-13  Nick Clifton  <nickc@redhat.com>
 704
 705         PR/301
 706         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 707         processors.
 708
 709 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 710
 711         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 712
 713 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 716
 717 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 718
 719         * i386.h: Adjust instruction descriptions to better match the
 720         specification.
 721
 722 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 723
 724         * arm.h: Remove all old content.  Replace with architecture defines
 725         from gas/config/tc-arm.c.
 726
 727 2004-07-09  Andreas Schwab  <schwab@suse.de>
 728
 729         * m68k.h: Fix comment.
 730
 731 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 732
 733         * crx.h: New file.
 734
 735 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 736
 737         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 738
 739 2004-05-24  Peter Barada  <peter@the-baradas.com>
 740
 741         * m68k.h: Add 'size' to m68k_opcode.
 742
 743 2004-05-05  Peter Barada  <peter@the-baradas.com>
 744
 745         * m68k.h: Switch from ColdFire chip name to core variant.
 746
 747 2004-04-22  Peter Barada  <peter@the-baradas.com>
 748
 749         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 750         descriptions for new EMAC cases.
 751         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 752         handle Motorola MAC syntax.
 753         Allow disassembly of ColdFire V4e object files.
 754
 755 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 756
 757         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 758
 759 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 760
 761         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 762
 763 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 764
 765         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 766
 767 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 768
 769         * i386.h (i386_optab): Added xstore/xcrypt insns.
 770
 771 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 772
 773         * h8300.h (32bit ldc/stc): Add relaxing support.
 774
 775 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 776
 777         * h8300.h (BITOP): Pass MEMRELAX flag.
 778
 779 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 780
 781         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 782         except for the H8S.
 783
 784 For older changes see ChangeLog-9103
 785 \f
 786 Local Variables:
 787 mode: change-log
 788 left-margin: 8
 789 fill-column: 74
 790 version-control: never
 791 End: