include/opcode/ChangeLog

   1 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
   2
   3         * mips.h: Update copyright.
   4         (INSN_CHIP_MASK): New macro.
   5         (INSN_OCTEON): New macro.
   6         (CPU_OCTEON): New macro.
   7         (OPCODE_IS_MEMBER): Handle Octeon instructions.
   8
   9 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  10
  11         * mips.h (INSN_LOONGSON_2E): New.
  12         (INSN_LOONGSON_2F): New.
  13         (CPU_LOONGSON_2E): New.
  14         (CPU_LOONGSON_2F): New.
  15         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
  16
  17 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  18
  19         * mips.h (INSN_ISA*): Redefine certain values as an
  20         enumeration.  Update comments.
  21         (mips_isa_table): New.
  22         (ISA_MIPS*): Redefine to match enumeration.
  23         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  24         values.
  25
  26 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  27
  28         * ppc.h (PPC_OPCODE_PPCPS): New.
  29
  30 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  31
  32         * m68k.h: Document j K & E.
  33
  34 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  35
  36         * cr16.h: New file for CR16 target.
  37
  38 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  39
  40         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  41
  42 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  43
  44         * m68k.h (mcfisa_c): New.
  45         (mcfusp, mcf_mask): Adjust.
  46
  47 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  48
  49         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  50         (num_powerpc_operands): Declare.
  51         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  52         (PPC_OPERAND_PLUS1): Define.
  53
  54 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * i386.h (REX_MODE64): Renamed to ...
  57         (REX_W): This.
  58         (REX_EXTX): Renamed to ...
  59         (REX_R): This.
  60         (REX_EXTY): Renamed to ...
  61         (REX_X): This.
  62         (REX_EXTZ): Renamed to ...
  63         (REX_B): This.
  64
  65 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386.h: Add entries from config/tc-i386.h and move tables
  68         to opcodes/i386-opc.h.
  69
  70 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386.h (FloatDR): Removed.
  73         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  74
  75 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  76
  77         * spu-insns.h: Add soma double-float insns.
  78
  79 2007-02-20  Thiemo Seufer  <ths@mips.com>
  80             Chao-Ying Fu  <fu@mips.com>
  81
  82         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  83         (INSN_DSPR2): Add flag for DSP R2 instructions.
  84         (M_BALIGN): New macro.
  85
  86 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  87
  88         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  89         and Seg3ShortFrom with Shortform.
  90
  91 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         PR gas/4027
  94         * i386.h (i386_optab): Put the real "test" before the pseudo
  95         one.
  96
  97 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  98
  99         * m68k.h (m68010up): OR fido_a.
 100
 101 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 102
 103         * m68k.h (fido_a): New.
 104
 105 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 106
 107         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 108         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 109         values.
 110
 111 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 112
 113         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 114
 115 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 116
 117         * score-inst.h (enum score_insn_type): Add Insn_internal.
 118
 119 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 120             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 121             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 122             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 123             Alan Modra  <amodra@bigpond.net.au>
 124
 125         * spu-insns.h: New file.
 126         * spu.h: New file.
 127
 128 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 129
 130         * ppc.h (PPC_OPCODE_CELL): Define.
 131
 132 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 133
 134         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 135         in amdfam10 architecture.
 136
 137 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386.h: Replace CpuMNI with CpuSSSE3.
 140
 141 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 142             Joseph Myers  <joseph@codesourcery.com>
 143             Ian Lance Taylor  <ian@wasabisystems.com>
 144             Ben Elliston  <bje@wasabisystems.com>
 145
 146         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 147
 148 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 149
 150         * score-datadep.h: New file.
 151         * score-inst.h: New file.
 152
 153 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 156         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 157         movdq2q and movq2dq.
 158
 159 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 160            Michael Meissner             <michael.meissner@amd.com>
 161
 162         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 163
 164 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 165
 166         * i386.h (i386_optab): Add "nop" with memory reference.
 167
 168 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         * i386.h (i386_optab): Update comment for 64bit NOP.
 171
 172 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 173             Anton Blanchard  <anton@samba.org>
 174
 175         * ppc.h (PPC_OPCODE_POWER6): Define.
 176         Adjust whitespace.
 177
 178 2006-06-05  Thiemo Seufer  <ths@mips.com>
 179
 180         * mips.h: Improve description of MT flags.
 181
 182 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 183
 184         * m68k.h (mcf_mask): Define.
 185
 186 2006-05-05  Thiemo Seufer  <ths@mips.com>
 187             David Ung  <davidu@mips.com>
 188
 189         * mips.h (enum): Add macro M_CACHE_AB.
 190
 191 2006-05-04  Thiemo Seufer  <ths@mips.com>
 192             Nigel Stephens  <nigel@mips.com>
 193             David Ung  <davidu@mips.com>
 194
 195         * mips.h: Add INSN_SMARTMIPS define.
 196
 197 2006-04-30  Thiemo Seufer  <ths@mips.com>
 198             David Ung  <davidu@mips.com>
 199
 200         * mips.h: Defines udi bits and masks.  Add description of
 201         characters which may appear in the args field of udi
 202         instructions.
 203
 204 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 205
 206         * mips.h: Improve comments describing the bitfield instruction
 207         fields.
 208
 209 2006-04-26  Julian Brown  <julian@codesourcery.com>
 210
 211         * arm.h (FPU_VFP_EXT_V3): Define constant.
 212         (FPU_NEON_EXT_V1): Likewise.
 213         (FPU_VFP_HARD): Update.
 214         (FPU_VFP_V3): Define macro.
 215         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 216
 217 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 218
 219         * avr.h (AVR_ISA_PWMx): New.
 220
 221 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 222
 223         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 224         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 225         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 226         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 227         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 228
 229 2006-03-10  Paul Brook  <paul@codesourcery.com>
 230
 231         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 232
 233 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 234
 235         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 236         first.  Correct mask of bb "B" opcode.
 237
 238 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 239
 240         * i386.h (i386_optab): Support Intel Merom New Instructions.
 241
 242 2006-02-24  Paul Brook  <paul@codesourcery.com>
 243
 244         * arm.h: Add V7 feature bits.
 245
 246 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 249
 250 2006-01-31  Paul Brook  <paul@codesourcery.com>
 251         Richard Earnshaw <rearnsha@arm.com>
 252
 253         * arm.h: Use ARM_CPU_FEATURE.
 254         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 255         (arm_feature_set): Change to a structure.
 256         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 257         ARM_FEATURE): New macros.
 258
 259 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 260
 261         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 262         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 263         (ADD_PC_INCR_OPCODE): Don't define.
 264
 265 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 266
 267         PR gas/1874
 268         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 269
 270 2005-11-14  David Ung  <davidu@mips.com>
 271
 272         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 273         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 274         save/restore encoding of the args field.
 275
 276 2005-10-28  Dave Brolley  <brolley@redhat.com>
 277
 278         Contribute the following changes:
 279         2005-02-16  Dave Brolley  <brolley@redhat.com>
 280
 281         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 282         cgen_isa_mask_* to cgen_bitset_*.
 283         * cgen.h: Likewise.
 284
 285         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 286
 287         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 288         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 289         (CGEN_CPU_TABLE): Make isas a ponter.
 290
 291         2003-09-29  Dave Brolley  <brolley@redhat.com>
 292
 293         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 294         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 295         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 296
 297         2002-12-13  Dave Brolley  <brolley@redhat.com>
 298
 299         * cgen.h (symcat.h): #include it.
 300         (cgen-bitset.h): #include it.
 301         (CGEN_ATTR_VALUE_TYPE): Now a union.
 302         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 303         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 304         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 305         * cgen-bitset.h: New file.
 306
 307 2005-09-30  Catherine Moore  <clm@cm00re.com>
 308
 309         * bfin.h: New file.
 310
 311 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 312
 313         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 314         indirect operands.
 315
 316 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 317
 318         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 319         Add FLAG_STRICT to pa10 ftest opcode.
 320
 321 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 322
 323         * hppa.h (pa_opcodes): Remove lha entries.
 324
 325 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 326
 327         * hppa.h (FLAG_STRICT): Revise comment.
 328         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 329         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 330         entries for "fdc".
 331
 332 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 333
 334         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 335
 336 2005-09-06  Chao-ying Fu  <fu@mips.com>
 337
 338         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 339         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 340         define.
 341         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 342         (INSN_ASE_MASK): Update to include INSN_MT.
 343         (INSN_MT): New define for MT ASE.
 344
 345 2005-08-25  Chao-ying Fu  <fu@mips.com>
 346
 347         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 348         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 349         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 350         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 351         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 352         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 353         instructions.
 354         (INSN_DSP): New define for DSP ASE.
 355
 356 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 357
 358         * a29k.h: Delete.
 359
 360 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 361
 362         * ppc.h (PPC_OPCODE_E300): Define.
 363
 364 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 365
 366         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 367
 368 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 369
 370         PR gas/336
 371         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 372         and pitlb.
 373
 374 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 375
 376         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 377         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 378         Add movq-s as 64-bit variants of movd-s.
 379
 380 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 381
 382         * hppa.h: Fix punctuation in comment.
 383
 384         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 385         implicit space-register addressing.  Set space-register bits on opcodes
 386         using implicit space-register addressing.  Add various missing pa20
 387         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 388         space-register addressing.  Use "fE" instead of "fe" in various
 389         fstw opcodes.
 390
 391 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 392
 393         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 394
 395 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 396
 397         * i386.h (i386_optab): Support Intel VMX Instructions.
 398
 399 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 400
 401         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 402
 403 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 404
 405         * i386.h (i386_optab): Add new insns.
 406
 407 2005-07-01  Nick Clifton  <nickc@redhat.com>
 408
 409         * sparc.h: Add typedefs to structure declarations.
 410
 411 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         PR 1013
 414         * i386.h (i386_optab): Update comments for 64bit addressing on
 415         mov. Allow 64bit addressing for mov and movq.
 416
 417 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 418
 419         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 420         respectively, in various floating-point load and store patterns.
 421
 422 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (FLAG_STRICT): Correct comment.
 425         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 426         PA 2.0 mneumonics when equivalent.  Entries with cache control
 427         completers now require PA 1.1.  Adjust whitespace.
 428
 429 2005-05-19  Anton Blanchard  <anton@samba.org>
 430
 431         * ppc.h (PPC_OPCODE_POWER5): Define.
 432
 433 2005-05-10  Nick Clifton  <nickc@redhat.com>
 434
 435         * Update the address and phone number of the FSF organization in
 436         the GPL notices in the following files:
 437         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 438         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 439         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 440         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 441         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 442         tic54x.h, tic80.h, v850.h, vax.h
 443
 444 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 445
 446         * i386.h (i386_optab): Add ht and hnt.
 447
 448 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 449
 450         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 451         Add xcrypt-ctr.  Provide aliases without hyphens.
 452
 453 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         Moved from ../ChangeLog
 456
 457         2005-04-12  Paul Brook  <paul@codesourcery.com>
 458         * m88k.h: Rename psr macros to avoid conflicts.
 459
 460         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 461         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 462         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 463         and ARM_ARCH_V6ZKT2.
 464
 465         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 466         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 467         Remove redundant instruction types.
 468         (struct argument): X_op - new field.
 469         (struct cst4_entry): Remove.
 470         (no_op_insn): Declare.
 471
 472         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 473         * crx.h (enum argtype): Rename types, remove unused types.
 474
 475         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 476         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 477         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 478         (enum operand_type): Rearrange operands, edit comments.
 479         replace us<N> with ui<N> for unsigned immediate.
 480         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 481         displacements (respectively).
 482         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 483         (instruction type): Add NO_TYPE_INS.
 484         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 485         (operand_entry): New field - 'flags'.
 486         (operand flags): New.
 487
 488         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 489         * crx.h (operand_type): Remove redundant types i3, i4,
 490         i5, i8, i12.
 491         Add new unsigned immediate types us3, us4, us5, us16.
 492
 493 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 494
 495         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 496         adjust them accordingly.
 497
 498 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 499
 500         * i386.h (i386_optab): Add rdtscp.
 501
 502 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 503
 504         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 505         between memory and segment register. Allow movq for moving between
 506         general-purpose register and segment register.
 507
 508 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 509
 510         PR gas/707
 511         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 512         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 513         fnstsw.
 514
 515 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 516
 517         * m68k.h (m68008, m68ec030, m68882): Remove.
 518         (m68k_mask): New.
 519         (cpu_m68k, cpu_cf): New.
 520         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 521         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 522
 523 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 524
 525         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 526         * cgen.h (enum cgen_parse_operand_type): Add
 527         CGEN_PARSE_OPERAND_SYMBOLIC.
 528
 529 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 530
 531         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 532         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 533         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 534
 535 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 536
 537         * mips.h (struct mips_opcode): Add new pinfo2 member.
 538         (INSN_ALIAS): New define for opcode table entries that are
 539         specific instances of another entry, such as 'move' for an 'or'
 540         with a zero operand.
 541         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 542         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 543
 544 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 545
 546         * mips.h (CPU_RM9000): Define.
 547         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 548
 549 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 550
 551         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 552         to/from test registers are illegal in 64-bit mode. Add missing
 553         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 554         (previously one had to explicitly encode a rex64 prefix). Re-enable
 555         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 556         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 557
 558 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 559
 560         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 561         available only with SSE2. Change the MMX additions introduced by SSE
 562         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 563         instructions by their now designated identifier (since combining i686
 564         and 3DNow! does not really imply 3DNow!A).
 565
 566 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 567
 568         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 569         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 570
 571 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 572             Vineet Sharma      <vineets@noida.hcltech.com>
 573
 574         * maxq.h: New file: Disassembly information for the maxq port.
 575
 576 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         * i386.h (i386_optab): Put back "movzb".
 579
 580 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 581
 582         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 583         comments.  Remove member cris_ver_sim.  Add members
 584         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 585         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 586         (struct cris_support_reg, struct cris_cond15): New types.
 587         (cris_conds15): Declare.
 588         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 589         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 590         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 591         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 592         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 593         SIZE_FIELD_UNSIGNED.
 594
 595 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 596
 597         * i386.h (sldx_Suf): Remove.
 598         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 599         (q_FP): Define, implying no REX64.
 600         (x_FP, sl_FP): Imply FloatMF.
 601         (i386_optab): Split reg and mem forms of moving from segment registers
 602         so that the memory forms can ignore the 16-/32-bit operand size
 603         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 604         all non-floating-point instructions. Unite 32- and 64-bit forms of
 605         movsx, movzx, and movd. Adjust floating point operations for the above
 606         changes to the *FP macros. Add DefaultSize to floating point control
 607         insns operating on larger memory ranges. Remove left over comments
 608         hinting at certain insns being Intel-syntax ones where the ones
 609         actually meant are already gone.
 610
 611 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 612
 613         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 614         instruction type.
 615
 616 2004-09-30  Paul Brook  <paul@codesourcery.com>
 617
 618         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 619         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 620
 621 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 622
 623         * avr.h: Add support for
 624         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 625
 626 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 627
 628         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 629
 630 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 631
 632         * msp430.h (msp430_opc): Add new instructions.
 633         (msp430_rcodes): Declare new instructions.
 634         (msp430_hcodes): Likewise..
 635
 636 2004-08-13  Nick Clifton  <nickc@redhat.com>
 637
 638         PR/301
 639         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 640         processors.
 641
 642 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 643
 644         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 645
 646 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 647
 648         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 649
 650 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 651
 652         * i386.h: Adjust instruction descriptions to better match the
 653         specification.
 654
 655 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 656
 657         * arm.h: Remove all old content.  Replace with architecture defines
 658         from gas/config/tc-arm.c.
 659
 660 2004-07-09  Andreas Schwab  <schwab@suse.de>
 661
 662         * m68k.h: Fix comment.
 663
 664 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 665
 666         * crx.h: New file.
 667
 668 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 669
 670         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 671
 672 2004-05-24  Peter Barada  <peter@the-baradas.com>
 673
 674         * m68k.h: Add 'size' to m68k_opcode.
 675
 676 2004-05-05  Peter Barada  <peter@the-baradas.com>
 677
 678         * m68k.h: Switch from ColdFire chip name to core variant.
 679
 680 2004-04-22  Peter Barada  <peter@the-baradas.com>
 681
 682         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 683         descriptions for new EMAC cases.
 684         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 685         handle Motorola MAC syntax.
 686         Allow disassembly of ColdFire V4e object files.
 687
 688 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 689
 690         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 691
 692 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 693
 694         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 695
 696 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 697
 698         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 699
 700 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 701
 702         * i386.h (i386_optab): Added xstore/xcrypt insns.
 703
 704 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 705
 706         * h8300.h (32bit ldc/stc): Add relaxing support.
 707
 708 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 709
 710         * h8300.h (BITOP): Pass MEMRELAX flag.
 711
 712 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 713
 714         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 715         except for the H8S.
 716
 717 For older changes see ChangeLog-9103
 718 \f
 719 Local Variables:
 720 mode: change-log
 721 left-margin: 8
 722 fill-column: 74
 723 version-control: never
 724 End: