include/opcode/ChangeLog

   1 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
   2
   3         * ppc.h (PPC_OPCODE_CELL): Define.
   4
   5 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
   6
   7         * i386.h :  Modify opcode to support for the change in POPCNT opcode
   8         in amdfam10 architecture.
   9
  10 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386.h: Replace CpuMNI with CpuSSSE3.
  13
  14 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  15             Joseph Myers  <joseph@codesourcery.com>
  16             Ian Lance Taylor  <ian@wasabisystems.com>
  17             Ben Elliston  <bje@wasabisystems.com>
  18
  19         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  20
  21 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  22
  23         * score-datadep.h: New file.
  24         * score-inst.h: New file.
  25
  26 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  29         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  30         movdq2q and movq2dq.
  31
  32 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  33            Michael Meissner             <michael.meissner@amd.com>
  34
  35         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  36
  37 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386.h (i386_optab): Add "nop" with memory reference.
  40
  41 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * i386.h (i386_optab): Update comment for 64bit NOP.
  44
  45 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  46             Anton Blanchard  <anton@samba.org>
  47
  48         * ppc.h (PPC_OPCODE_POWER6): Define.
  49         Adjust whitespace.
  50
  51 2006-06-05  Thiemo Seufer  <ths@mips.com>
  52
  53         * mips.h: Improve description of MT flags.
  54
  55 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  56
  57         * m68k.h (mcf_mask): Define.
  58
  59 2006-05-05  Thiemo Seufer  <ths@mips.com>
  60             David Ung  <davidu@mips.com>
  61
  62         * mips.h (enum): Add macro M_CACHE_AB.
  63
  64 2006-05-04  Thiemo Seufer  <ths@mips.com>
  65             Nigel Stephens  <nigel@mips.com>
  66             David Ung  <davidu@mips.com>
  67
  68         * mips.h: Add INSN_SMARTMIPS define.
  69
  70 2006-04-30  Thiemo Seufer  <ths@mips.com>
  71             David Ung  <davidu@mips.com>
  72
  73         * mips.h: Defines udi bits and masks.  Add description of
  74         characters which may appear in the args field of udi
  75         instructions.
  76
  77 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  78
  79         * mips.h: Improve comments describing the bitfield instruction
  80         fields.
  81
  82 2006-04-26  Julian Brown  <julian@codesourcery.com>
  83
  84         * arm.h (FPU_VFP_EXT_V3): Define constant.
  85         (FPU_NEON_EXT_V1): Likewise.
  86         (FPU_VFP_HARD): Update.
  87         (FPU_VFP_V3): Define macro.
  88         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
  89
  90 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
  91
  92         * avr.h (AVR_ISA_PWMx): New.
  93
  94 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
  95
  96         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
  97         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
  98         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
  99         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 100         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 101
 102 2006-03-10  Paul Brook  <paul@codesourcery.com>
 103
 104         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 105
 106 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 107
 108         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 109         first.  Correct mask of bb "B" opcode.
 110
 111 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 112
 113         * i386.h (i386_optab): Support Intel Merom New Instructions.
 114
 115 2006-02-24  Paul Brook  <paul@codesourcery.com>
 116
 117         * arm.h: Add V7 feature bits.
 118
 119 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 122
 123 2006-01-31  Paul Brook  <paul@codesourcery.com>
 124         Richard Earnshaw <rearnsha@arm.com>
 125
 126         * arm.h: Use ARM_CPU_FEATURE.
 127         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 128         (arm_feature_set): Change to a structure.
 129         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 130         ARM_FEATURE): New macros.
 131
 132 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 133
 134         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 135         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 136         (ADD_PC_INCR_OPCODE): Don't define.
 137
 138 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         PR gas/1874
 141         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 142
 143 2005-11-14  David Ung  <davidu@mips.com>
 144
 145         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 146         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 147         save/restore encoding of the args field.
 148
 149 2005-10-28  Dave Brolley  <brolley@redhat.com>
 150
 151         Contribute the following changes:
 152         2005-02-16  Dave Brolley  <brolley@redhat.com>
 153
 154         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 155         cgen_isa_mask_* to cgen_bitset_*.
 156         * cgen.h: Likewise.
 157
 158         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 159
 160         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 161         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 162         (CGEN_CPU_TABLE): Make isas a ponter.
 163
 164         2003-09-29  Dave Brolley  <brolley@redhat.com>
 165
 166         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 167         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 168         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 169
 170         2002-12-13  Dave Brolley  <brolley@redhat.com>
 171
 172         * cgen.h (symcat.h): #include it.
 173         (cgen-bitset.h): #include it.
 174         (CGEN_ATTR_VALUE_TYPE): Now a union.
 175         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 176         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 177         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 178         * cgen-bitset.h: New file.
 179
 180 2005-09-30  Catherine Moore  <clm@cm00re.com>
 181
 182         * bfin.h: New file.
 183
 184 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 185
 186         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 187         indirect operands.
 188
 189 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 190
 191         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 192         Add FLAG_STRICT to pa10 ftest opcode.
 193
 194 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 195
 196         * hppa.h (pa_opcodes): Remove lha entries.
 197
 198 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 199
 200         * hppa.h (FLAG_STRICT): Revise comment.
 201         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 202         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 203         entries for "fdc".
 204
 205 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 206
 207         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 208
 209 2005-09-06  Chao-ying Fu  <fu@mips.com>
 210
 211         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 212         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 213         define.
 214         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 215         (INSN_ASE_MASK): Update to include INSN_MT.
 216         (INSN_MT): New define for MT ASE.
 217
 218 2005-08-25  Chao-ying Fu  <fu@mips.com>
 219
 220         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 221         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 222         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 223         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 224         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 225         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 226         instructions.
 227         (INSN_DSP): New define for DSP ASE.
 228
 229 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 230
 231         * a29k.h: Delete.
 232
 233 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 234
 235         * ppc.h (PPC_OPCODE_E300): Define.
 236
 237 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 238
 239         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 240
 241 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 242
 243         PR gas/336
 244         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 245         and pitlb.
 246
 247 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 248
 249         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 250         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 251         Add movq-s as 64-bit variants of movd-s.
 252
 253 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 254
 255         * hppa.h: Fix punctuation in comment.
 256
 257         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 258         implicit space-register addressing.  Set space-register bits on opcodes
 259         using implicit space-register addressing.  Add various missing pa20
 260         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 261         space-register addressing.  Use "fE" instead of "fe" in various
 262         fstw opcodes.
 263
 264 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 265
 266         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 267
 268 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 269
 270         * i386.h (i386_optab): Support Intel VMX Instructions.
 271
 272 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 273
 274         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 275
 276 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 277
 278         * i386.h (i386_optab): Add new insns.
 279
 280 2005-07-01  Nick Clifton  <nickc@redhat.com>
 281
 282         * sparc.h: Add typedefs to structure declarations.
 283
 284 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         PR 1013
 287         * i386.h (i386_optab): Update comments for 64bit addressing on
 288         mov. Allow 64bit addressing for mov and movq.
 289
 290 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 291
 292         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 293         respectively, in various floating-point load and store patterns.
 294
 295 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 296
 297         * hppa.h (FLAG_STRICT): Correct comment.
 298         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 299         PA 2.0 mneumonics when equivalent.  Entries with cache control
 300         completers now require PA 1.1.  Adjust whitespace.
 301
 302 2005-05-19  Anton Blanchard  <anton@samba.org>
 303
 304         * ppc.h (PPC_OPCODE_POWER5): Define.
 305
 306 2005-05-10  Nick Clifton  <nickc@redhat.com>
 307
 308         * Update the address and phone number of the FSF organization in
 309         the GPL notices in the following files:
 310         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 311         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 312         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 313         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 314         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 315         tic54x.h, tic80.h, v850.h, vax.h
 316
 317 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 318
 319         * i386.h (i386_optab): Add ht and hnt.
 320
 321 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 322
 323         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 324         Add xcrypt-ctr.  Provide aliases without hyphens.
 325
 326 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         Moved from ../ChangeLog
 329
 330         2005-04-12  Paul Brook  <paul@codesourcery.com>
 331         * m88k.h: Rename psr macros to avoid conflicts.
 332
 333         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 334         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 335         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 336         and ARM_ARCH_V6ZKT2.
 337
 338         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 339         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 340         Remove redundant instruction types.
 341         (struct argument): X_op - new field.
 342         (struct cst4_entry): Remove.
 343         (no_op_insn): Declare.
 344
 345         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 346         * crx.h (enum argtype): Rename types, remove unused types.
 347
 348         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 349         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 350         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 351         (enum operand_type): Rearrange operands, edit comments.
 352         replace us<N> with ui<N> for unsigned immediate.
 353         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 354         displacements (respectively).
 355         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 356         (instruction type): Add NO_TYPE_INS.
 357         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 358         (operand_entry): New field - 'flags'.
 359         (operand flags): New.
 360
 361         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 362         * crx.h (operand_type): Remove redundant types i3, i4,
 363         i5, i8, i12.
 364         Add new unsigned immediate types us3, us4, us5, us16.
 365
 366 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 367
 368         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 369         adjust them accordingly.
 370
 371 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 372
 373         * i386.h (i386_optab): Add rdtscp.
 374
 375 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 376
 377         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 378         between memory and segment register. Allow movq for moving between
 379         general-purpose register and segment register.
 380
 381 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 382
 383         PR gas/707
 384         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 385         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 386         fnstsw.
 387
 388 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 389
 390         * m68k.h (m68008, m68ec030, m68882): Remove.
 391         (m68k_mask): New.
 392         (cpu_m68k, cpu_cf): New.
 393         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 394         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 395
 396 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 397
 398         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 399         * cgen.h (enum cgen_parse_operand_type): Add
 400         CGEN_PARSE_OPERAND_SYMBOLIC.
 401
 402 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 403
 404         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 405         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 406         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 407
 408 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 409
 410         * mips.h (struct mips_opcode): Add new pinfo2 member.
 411         (INSN_ALIAS): New define for opcode table entries that are
 412         specific instances of another entry, such as 'move' for an 'or'
 413         with a zero operand.
 414         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 415         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 416
 417 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 418
 419         * mips.h (CPU_RM9000): Define.
 420         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 421
 422 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 423
 424         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 425         to/from test registers are illegal in 64-bit mode. Add missing
 426         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 427         (previously one had to explicitly encode a rex64 prefix). Re-enable
 428         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 429         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 430
 431 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 432
 433         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 434         available only with SSE2. Change the MMX additions introduced by SSE
 435         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 436         instructions by their now designated identifier (since combining i686
 437         and 3DNow! does not really imply 3DNow!A).
 438
 439 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 440
 441         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 442         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 443
 444 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 445             Vineet Sharma      <vineets@noida.hcltech.com>
 446
 447         * maxq.h: New file: Disassembly information for the maxq port.
 448
 449 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 450
 451         * i386.h (i386_optab): Put back "movzb".
 452
 453 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 454
 455         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 456         comments.  Remove member cris_ver_sim.  Add members
 457         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 458         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 459         (struct cris_support_reg, struct cris_cond15): New types.
 460         (cris_conds15): Declare.
 461         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 462         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 463         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 464         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 465         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 466         SIZE_FIELD_UNSIGNED.
 467
 468 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 469
 470         * i386.h (sldx_Suf): Remove.
 471         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 472         (q_FP): Define, implying no REX64.
 473         (x_FP, sl_FP): Imply FloatMF.
 474         (i386_optab): Split reg and mem forms of moving from segment registers
 475         so that the memory forms can ignore the 16-/32-bit operand size
 476         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 477         all non-floating-point instructions. Unite 32- and 64-bit forms of
 478         movsx, movzx, and movd. Adjust floating point operations for the above
 479         changes to the *FP macros. Add DefaultSize to floating point control
 480         insns operating on larger memory ranges. Remove left over comments
 481         hinting at certain insns being Intel-syntax ones where the ones
 482         actually meant are already gone.
 483
 484 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 485
 486         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 487         instruction type.
 488
 489 2004-09-30  Paul Brook  <paul@codesourcery.com>
 490
 491         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 492         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 493
 494 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 495
 496         * avr.h: Add support for
 497         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 498
 499 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 500
 501         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 502
 503 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 504
 505         * msp430.h (msp430_opc): Add new instructions.
 506         (msp430_rcodes): Declare new instructions.
 507         (msp430_hcodes): Likewise..
 508
 509 2004-08-13  Nick Clifton  <nickc@redhat.com>
 510
 511         PR/301
 512         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 513         processors.
 514
 515 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 516
 517         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 518
 519 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 522
 523 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 524
 525         * i386.h: Adjust instruction descriptions to better match the
 526         specification.
 527
 528 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 529
 530         * arm.h: Remove all old content.  Replace with architecture defines
 531         from gas/config/tc-arm.c.
 532
 533 2004-07-09  Andreas Schwab  <schwab@suse.de>
 534
 535         * m68k.h: Fix comment.
 536
 537 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 538
 539         * crx.h: New file.
 540
 541 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 544
 545 2004-05-24  Peter Barada  <peter@the-baradas.com>
 546
 547         * m68k.h: Add 'size' to m68k_opcode.
 548
 549 2004-05-05  Peter Barada  <peter@the-baradas.com>
 550
 551         * m68k.h: Switch from ColdFire chip name to core variant.
 552
 553 2004-04-22  Peter Barada  <peter@the-baradas.com>
 554
 555         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 556         descriptions for new EMAC cases.
 557         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 558         handle Motorola MAC syntax.
 559         Allow disassembly of ColdFire V4e object files.
 560
 561 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 562
 563         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 564
 565 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 566
 567         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 568
 569 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 570
 571         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 572
 573 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 574
 575         * i386.h (i386_optab): Added xstore/xcrypt insns.
 576
 577 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 578
 579         * h8300.h (32bit ldc/stc): Add relaxing support.
 580
 581 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 582
 583         * h8300.h (BITOP): Pass MEMRELAX flag.
 584
 585 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 586
 587         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 588         except for the H8S.
 589
 590 For older changes see ChangeLog-9103
 591 \f
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 593 mode: change-log
 594 left-margin: 8
 595 fill-column: 74
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