include/opcode/ChangeLog

   1 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   2
   3         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
   4         implicit space-register addressing.  Set space-register bits on opcodes
   5         using implicit space-register addressing.  Add various missing pa20
   6         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
   7         space-register addressing.  Use "fE" instead of "fe" in various
   8         fstw opcodes.
   9
  10 2005-07-18  Jan Beulich  <jbeulich@novell.com>
  11
  12         * i386.h (i386_optab): Operands of aam and aad are unsigned.
  13
  14 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
  15
  16         * i386.h (i386_optab): Support Intel VMX Instructions.
  17
  18 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  19
  20         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
  21
  22 2005-07-05  Jan Beulich  <jbeulich@novell.com>
  23
  24         * i386.h (i386_optab): Add new insns.
  25
  26 2005-07-01  Nick Clifton  <nickc@redhat.com>
  27
  28         * sparc.h: Add typedefs to structure declarations.
  29
  30 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         PR 1013
  33         * i386.h (i386_optab): Update comments for 64bit addressing on
  34         mov. Allow 64bit addressing for mov and movq.
  35
  36 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  37
  38         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  39         respectively, in various floating-point load and store patterns.
  40
  41 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  42
  43         * hppa.h (FLAG_STRICT): Correct comment.
  44         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  45         PA 2.0 mneumonics when equivalent.  Entries with cache control
  46         completers now require PA 1.1.  Adjust whitespace.
  47
  48 2005-05-19  Anton Blanchard  <anton@samba.org>
  49
  50         * ppc.h (PPC_OPCODE_POWER5): Define.
  51
  52 2005-05-10  Nick Clifton  <nickc@redhat.com>
  53
  54         * Update the address and phone number of the FSF organization in
  55         the GPL notices in the following files:
  56         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
  57         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
  58         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
  59         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
  60         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  61         tic54x.h, tic80.h, v850.h, vax.h
  62
  63 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  64
  65         * i386.h (i386_optab): Add ht and hnt.
  66
  67 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  68
  69         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  70         Add xcrypt-ctr.  Provide aliases without hyphens.
  71
  72 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         Moved from ../ChangeLog
  75
  76         2005-04-12  Paul Brook  <paul@codesourcery.com>
  77         * m88k.h: Rename psr macros to avoid conflicts.
  78
  79         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  80         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  81         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  82         and ARM_ARCH_V6ZKT2.
  83
  84         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  85         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  86         Remove redundant instruction types.
  87         (struct argument): X_op - new field.
  88         (struct cst4_entry): Remove.
  89         (no_op_insn): Declare.
  90
  91         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  92         * crx.h (enum argtype): Rename types, remove unused types.
  93
  94         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  95         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  96         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  97         (enum operand_type): Rearrange operands, edit comments.
  98         replace us<N> with ui<N> for unsigned immediate.
  99         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 100         displacements (respectively).
 101         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 102         (instruction type): Add NO_TYPE_INS.
 103         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 104         (operand_entry): New field - 'flags'.
 105         (operand flags): New.
 106
 107         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 108         * crx.h (operand_type): Remove redundant types i3, i4,
 109         i5, i8, i12.
 110         Add new unsigned immediate types us3, us4, us5, us16.
 111
 112 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 113
 114         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 115         adjust them accordingly.
 116
 117 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 118
 119         * i386.h (i386_optab): Add rdtscp.
 120
 121 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 124         between memory and segment register. Allow movq for moving between
 125         general-purpose register and segment register.
 126
 127 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 128
 129         PR gas/707
 130         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 131         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 132         fnstsw.
 133
 134 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 135
 136         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 137         * cgen.h (enum cgen_parse_operand_type): Add
 138         CGEN_PARSE_OPERAND_SYMBOLIC.
 139
 140 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 141
 142         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 143         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 144         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 145
 146 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 147
 148         * mips.h (struct mips_opcode): Add new pinfo2 member.
 149         (INSN_ALIAS): New define for opcode table entries that are
 150         specific instances of another entry, such as 'move' for an 'or'
 151         with a zero operand.
 152         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 153         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 154
 155 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 156
 157         * mips.h (CPU_RM9000): Define.
 158         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 159
 160 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 161
 162         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 163         to/from test registers are illegal in 64-bit mode. Add missing
 164         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 165         (previously one had to explicitly encode a rex64 prefix). Re-enable
 166         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 167         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 168
 169 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 170
 171         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 172         available only with SSE2. Change the MMX additions introduced by SSE
 173         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 174         instructions by their now designated identifier (since combining i686
 175         and 3DNow! does not really imply 3DNow!A).
 176
 177 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 178
 179         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 180         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 181
 182 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 183             Vineet Sharma      <vineets@noida.hcltech.com>
 184
 185         * maxq.h: New file: Disassembly information for the maxq port.
 186
 187 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386.h (i386_optab): Put back "movzb".
 190
 191 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 192
 193         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 194         comments.  Remove member cris_ver_sim.  Add members
 195         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 196         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 197         (struct cris_support_reg, struct cris_cond15): New types.
 198         (cris_conds15): Declare.
 199         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 200         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 201         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 202         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 203         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 204         SIZE_FIELD_UNSIGNED.
 205
 206 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 207
 208         * i386.h (sldx_Suf): Remove.
 209         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 210         (q_FP): Define, implying no REX64.
 211         (x_FP, sl_FP): Imply FloatMF.
 212         (i386_optab): Split reg and mem forms of moving from segment registers
 213         so that the memory forms can ignore the 16-/32-bit operand size
 214         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 215         all non-floating-point instructions. Unite 32- and 64-bit forms of
 216         movsx, movzx, and movd. Adjust floating point operations for the above
 217         changes to the *FP macros. Add DefaultSize to floating point control
 218         insns operating on larger memory ranges. Remove left over comments
 219         hinting at certain insns being Intel-syntax ones where the ones
 220         actually meant are already gone.
 221
 222 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 223
 224         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 225         instruction type.
 226
 227 2004-09-30  Paul Brook  <paul@codesourcery.com>
 228
 229         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 230         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 231
 232 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 233
 234         * avr.h: Add support for
 235         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 236
 237 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 238
 239         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 240
 241 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 242
 243         * msp430.h (msp430_opc): Add new instructions.
 244         (msp430_rcodes): Declare new instructions.
 245         (msp430_hcodes): Likewise..
 246
 247 2004-08-13  Nick Clifton  <nickc@redhat.com>
 248
 249         PR/301
 250         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 251         processors.
 252
 253 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 254
 255         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 256
 257 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 260
 261 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 262
 263         * i386.h: Adjust instruction descriptions to better match the
 264         specification.
 265
 266 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 267
 268         * arm.h: Remove all old content.  Replace with architecture defines
 269         from gas/config/tc-arm.c.
 270
 271 2004-07-09  Andreas Schwab  <schwab@suse.de>
 272
 273         * m68k.h: Fix comment.
 274
 275 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 276
 277         * crx.h: New file.
 278
 279 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 280
 281         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 282
 283 2004-05-24  Peter Barada  <peter@the-baradas.com>
 284
 285         * m68k.h: Add 'size' to m68k_opcode.
 286
 287 2004-05-05  Peter Barada  <peter@the-baradas.com>
 288
 289         * m68k.h: Switch from ColdFire chip name to core variant.
 290
 291 2004-04-22  Peter Barada  <peter@the-baradas.com>
 292
 293         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 294         descriptions for new EMAC cases.
 295         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 296         handle Motorola MAC syntax.
 297         Allow disassembly of ColdFire V4e object files.
 298
 299 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 300
 301         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 302
 303 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 304
 305         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 306
 307 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 308
 309         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 310
 311 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 312
 313         * i386.h (i386_optab): Added xstore/xcrypt insns.
 314
 315 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 316
 317         * h8300.h (32bit ldc/stc): Add relaxing support.
 318
 319 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 320
 321         * h8300.h (BITOP): Pass MEMRELAX flag.
 322
 323 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 324
 325         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 326         except for the H8S.
 327
 328 For older changes see ChangeLog-9103
 329 \f
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 331 mode: change-log
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